Class 21: Testing and Yield

Joseph A. Elias, PhD1

Class 21: Testing and Yield

Topics:1. Intro2. Motivation for Test3. Functional vs. Manufacturing Tests4. Testing Sequence5. Testing Sequence6. Testing Sequence7. Manufacturing Tests and Yield 8. Yield vs. Area and DD9. Yield vs. Process10. Fault Models 11. Fault Models 12. Fault Models 13. Fault Models 14. IDDQ15. JTAG a.k.a. Boundary Scan


Class 21: Testing and YieldMotivation for Test (Weste, c.7)

Testing of a chip can occur at the following stages:1) wafer level2) package chip level3) board level4) system level5) in the field

Approximate cost (1986 $s) to a company to detect a fault (total cost/total chips)1) wafer : $0.01 $0.102) package: $0.10 $1.003) board: $1.00 $104) system: $10 $1005) field: $100 $1000

Thus the motivation to test early to avoid expensive debug effortand to avoid what consequence?


Class 21: Testing and YieldFunctional vs. Manufacturing Tests (Weste, c.7)

Functional tests refer to tests done to verify a variety of requirements:1) verbal (customer to supplier)2) high level test language description (ex., C)3) hardware description language (ex., VHDL)4) look-up table5) a detailed spec which describes what is expected, at what test conditions

Which is probably the best one to choose?

Manufacturing tests refer to tests done before parts reach the customer, and arerelated to known physical causes:1) shorts (ex., inter- and intra-layer)2) opens (ex., missing features, such as metal lines, contacts, diffusions)

These will manifest themselves as:o nodes shorted from power to groundo nodes shorted to each othero inputs floating, outputs not connected


Class 21: Testing and YieldTesting Sequence (Weste, c.7)

A basic overview of how and when a wafer/chip gets tested:(1) Parametric, a.k.a., ETEST, PCMo In-Line: refers to testing at a wafer level, while the wafer is physically within the fab for items such as gate poly width, metal-to-metal shorting, contact resistance, and first pass transistor performance. These are located in the scribe line area.

o End-of-Line: refers to testing at a wafer level, while the wafer is physically within the fab, for an entire suite of test sites. These are located in the scribe line area.

Die

100um mm’s to cm’s

Scribelinearea

Individual test structure



A basic overview of how and when a wafer/chip gets tested:(2) Functional, a.k.a., full chip, first memory testo Memory testing: done on SRAM, DRAM, EEPROM, and/or FLASH portions of chip. In order to test memory by itself, test modes are usually done as part of the design. This will test the functionality of the addressing as well as a defect density monitor

o Logic Testing: done on the entire chip, which accesses the internal circuitry (issues such as addressing, logic patterns, speed are exercised). Can be done in a variety of ways, one of which is JTAG (covered later)

32k x 16

FLASHScribelinearea

4k x16SRAM

Memory

Memory

Logic



A basic overview of how and when a wafer/chip gets tested:(3) Package, board, system, fieldo Package is done by the supplier; demonstrates initial package integrityo Board level takes into account PCB issues, such as handshaking, RC delays, etc.o System level tests whether the chip boots Unix, for example, on a microprocessoro Field is using the chip in the actual end user’s configuration, for example, on the engine block of a Cadillac.

32k x 16

FLASH

4k x16SRAM

Die Package Board


Class 21: Testing and YieldManufacturing Tests and Yield (Weste, c.7)

Yield at the wafer level is defined as

The yield is dependent on area anddefect density, as shown in one form:

Another model for yield is

Yield is also a function of “killer” design or parametric issuesBinning sorts the yield into buckets, or binsParametric vs. Functional yield


Class 21: Testing and YieldYield vs. Area and DD

Yield vs. Area (cm2)

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Yield vs. DD (cm-2)

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•Bigger chips yield lower, all else being equal•Decreasing DD dramatically improves yield•Defect density limited yield is as good as one

can achieve.


Class 21: Testing and Yield

Gate line width distribution Speed distribution of a logic cell

Part fails boot up sequence at 1 GHzlow voltage, and high temperature

Schmoo plot

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VDD

Frequency

Yield vs. Process


Class 21: Testing and YieldFault Models (Weste, c.7)

To test a combinational logic circuitwith n inputs, need 2n vectors

To test a combinational logic circuitwith n inputs, and an m input register,need 2n+m vectors

If n=25 and m=50, at 1us per test,the total test time is 1e9 years



Stuck at Faults: SA1, SA0



S2:Fault which causes a schematic fault tobe “hidden” - how is that?

S1:What problem does this cause?



Open causes combinational logic to becomesequential logic, as one of the transistors istaken out of the logic. Therefore a normalNOR gate becomes:

F = ( (A+B)’ + (A (B’) F ) )


Class 21: Testing and YieldIDDQ Testing (Weste, c.7)

2-Input gateWhat is the gate?What is shorted in this diagram?If testing for quiescent current, whatpattern would be used to find this fault?


Class 21: Testing and YieldJTAG a.k.a. Boundary Scan (Weste, c.7; Martin, p.527)

Joint Test-Action Group standard enables:•connectivity tests between components•sampling and setting chip I/Os•distribution and collection of self-test or built-in self test results•enable automated test equipment to interface to chips•reduce count for testing at wafer level

Documents

Class 21: Testing and Yield