CISC & RISC

CISC & RISCCISC & RISC

By Tue NguyenBy Tue Nguyen

ContentsContents

History of CISC and RISCHistory of CISC and RISC Philosophy behind CISC and RISCPhilosophy behind CISC and RISC SourcesSources

History of CISC and RISCHistory of CISC and RISC

1950s IBM instituted a research program1950s IBM instituted a research program 1964 Release of System/3601964 Release of System/360 Mid-1970s improved measurement tools demonstrated on CISCMid-1970s improved measurement tools demonstrated on CISC 1975 801 project initiated at IBM’s Watson Research Center1975 801 project initiated at IBM’s Watson Research Center 1979 32-bit RISC microprocessor (801) developed led by Joel 1979 32-bit RISC microprocessor (801) developed led by Joel

BirnbaumBirnbaum 1984 MIPS developed at Stanford, as well as projects done at 1984 MIPS developed at Stanford, as well as projects done at

BerkeleyBerkeley 1988 RISC processors had taken over high-end of the workstation 1988 RISC processors had taken over high-end of the workstation

marketmarket Early 1990s IBM’s POWER (Early 1990s IBM’s POWER (PPerformance erformance OOptimization ptimization WWith ith EEnhanced nhanced RRISCISC) architecture introduced w/ the RISC System/6k) architecture introduced w/ the RISC System/6k AIM (Apple, IBM, Motorola) alliance formed, resulting in AIM (Apple, IBM, Motorola) alliance formed, resulting in

PowerPCPowerPC

What is CISC?What is CISC?

CISC stands for Complex Instruction Set ComputerCISC stands for Complex Instruction Set Computer CISC takes its name from the the very large number of CISC takes its name from the the very large number of

instructions (typically hundreds) and addressing modes instructions (typically hundreds) and addressing modes in its ISA.in its ISA.

A 2-operand format, where instructions have a source A 2-operand format, where instructions have a source and a destination. Register to register, register to and a destination. Register to register, register to memory, and memory to register commands. Multiple memory, and memory to register commands. Multiple addressing modes for memory, including specialized addressing modes for memory, including specialized modes for indexing through arrays modes for indexing through arrays

Variable length instructions where the length often Variable length instructions where the length often varies according to the addressing mode varies according to the addressing mode

Instructions which require multiple clock cycles to Instructions which require multiple clock cycles to execute.execute.

CISC design philosophyCISC design philosophy

In the early days of the computer industry, In the early days of the computer industry, compilercompiler technology did not exist. technology did not exist. Programming was done in either Programming was done in either machine codemachine code or in or in assembly languageassembly language. To make . To make programming easier, computer architects programming easier, computer architects created more and more complex instructions created more and more complex instructions which were direct representations of high level which were direct representations of high level functions of high level programming languages. functions of high level programming languages. The attitude at the time was that hardware The attitude at the time was that hardware design was easier than compiler design, so the design was easier than compiler design, so the complexity went into the hardware. complexity went into the hardware.


Another force that encouraged complex instructions was Another force that encouraged complex instructions was the lack of large memories. Since memories were small, it the lack of large memories. Since memories were small, it was advantageous for the density of information held in was advantageous for the density of information held in computer programs to be very high. When every byte of computer programs to be very high. When every byte of memory was precious, eg. your entire system only had a memory was precious, eg. your entire system only had a few kilobytes of storage, it moved the industry to such few kilobytes of storage, it moved the industry to such features as highly encoded instructions, instructions features as highly encoded instructions, instructions which could be variable sized, instructions which did which could be variable sized, instructions which did multiple operations, instructions which did both data multiple operations, instructions which did both data movement and data calculation. At that time, such movement and data calculation. At that time, such instruction packing issues were of higher priority than the instruction packing issues were of higher priority than the ease of decoding such instructions. ease of decoding such instructions.

Memory was not only small, but rather slow since they Memory was not only small, but rather slow since they were implemented using magnetic technology at the time. were implemented using magnetic technology at the time.


CPU designers tried to make instructions that would do CPU designers tried to make instructions that would do as much work as possible. This led to one instruction as much work as possible. This led to one instruction that would do all of the work in a single instruction: load that would do all of the work in a single instruction: load up the two numbers to be added, add them, and then up the two numbers to be added, add them, and then store the result back directly to memory. Another store the result back directly to memory. Another version would read the two numbers from memory, but version would read the two numbers from memory, but store the result in a register. Another version would store the result in a register. Another version would read one from memory and the other from a register read one from memory and the other from a register and store to memory again. And so on. This processor and store to memory again. And so on. This processor design philosophy eventually became known as design philosophy eventually became known as Complex Instruction Set Computer or Complex Instruction Set Computer or CISCCISC for short. for short.

What is RISC?What is RISC?

RISC, or RISC, or Reduced Instruction Set ComputerReduced Instruction Set Computer. is a type of . is a type of microprocessor architecture that utilizes a small, highly-optimized microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of set of instructions, rather than a more specialized set of instructions often found in other types of architectures.instructions often found in other types of architectures.

All instructions are the same lengthAll instructions are the same length Reduced instruction set. Reduced instruction set. Less complex, simple instructions. Less complex, simple instructions. Hardwired control unit and machine instructions. Hardwired control unit and machine instructions. Few addressing schemes for memory operands with only two Few addressing schemes for memory operands with only two

basic instructions, LOAD and STORE basic instructions, LOAD and STORE Many symmetric registers which are organized into a register file.Many symmetric registers which are organized into a register file.

RISC design philosophyRISC design philosophy

In the early 1980s it was thought that existing design of In the early 1980s it was thought that existing design of CISC was reaching theoretical limits. Future CISC was reaching theoretical limits. Future improvements in speed would be primarily through improvements in speed would be primarily through improved "process", that is, smaller features on the improved "process", that is, smaller features on the chip. The complexity of the chip would remain largely chip. The complexity of the chip would remain largely the same, but the smaller size would allow it to run at the same, but the smaller size would allow it to run at higher clock rates. A considerable amount of effort was higher clock rates. A considerable amount of effort was put into designing chips for parallel computing, with put into designing chips for parallel computing, with built-in communications links. Instead of making faster built-in communications links. Instead of making faster chips, a large number of chips would be used, dividing chips, a large number of chips would be used, dividing up problems among them. up problems among them.

RISC design philosophyRISC design philosophy

One idea was to include a pipeline which would break down One idea was to include a pipeline which would break down instructions into steps, and work on one step of several different instructions into steps, and work on one step of several different instructions at the same time. A normal processor might read an instructions at the same time. A normal processor might read an instruction, decode it, fetch the memory the instruction asked for, instruction, decode it, fetch the memory the instruction asked for, perform the operation, and then write the results back out. The perform the operation, and then write the results back out. The key to pipelining is the observation that the processor can start key to pipelining is the observation that the processor can start reading the next instruction as soon as it finishes reading the last, reading the next instruction as soon as it finishes reading the last, meaning that there are now two instructions being worked on (one meaning that there are now two instructions being worked on (one is being read, the next is being decoded), and after another cycle is being read, the next is being decoded), and after another cycle there will be three. While no single instruction is completed any there will be three. While no single instruction is completed any faster, the faster, the nextnext instruction would complete right after the previous instruction would complete right after the previous one. The illusion was of a much faster system, and more efficient one. The illusion was of a much faster system, and more efficient utilization of processor resources. utilization of processor resources.

PipeliningPipelining RISC Pipelines

A RISC processor pipeline operates in much the same way, although the stages in the pipeline are different. While different processors have different numbers of steps, they are basically variations of these five, used in the MIPS R3000 processor:

- fetch instructions from memory - read registers and decode the instruction - execute the instruction or calculate an address - access an operand in data memory - write the result into a register

CISC versus RISCCISC versus RISC

CISCCISC RISCRISC

Emphasis on hardwareEmphasis on hardware Emphasis on softwareEmphasis on software

Includes multi-clockIncludes multi-clockcomplex instructionscomplex instructions

Single-clock,Single-clock,reduced instruction onlyreduced instruction only

Memory-to-memory:Memory-to-memory:"LOAD" and "STORE""LOAD" and "STORE"incorporated in instructionsincorporated in instructions

Register to register:Register to register:"LOAD" and "STORE""LOAD" and "STORE"are independent instructionsare independent instructions

Small code sizes,Small code sizes,high cycles per secondhigh cycles per second

Low cycles per second,Low cycles per second,large code sizeslarge code sizes

Transistors used for storingTransistors used for storingcomplex instructionscomplex instructions

Spends more transistorsSpends more transistorson memory registerson memory registers

Modern Day Modern Day AdvancementAdvancement

As memory speed increased, and high-level languages displaced As memory speed increased, and high-level languages displaced assembly language, the major reasons for CISC began to assembly language, the major reasons for CISC began to disappear, and computer designers began to look at ways disappear, and computer designers began to look at ways computer performance could be optimized beyond just making computer performance could be optimized beyond just making faster hardware.faster hardware.

One of their key realizations was that a sequence of simple One of their key realizations was that a sequence of simple instructions produces the same results as a sequence of complex instructions produces the same results as a sequence of complex instructions, but can be implemented with a simpler (and faster) instructions, but can be implemented with a simpler (and faster) hardware design. (Assuming that memory can keep up.) RISC hardware design. (Assuming that memory can keep up.) RISC (Reduced Instruction Set Computers) processors were the result.(Reduced Instruction Set Computers) processors were the result.

CISC and RISC implementations are becoming more and more CISC and RISC implementations are becoming more and more alike. Many of today’s RISC chips support as many instructions as alike. Many of today’s RISC chips support as many instructions as yesterday's CISC chips. And today's CISC chips use many yesterday's CISC chips. And today's CISC chips use many techniques formerly associated with RISC chips.techniques formerly associated with RISC chips.


CISC and RISC ConvergenceCISC and RISC ConvergenceState of the art processor technology has changed State of the art processor technology has changed significantly since RISC chips were first introduced in significantly since RISC chips were first introduced in the early '80s. Because a number of advancements are the early '80s. Because a number of advancements are used by both RISC used by both RISC andand CISC processors, the lines CISC processors, the lines between the two architectures have begun to blur. In between the two architectures have begun to blur. In fact, the two architectures almost seem to have fact, the two architectures almost seem to have adopted the strategies of the other. Because processor adopted the strategies of the other. Because processor speeds have increased, CISC chips are now able to speeds have increased, CISC chips are now able to execute more than one instruction within a single clock. execute more than one instruction within a single clock. This also allows CISC chips to make use of pipelining. This also allows CISC chips to make use of pipelining. With other technological improvements, it is now With other technological improvements, it is now possible to fit many more transistors on a single chip.possible to fit many more transistors on a single chip.


This gives RISC processors enough space to This gives RISC processors enough space to incorporate more complicated, CISC-like commands. incorporate more complicated, CISC-like commands. RISC chips also make use of more complicated RISC chips also make use of more complicated hardware, making use of extra function units for hardware, making use of extra function units for superscalar execution. All of these factors have led superscalar execution. All of these factors have led some groups to argue that we are now in a "post-some groups to argue that we are now in a "post-RISC" era, in which the two styles have become so RISC" era, in which the two styles have become so similar that distinguishing between them is no longer similar that distinguishing between them is no longer relevant. However, it should be noted that RISC chips relevant. However, it should be noted that RISC chips still retain some important traits. RISC chips stricly still retain some important traits. RISC chips stricly utilize uniform, single-cycle instructions. They also utilize uniform, single-cycle instructions. They also retain the register-to-register, load/store architecture. retain the register-to-register, load/store architecture. And despite their extended instruction sets, RISC chips And despite their extended instruction sets, RISC chips still have a large number of general purpose registers.still have a large number of general purpose registers.

ReferencesReferences

http://ouray.cudenver.eduhttp://ouray.cudenver.edu http://en.wikipedia.org/wiki/CISChttp://en.wikipedia.org/wiki/CISC http://cse.stanford.edu/class/sophomore-http://cse.stanford.edu/class/sophomore-

college/projects-00/risc/college/projects-00/risc/ http://www.sunderland.ac.uk/~ts0jti/http://www.sunderland.ac.uk/~ts0jti/

comparch/ciscrisc.htmcomparch/ciscrisc.htm http://www.heyrick.co.uk/assembler/http://www.heyrick.co.uk/assembler/

riscvcisc.htmlriscvcisc.html

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CISC & RISC