Choosing the right preamplifier/discriminator

comparing advantages and drawbacks :NL-277-L (Nanometrics), ASD-8 (Cern) and MAD4 (INFN Italy)

Our favorite: "The MAD"-Chip

• optimized for DC readout• very fast, low crosstalk, LVDS output• 1 Chip: 4 preamp/discriminator• very cheap: ~$8/channel

received 5 MAD chips + test board from INFN Italy for evaluation

The MAD-Chip Board

En/Disabling channelsover I2C bus

(Philips PCF8577)

MAD Chips

Example shown here:16 channel Frontend Board

(INFN Italy)

Input for test signal

16 chan output (LVDS->TDC)

• Threshold Setting• Temperature Readout

Front Side

Front side of board

Test points

The MAD-Chip Board Example shown here:16 channel Frontend Board

(INFN Italy)

Back Side

Input for test signal Differential wire signal inputs(as close to MAD chips as possible)

Back side of board

Principle of a traditional delayline readout

Example for a delayline readout with an interleave factor Fi=3 and N=4

I

L R L RK

F : interleave factor

K : channel numberτ : delay of one delaylineN : number of delay lines per chain

t -t t +tN NτK = + t = +2τ 2 2τ 2

Total number of TDC channel neededfor delayline readout (2x Dual VDC chambers)

#chan = 2*FI*Nplanes with FI=8 = 2*8*8 = 128 channels (=64/Octant) -> 256 channels (Top/Bottom RO)

Qweak:FI=8,Tau=2ns or less, (depends on TDC resolution)N=18 (top/bottom RO)

Max Deadtime: N*Tau ~36ns

8 TDC channels

8 TDC channels

“Top readout” of 141 wires

“Bottom readout” of 141 wires

Principle of the Encoding Readout System (EROS)

8 x 5-Bit Busfor decoding thechannel number

(8*2^5 = 256 max)To Pattern Logic

(40 channels)

To Pattern Logic(40 channels)

282 wires per plane,Read out by 16 TDC channels

and a 2*256 Pattern Unit.(VDC: Max 8 simultaneous

wire hits per track)

Channel Bit Pattern (2^5 =32)

-> Delayline free readout (less dead time)

Preamplifier/Discriminator(MAD Board)

Wire Signal Readout using a flexible board

Material: DuPont Pyralux Copper-Clad Laminate+Adhesive

• available in single, double, and mulilayer version• can be photoetched like a regular PCB• max format: 24"x36" (610x914)• FR 9150: Kapton 127um, copper 35um, adhesive 25um (used for Mainz Drift Chambers)

• Need 144 + X Pyralux boards (18 per plane, 8 planes total)• Up to now: All boards have the same layout. Might change with placing precision dowel pins on wire frame• Pyralux board will contain holes for screws (keep out zone)• Unclear: Do we need additional shielding like

• grounded copper strip between signal copper strip, and/or• signal plane between grounded copper planes (sandwiched)• Shielding might add unwanted input capacity• According to MAD data sheet: input impedance ~

• Glue area: 7” x 4.6” • Length from Frame to MAD board is not fixed (assumed 2”)

Input: 16 wires (gold plated tungsten, 25um diameter)

Output: (SMD) connector, will be plugged on 16 channel MAD board

Photoedged Copper lines

Pyralux area with an adhesive Pyralux area without an adhesive

MAD Board Specification

• One Frontend Board (FEB) reads out 16 channels• 4 MAD chips• Enable/Disable of individual output channels (I2C)• Input for test signal (offline test)• temperature readout (sum of 4 MAD chip temperature sensors)• Board Size: ~6” x ~2”, INFN needed 4 layers

• Max Width: 160mm given by wire spacing • The connector for the incoming wire signal should be on board, minimizing the distance to the MAD chip inputs• The board should be pluggable. The plug provides the low voltages.

• Slow Control (multiplexing) with I2C chips• Local controll of a FEB: PCF8577 (32 I/O’s)• 3-Bit Address Multiplexing of the PCF8577 done globally using a PCF8574 (8 I/O’s)

Information about the MAD chip:

http://dilbert.physics.wm.edu/elog/Construction/2 and sub-links

16 channel outputConnector (LVDS)

8 channel inputconnector

8 channel inputconnector

I2C ChannelControl

(backside?)

MAD Chip MAD Chip

INFN Layout(154x44 mm)

Qweak possibleLayout

Connection toGround bar

(+ Mounting Holes)Daisy Chain

I2C BusVref, Vthres

Input fortest signal