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IBM Technology Development
IBM Systems and Technology Group © 2009 IBM Corporation
Chip Package Challenges
Jerry Bartley
Challenges
10/20/2009 2
Quotes to remind you of your perceived limits“I think there is a world marketfor maybe five computers.”
Thomas Watson, chairman of IBM, 1943
“Computers in the future may weigh no more than 1.5 tons. ”
Popular Mechanics, 1949
“There is no reason anyone would want a computer in their home. ”
Ken Olsen, founder of DEC, 1977
“640K ought to be enough for anybody. ”
Bill Gates, 1981
“Prediction is difficult, especially about the future”
Yogi Berra
Challenges
© 2009 IBM CorporationIBM Technology Development
Moore’s Law (Predicting the future….)
Challenges
10/20/2009 4
Trends in Heat flux
5
Power Dissipation Trends
1
10
100
1000
1980 1990 2000 2010
Pow
er D
ensi
ty (
W/c
m2 ) Intel Data
SIA Projection
Hot Plate
Nuclear Reactor
386486
Pentium
Pentium Pro
Pentium II
Pentium III
Problems:•Power Delivery•“Max” Power•“Avg” Power
Challenges
10/20/2009 6
Challenges
10/20/2009 7
Challenges
© 2009 IBM CorporationIBM Technology Development
High Level Definition/Design (Managing the application variables)
Functional requirements (what does it have to do?)Schedules, resource requirementsCost targets (including take-down over time)Electrical (Signaling, modeling, noise, power, etc.)MechanicalThermal Reliability goals, requirements, service/warrenty strategyTechnology selection (criteria, risks, NRE)Card and Board layout, structureProcurement environment (number of suppliers?)Assembly process requirementsDesign margin requirementsFirst level packaging (technology selection, risks, NRE)Connectors (size, shape, performance, models)Test coverage
Challenges
© 2009 IBM CorporationIBM Technology Development
Wavelength Worries
0.1 MHz 1 MHz 10 MHz 100 MHz 1000 MHz 10 GHz 100 GHz
Wavelength = speed of light / frequency(in FR4…)
365 m 36.5 m 3.65 m 36.5 cm 3.65 cm 3.65 mm 365 umλ/4:
RackDatacenterinterconnect
Card-to-cardinterconnect
Trace lengthsPower shapes
High-end board thicknessConnector features
Package tracesPower shapes
Component attach
Scary in currenttechnology
Challenges
© 2009 IBM CorporationIBM Technology Development
Channel structure at the Fundamental Frequency
0.1 MHz 1 MHz 10 MHz 100 MHz 1000 MHz 10 GHz 100 GHz
Simple RLC models
Impedance match/reflectionsRough timing/delay“Many-drop” nets (JTAG, I2C)Asynchronous/self-timed
Impedance match/reflectionsDetailed timing/delay“Few-drop” nets (60x, PCI)Common-clock
RLC discontinuitiesLossless T-lines
Staged RLC discontinuitiesCoupled lossy T-lines
Board/Package process variationsGroup matchingPoint-to-point nets (DDRx, HT, PCIx)Source-synchronous groups
Board/Package process variationsAttenuation dominatedPoint-to-point differential (HSS, PCIE)Reference/Recovered clockPattern restrictions
3D fully-extracted channel features
DRAM
Challenges
© 2009 IBM CorporationIBM Technology Development
0 0.002 0.004 0.006 0.008 0.01Time (uS)
-5
0
5
10
15
Cur
rent
(am
ps)
Time Domain Wave form
1.00
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2
2.00
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9.00
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1.00
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1.10
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3
1.20
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3
1.30
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1.40
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3
1.50
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3
1.60
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3
1.70
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3
1.80
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3
1.90
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3
2.00
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3
2.10
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3
2.20
E+00
3
2.30
E+00
3
2.40
E+00
3
2.50
E+00
3
Frequency (MHz)
1
10
mag
(i)
|I|
Frequency Domain
1.00
E+00
2
2.00
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2
3.00
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2
4.00
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2
5.00
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2
6.00
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2
7.00
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2
8.00
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2
9.00
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1.00
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3
1.10
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1.20
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3
1.30
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1.40
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3
1.50
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3
1.60
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3
1.70
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3
1.80
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3
1.90
E+00
3
2.00
E+00
3
2.10
E+00
3
2.20
E+00
3
2.30
E+00
3
2.40
E+00
3
2.50
E+00
3
Frequency (MHz)
1
10
mag
(i)
|I|
Frequency Domain
0 0.002 0.004 0.006 0.008 0.01Time (uS)
-5
0
5
10
15
Cur
rent
(am
ps)
Time Domain Wave form
1.00
E+00
2
2.00
E+00
2
3.00
E+00
2
4.00
E+00
2
5.00
E+00
2
6.00
E+00
2
7.00
E+00
2
8.00
E+00
2
9.00
E+00
2
1.00
E+00
3
1.10
E+00
3
1.20
E+00
3
1.30
E+00
3
1.40
E+00
3
1.50
E+00
3
1.60
E+00
3
1.70
E+00
3
1.80
E+00
3
1.90
E+00
3
2.00
E+00
3
2.10
E+00
3
2.20
E+00
3
2.30
E+00
3
2.40
E+00
3
2.50
E+00
3
Frequency (MHz)
1
10
mag
(i)
|I|
Frequency Domain
0 0.002 0.004 0.006 0.008 0.01Time (uS)
-5
0
5
10
15
Cur
rent
(am
ps)
Time Domain Wave form
1.00
E+00
2
2.00
E+00
2
3.00
E+00
2
4.00
E+00
2
5.00
E+00
2
6.00
E+00
2
7.00
E+00
2
8.00
E+00
2
9.00
E+00
2
1.00
E+00
3
1.10
E+00
3
1.20
E+00
3
1.30
E+00
3
1.40
E+00
3
1.50
E+00
3
1.60
E+00
3
1.70
E+00
3
1.80
E+00
3
1.90
E+00
3
2.00
E+00
3
2.10
E+00
3
2.20
E+00
3
2.30
E+00
3
2.40
E+00
3
2.50
E+00
3
Frequency (MHz)
0.1
1
10
mag
(i)
|I|
Frequency Domain
0 0.002 0.004 0.006 0.008 0.01Time (uS)
-5
0
5
10
15
Cur
rent
(am
ps)
Time Domain Wave form
1.00
E+00
2
2.00
E+00
2
3.00
E+00
2
4.00
E+00
2
5.00
E+00
2
6.00
E+00
2
7.00
E+00
2
8.00
E+00
2
9.00
E+00
2
1.00
E+00
3
1.10
E+00
3
1.20
E+00
3
1.30
E+00
3
1.40
E+00
3
1.50
E+00
3
1.60
E+00
3
1.70
E+00
3
1.80
E+00
3
1.90
E+00
3
2.00
E+00
3
2.10
E+00
3
2.20
E+00
3
2.30
E+00
3
2.40
E+00
3
2.50
E+00
3
Frequency (MHz)
0.1
1
10
mag
(i)
|I|
Frequency Domain
0 0.002 0.004 0.006 0.008 0.01Time (uS)
-5
0
5
10
15
Cur
rent
(am
ps)
Time Domain Wave form
1.00
E+00
2
2.00
E+00
2
3.00
E+00
2
4.00
E+00
2
5.00
E+00
2
6.00
E+00
2
7.00
E+00
2
8.00
E+00
2
9.00
E+00
2
1.00
E+00
3
1.10
E+00
3
1.20
E+00
3
1.30
E+00
3
1.40
E+00
3
1.50
E+00
3
1.60
E+00
3
1.70
E+00
3
1.80
E+00
3
1.90
E+00
3
2.00
E+00
3
2.10
E+00
3
2.20
E+00
3
2.30
E+00
3
2.40
E+00
3
2.50
E+00
3
Frequency (MHz)
0.1
1
10
mag
(i)
|I|
Frequency Domain
0 0.002 0.004 0.006 0.008 0.01Time (uS)
-2
0
2
4
6
8
10
12
Cur
rent
(am
ps)
Time Domain Wave form
1.00
E+00
2
2.00
E+00
2
3.00
E+00
2
4.00
E+00
2
5.00
E+00
2
6.00
E+00
2
7.00
E+00
2
8.00
E+00
2
9.00
E+00
2
1.00
E+00
3
1.10
E+00
3
1.20
E+00
3
1.30
E+00
3
1.40
E+00
3
1.50
E+00
3
1.60
E+00
3
1.70
E+00
3
1.80
E+00
3
1.90
E+00
3
2.00
E+00
3
2.10
E+00
3
2.20
E+00
3
2.30
E+00
3
2.40
E+00
3
2.50
E+00
3
Frequency (MHz)
0.1
1
10
mag
(i)
|I|
Frequency Domain
0 0.002 0.004 0.006 0.008 0.01Time (uS)
-2
0
2
4
6
8
10
12
Cur
rent
(am
ps)
Time Domain Wave form
Building a square wave with Sine/Cosine waves
Expansion of Fourier Series
Challenges
10/20/2009 12
Transition to 3D CMOS
Year of Announcement1950 1960 1970 1980 1990 2000 2010
Mod
ule
Hea
t Flu
x(w
atts
/cm
2 )
0
2
4
6
8
10
12
14
Bipolar
CMOS
? Opp
ortu
nity
for 3
D S
i
Challenges
© 2009 IBM CorporationIBM Technology Development
Emerging 3D Silicon Integration
CPUCPU
FlashFlash
DRAMDRAM
DSPDSP
2D structure Package in Package
High Density Chip Carrier Pkg
Si Carrier
103
Package on Package
Integration (I/
O / cm
2 )
104 - 105
Wire bonded Chip Stack
Through silicon via Stacking
Chip stack
3D IC
Device Layer 2Vertical Interconnect
Silicon
1Device Layer
Silicon
1
Device Layer 2Vertical Interconnect
Silicon
1
Device Layer 2Vertical Interconnect
Silicon
1
Device Layer 2Vertical Interconnect
Silicon
1Device Layer
Silicon
Device Layer
Silicon
1
105 - 106
Another way to extend Moore’s Law
Challenges
© 2009 IBM CorporationIBM Technology Development
3D Structures and Cooling Approaches
Chip 2Chip 1
Carrier
Cooler
Cooling one layer of chips on a Si carrier
Chips on a Si carrierHave direct access to the back of each chipMechanical issues predominate over thermal issuesMust develop a very good thermal interface material thick
enough to handle chip non-planarity
Stacked chips of moderate powerCan be cooled from the back of the stackMust improve conductivity through complex stack with
many thermal interfaces
Bring cooling into the stackFar more complex, but might allow higher stacks
Bringing liquid cooling into chip stack
Cooling a chip stack from the back
CoolerChip 1Chip 2
Challenges
© 2009 IBM CorporationIBM Technology Development
Thru – Silicon Vias (TSV)
3D Chip
Laminate package
C4
C4
TSV50-90um
A TSV, before filling
Challenges
10/20/2009 16
99.4 % HUMAN DNA
Chimp off the old block
0.6% Really does make a difference !!!!!
DETAILS REALLY MATTER !!!!!!!!
Challenges
10/20/2009 17
More Thermal Reality
tenS45120⋅
FIT45120⋅
Detailed knowledge is important
• Understanding the power density
• Understanding the impact of higher Temperatures
• Having the ability to bring the appropriate amount of technology to the application. Power density maps
Tambient Tj_nom effective hot-spot R
fin base HTC
TIM1 interface condition
C C C/W W/m**2K
25 57.5 0 755 uniformly heated chip
25 64.1 0.15 755 best can-do grease
25 91.9 0.76 755 2 mil PCM interface
Challenges
10/20/2009 18
Characteristics of today’s Silicon
Transistor Leakage Vs. Channel Length - nA of leakage vs. Transistor Length (nm)
0
100
200
300
400
500
30 40 50 60
Total Die Power vs. Vdd by Tj
12141618202224262830
0.9 1 1.1 1.2 1.3 1.4 1.5
Supply Voltage (at die)
Pow
er (W
)
Tj = 25CTj = 55CTj = 85C
Die-Level Leakage Power vs. Temperature
01234567
-10 10 30 50 70 90 110
Die Junction Temp
Die
Sta
tic P
ower
(mA
)
Challenges
10/20/2009 19
ObservationsWe currently are not able to utilize all of the transistors and capability we can build within the Silicon Power in… and Power out… among the key limitationsCircuit designs, chip materials…. Timing, reliability, yield all pressuring our analysis capability.More and more analysis necessary with much higher detail, trade-offs required to achieve success. Power structure likely requires more extendibilityLimitations starting to engage broader teams and disciplines
Silicon process, Chemists, etc.System and micro-architecture Device/transistor designers
Challenges
10/20/2009 20
My Conclusion, Prediction, and Encouragement
Thermal limitation awareness has become pervasive across all facets of the electronic industry and thus the opportunity for this group to influence the direction of the industry has clearly increased.
More analytical capability will be required to provide the detail necessary to guide developers (including the other disciplines) toward optimization.
More interaction to close the gaps between the disciplines will provide large paybacks in the ability to integrate and deploy applications to the marketplace.
Challenges exist at all levels, we must evolve to succeed.
