Chip-Aware Power Integrity - url · 2019. 7. 24. · ANSYS Chip-Aware PDN Solution 0.00 2.00 4.00 6.00 8.00 10.00 Time [ns] 1.450 1.475 1.500 1.525 1.550 V] U1 VCC CPM Current Curve

© 2011 ANSYS, Inc. July 24, 20191

Chip-AwarePower Integrity

Greg Pitner

Isaac Waldron

© 2011 ANSYS, Inc. July 24, 20192

• Power integrity challenges and solution

• New PI features in R14.5

• Power integrity case study

Agenda

© 2011 ANSYS, Inc. July 24, 20193

Power Integrity Challenges and Solution

© 2011 ANSYS, Inc. July 24, 20194

The die-to-die system is extremely complex:

• Silicon driver/receiver• 3D component interconnect• Chip to package• Package to daughter card• Daughter card to backplane• Power delivery network effects

Complex problems• High risk

– New unfamiliar phenomena?

• High cost of design errors

Solving them is requiring new strategies and simulation tools.

Trends Requiring Chip Aware System Design

+

-

+

-

Via Via Via

MS SL SL

Package PackageConnectorBackplane Daughter Card

© 2011 ANSYS, Inc. July 24, 20195

What is a Power Distribution Network (PDN)?

Complex multi-stage network supplying power to all devices in a system.

PDN Requirements:

• Must deliver clean power to the ICs

• Must provide low impedance, low noise reference path for signals

• Must not contribute excessive EMI

For typical products the PDN includes:

• Voltage regulator module (VRM)

• Board power/ground planes and decoupling capacitors

• Package power/ground planes and decoupling capacitors

• Chip power/ground structures and capacitance

© 2011 ANSYS, Inc. July 24, 20196

Board Level Power Integrity?

Chip

Discrete Decoupling Capacitor on PCB

VRM

Bulk Capacitor

Low Inductance Capacitor on Package

Ball Grid Array Package

Ball Bonding Ground

Power

Chip

Package

PCB

ΔIWire

BondingPackage

P/G NetworkBall

BondingPCB

P/G Network

VRM

Bulk CapacitorNear VRM

Decoupling CapacitorOn PCB

Decoupling CapacitorOn Package

Decoupling CapacitorOn Chip

Full PDN

Very Low Frequency CurrentLow Frequency CurrentMedium Frequency CurrentHigh Frequency CurrentVery High Frequency Current

Board LevelP/G Impedance?

© 2011 ANSYS, Inc. July 24, 20197

Redhawk generates a chip power model (CPM) including chip PDN parasitics and switching currents.

PSI and SIwave provide robust extraction of IC packages and boards with broadband S-parameter models.

PI Advisor optimizes decoupling capacitor selection to meet a target impedance.

Designer SI simulates power noise in the time domain.

ANSYS Chip-Aware PDN Solution

0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

1.450

1.475

1.500

1.525

1.550

V(u

1_

vcc)

[V]

CPM CurrentU1 VCCCurve Info min max pk2pk avg

V(u1_vcc)NexximTransient

1.4507 1.5489 0.0982 1.4946

© 2011 ANSYS, Inc. July 24, 20198

Chip Power Model (CPM)

© 2011 ANSYS, Inc. July 24, 20199

Chip Design

Prototype

Design

Sign-off

Package / PCB Design

Selection, Planning

Package Design

System

Sign-off

Chip Power Model

CPS Convergence Using CPM

© 2011 ANSYS, Inc. July 24, 20191010

Each C4 bump (power & ground) will be associated to its corresponding:

✓Chip PDN RLC Physical model of chip layout

✓Transistor/cell current /cap/ESR Electrical model of chip layout

CPM is topological, physical and activity based

PCB + Package

What’s in a CPM?

© 2011 ANSYS, Inc. July 24, 201911

Traditional Die Model

RedHawk (SoC)

Layout

Chip Power Model

▪ RLC reduction: billions of parasitics to thousands of Spice elements

▪ Distributed with full couplings

Apache CPM™

Library

Ch

ip C

urr

en

tC

hip

Par

asit

ics

Traditional die model

Single Lumped Model

Apache CPM

Benefits of CPM

© 2011 ANSYS, Inc. July 24, 201912

SIwave CPM integration includes the following:

• Import of die PDN for inclusion in frequency-domain extractions

• Automatic matching of die pin to CPM pin locations

SIwave CPM Integration

© 2011 ANSYS, Inc. July 24, 201913

SIwave CPM Setup

© 2011 ANSYS, Inc. July 24, 201914

SIwave CPM Setup

© 2011 ANSYS, Inc. July 24, 201915

CPM Impedance Effect

0.10 1.00 10.00Freq [GHz]

0.10

1.00

10.00

100.00

1000.00

ma

g(Z

(FC

HIP

_V

DD

_1

5,F

CH

IP_

VD

D_

15

))

analysis_v2PDN Impedance at DieCurve Info

mag(Z(FCHIP_VDD_15,FCHIP_VDD_15))SYZ Sw eep 1

mag(Z(FCHIP_VDD_15,FCHIP_VDD_15))SYZ Sw eep 2

PKGPKG+CPM

© 2011 ANSYS, Inc. July 24, 201916

Sentinel PSI

© 2011 ANSYS, Inc. July 24, 201917

ANSYS Package/Board Solvers

Hybrid full-wave3D full-wave

SIwaveSentinel-PSI

• Fast FEM using prism elements • Tailored for PI package analysis

• FAST Hybrid method for PKG/BRD• Handles many, but not all 3D effects

FastTrade-off speed for 3D accuracy

SPEED

© 2011 ANSYS, Inc. July 24, 201918

Sentinel PSI Strengths

Package/PCB structures Containing

• Highly perforated metal planes– Swiss Cheese PWR/GND planes

– Hatched PWR/GND planes

• Two layer PCBs without reference layers

• Transmission lines over non-ideal ground

• Ports with unreferenced terminals

• Visualization of PWR/GND AC currents

• Vias with large anti-pads

Typical Hatched Plane

Port With Unreferenced Terminal

Large continuous anti-pads

Lines over non-ideal ground cutouts

© 2011 ANSYS, Inc. July 24, 201919

PI Advisor is an addon for Siwavethat automatically optimizes capacitor selection to meet a target impedance:

Inputs:

• Capacitor locations

• Candidate capacitors

Outputs:

• Capacitor schemes that indicate which candidate, if any, to populate at each location.

• Impedance versus target for each scheme.

PI Advisor

© 2011 ANSYS, Inc. July 24, 201920

Target Impedance

© 2011 ANSYS, Inc. July 24, 201921

Target Impedance

• Designing for power integrity often involves a target impedance– Maximum allowable impedance magnitude over frequency which will result in acceptable

voltage noise

• Several technical references contain something like

• An example can illustrate the complexities with this approach…

PDNIpwr

ZPDN

Vnoise

+

_Vnoise = Ipwr ZPDN

Ztarget =Vnoise(max)Ipwr(ACpeak)

(Quantities are phasors)

f

|Z|

Mag. of Z

targetZ

© 2011 ANSYS, Inc. July 24, 201922

A Simple Target Impedance Example

• Suppose we have a power current with the periodic AC component shown below (peak amplitude of 2A):

• Suppose we have a maximum allowable voltage amplitude of 1V

• The simple approach suggests a max ZPDN of 0.5W over the frequency components contained in the current will satisfy the noise requirement

-2

-1

0

1

2

0 0.5 1 1.5 2 2.5

Current (A)

ZPDN

0.5W

Freq

𝐼 𝑡 = 𝐼1 cos 2𝜋𝑡 + 𝜃𝐼1

+ 𝐼2 cos 4𝜋𝑡 + 𝜃𝐼2

+ 𝐼3 cos 6𝜋𝑡 + 𝜃𝐼3

𝑉𝑓 𝑡 = 𝐼𝑓 ∙ 𝑍𝑓 cos 2𝜋𝑓𝑡 + 𝜃𝐼𝑓 + 𝜃𝑍𝑓

But our impedance tolerance does not specify phase

© 2011 ANSYS, Inc. July 24, 201923

Effects of Different Impedance Phases

• Assume our PDN impedance just satisfies the requirement at each frequency:|Z1|= |Z2|= |Z3|= 0.5W, but vary the impedance phase assumptions

-2

-1

0

1

2

0 0.5 1 1.5 2 2.5

Current (A)

Voltage (V)

qZ1 = qZ2 = qZ3 = 0

-2

-1

0

1

2

0 0.5 1 1.5 2 2.5

Current (A)

Voltage (V)

-2

-1

0

1

2

0 0.5 1 1.5 2 2.5

Current (A)

Voltage (V)

qZ1 =0 qZ2 =90o qZ3 = 0 qZ1 =-90

o qZ2 =-90o qZ3 = -90

o

Simple approaches to calculating target impedance can provide a useful guide, but results should be verified with time-domain simulation

© 2011 ANSYS, Inc. July 24, 201924

Target Impedance Notes

Reliance on a purely resistive target impedance may not bound the resulting time-domain voltage waveform to the desired amplitude.

Target impedance calculations should take into account the impedance phase as well as magnitude, but the current state-of-the-art does not.

More to come from ANSYS on this topic…

© 2011 ANSYS, Inc. July 24, 201925

Power Integrity Case Study

© 2011 ANSYS, Inc. July 24, 201926

1.5V power supply for FPGA on board.

Chip included as Apache CPM.

Package included as static S-parameters.

Board extracted with SIwave 7.

Simulation includes:

• GND

• VCC_1V5

System excited by CPM currents.

PDN Under Test

© 2011 ANSYS, Inc. July 24, 201927

Time Domain Circuit

0

V5

DC=1.5V

AName=i_u1

VName=u1_vcc

Port1Port2

FGB Channel Power Only

VC

CV

SS

Die Current

0

© 2011 ANSYS, Inc. July 24, 201928

0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

300.00

400.00

500.00

600.00

700.00

800.00

900.00

1000.00

Ipo

sitiv

e(i

_u

1)

[mA

]

CPM CurrentDie Current

m2

m1

Curve Info

Ipositive(i_u1)NexximTransient

Name X Y

m1 7.3200 444.1449

m2 9.8700 422.7601

Name Delta(X) Delta(Y) Slope(Y) InvSlope(Y)

d(m1,m2) 2.5500 -21.3847 -8.3862 -0.1192

Die Current

0

V5

DC=1.5V

AName=i_u1

VName=u1_vcc

Port1Port2


VC

CV

SS

Die Current

0

Die Current

© 2011 ANSYS, Inc. July 24, 201929

PDN Channel

0

V5

DC=1.5V

AName=i_u1

VName=u1_vcc

Port1Port2


VC

CV

SS

Die Current

0

0

Port1Port2

VC

CV

SS

Die PDN VCC_DIE VCC_BGA

FGB Package

VCC_BGA VCC_VRM

FGB Board

BoardPackageDie

© 2011 ANSYS, Inc. July 24, 201930

PDN Impedance Components

1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

10.00

100.00

1000.00

Y1

[o

hm

]

FGB BoardPDN Impedance ComponentsCurve Info

BoardLinearFrequency

PackageImported

DieImported

BoardPackageCPM

© 2011 ANSYS, Inc. July 24, 201931

Full PDN Impedance

1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

ma

g(Z

(Po

rt2

,Po

rt2

)) [o

hm

]

FGB Channel Power OnlyFull PDN ImpedanceCurve Info

mag(Z(Port2,Port2))LinearFrequencyFull PDN

© 2011 ANSYS, Inc. July 24, 201932

Package Model Fit

0

Port1

883.15pF

C236

485.35pF

C237

23.855pH

L238

23.855pH

L239

0.0136ohm

R240

0.0139ohm

R241

883.15 pF

23.855 pH

13.6 mohm

485.35 pF

23.855 pH

13.9 mohm

© 2011 ANSYS, Inc. July 24, 201933

Package Model Fit

0.00 0.01 0.10 1.00 10.00F [GHz]

0.01

0.10

1.00

10.00

100.00

1000.00

Y1

[o

hm

]

Circuit3Package Model FitCurve Info

Package FitLinearFrequency

PackageImported

Package FitPackage

© 2011 ANSYS, Inc. July 24, 201935

Die Model Fit

0.00 0.01 0.10 1.00 10.00F [GHz]

0.10

1.00

10.00

100.00

Y1

[o

hm

]

Circuit1Die Model FitCurve Info

Die FitLinearFrequency

DieImported

Die FitDie

© 2011 ANSYS, Inc. July 24, 201936

Board with Package/Die Fits

1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

Y1

[o

hm

]

FGB BoardBoard PDN ImpedanceCurve Info

Board w ith Package/Die FitsLinearFrequency

Full PDNImported

Board w/ Package/Die FitsFull PDN

© 2011 ANSYS, Inc. July 24, 201937

1. As initially designed.

– Eight 100 uF bulk capacitors at VRM output, two 10 uF capacitors, and two 1 uF capacitors.

2. With added high-frequency capacitors.

– 12 0.01 uF capacitors placed on bottom layer below FPGA

3. With PI Advisor-optimized capacitor solution.

– Target impedance: 0.3 ohms up to 1 GHz

– Package RLC fit and die RC fit included at board FPGA footprint

Board Variations Analyzed

© 2011 ANSYS, Inc. July 24, 201938

0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

1.450

1.475

1.500

1.525

1.550

V(u

1_

vcc)

[V]



1.4632 1.5255 0.0623 1.4901

Variation 1: As-Designed

U1 VCCFinal period peak-to-peak: 62.3 mV

© 2011 ANSYS, Inc. July 24, 201939

Variation 2: Added Capacitors

1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

Y1

[o

hm

]


mag(Z(Port2,Port2))LinearFrequency

mag(Z(Port2,Port2))_1Imported

Variation 2As-built

© 2011 ANSYS, Inc. July 24, 201940

0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

1.450

1.475

1.500

1.525

1.550

V(u

1_

vcc)

[V]



1.4671 1.5344 0.0672 1.4988

Variation 2: Added Capacitors


© 2011 ANSYS, Inc. July 24, 201942


1.00 10.00 100.00 1000.00 10000.00F [MHz]

0.00

0.01

0.10

1.00

Y1

[o

hm

]


mag(Z(Port2,Port2))LinearFrequency

mag(Z(Port2,Port2))_1Imported

Variation 3Variation 2

© 2011 ANSYS, Inc. July 24, 201943

0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

1.450

1.475

1.500

1.525

1.550

V(u

1_

vcc)

[V]



1.4771 1.5177 0.0406 1.5005



© 2011 ANSYS, Inc. July 24, 201944

Power integrity simulation requires accurate package and chip PDN models to ensure correct designs.

The ANSYS chip-package-system technologies provide full coverage for PI simulation needs:

• CPM: chip PDN and current draw

• SIwave and PSI: package PDN

• SIwave: board PDN

• Designer: frequency- and time-domain simulation for full PDN

Conclusion

Documents

Chip-Aware Power Integrity - url · 2019. 7. 24. · ANSYS Chip-Aware PDN Solution 0.00 2.00 4.00 6.00 8.00 10.00 Time [ns] 1.450 1.475 1.500 1.525 1.550 V] U1 VCC CPM Current Curve