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Charge Measurement Using Commercial Devices
Jinyuan Wu, Zonghan Shi
For CKM Collaboration.
Jan. 2003
Introduction
PMT
QAD6644 FPGAIntegrator
HP1662C
AD6644
FPGAIntegrator(1)AD8055
Input Pulse
EPC2LC20
Integrator (2)OPA660
To Analyzer
The Circuit Board
All test equipments
Outline
• AD6644.
•Integrator circuit (1).
•ADC output.
•AD6644 stability
•Integrator circuit (2).
Commercial ADC: AD6644• The AD6644 is a high speed, high-
performance, monolithic 14-bit analog-to-digital converter.
•Current FPGA technology is used in our tests.
•The sample rate in our tests is 35 MHz or
the sample time is 28.5ns.
•The guaranteed sample rate is 65 MSPS.
Integrator for ADC [1]
+2.5V
GND
Input Pulse
100pf
36.5k
_
+
AD805551OUTPUT
•The output will send to AD6644 as a input signal.
•It is a traditional integrator.
•T=RC=36.5k x 100pf=3.65us=128 x 28.5ns
Input Pulse
Output
Input Pulse
Output
Digital Process of AD6644 Output
• Using FPGA hardware to find charge.
ADC ADCQ
SUB ABS
OR
AND
Higher Bits
DIFF
D
D
Simple Zero Suppression Algorithm
= Charge
DIFF = Charge
ADCQ
Data from HP 1662C Logic Analyzer
ADCQ
Charge
The Stability of AD6644
256
D
ABSEN
R(RESULT)SUB D
D(DATA FROM AD6644)
•Above circuit is used to produce the mean of absolute difference.
256
255
0)1(
nnn DD
R
• DC input is sent to AD6644.
Data From HP 1662C Logic Analyzer
Result
ADCQ
The Mean of Absolute Difference
191406.1256
)305(
256
)131(
256
255
0)1(
dechexn
nn DDR
ADCQ
ADC Output of DC Input
Standard Deviation
)146( 011904.1)(
1
2
n
n
XXn
ii
Integrator for ADC [2]
GND
Input Pulse
GND
51
150
GND
51
150
17
OUTPUT
100pf
36.5k
5V
5 6
3
8
2OPA660OperationalAmplifier & Buffer
+1
Similar as Ken Nelson’s design except the omission of the reset circuits.
Input Pulse
Output
Input Pulse
Output
Additional Works To Be Done
• Connect to the QIE test system in Lab 6.
• The test for Integrator (2).
Thanks
Input Pulse
Output
Integrator (1)
Input pulse
Output
Integrator (2)