Characterization of Electroplated Cu films for 3 dimensional advanced packaging

Characterization of electroplated copper films for three-dimensionaladvanced packaging

C. H. Seah,a) G. Z. You, C. Y. Li, and R. KumarInstitute of Microelectronics, 11 Science Park Road, Singapore 117685, Singapore

~Received 18 December 2003; accepted 5 April 2004; published 17 May 2004!

A study was carried out to determine the feasibility of using the Cu electroplating process to achievegood gap fill in interchip-via~ICV! wafers, focusing on the effect different current wave forms haveon electroplated Cu film properties, the gap fill capability and the chemical mechanical planarizationprocess. It was found that the roughness of direct current~dc!-plated Cu films is at least three timeslower than that of pulse-plated films and the roughness of the latter was observed to be stronglydependent on the magnitude of forward (I f) and reverse (I r) currents. This produced a significantdifference in reflectivity between the two types of films. The as-deposited dc- and pulse-plated Cufilms were also found to have specific resistivities of;2.2 and;2.1 mV cm, respectively. Theywere reduced to a similar value of 1.77mV cm after annealing at 200 °C. All the dc and higherI f

pulse-plating processes produced Cu films having an average polish rate of 7000 Å/min with thepolish rateU% less than 3%, showing a fluctuating profile across the wafer. The higherI r

pulse-plated film showed a very low polish rate of 210 Å/min with the polish rateU% at 58%,resulting in a dome profile. The multistep dc plating process was found unsuitable for the filling oflarge vias in the ICV wafers as it resulted in conformal plating with a large center seam being seendue to the pinch-off effect at the top of the via. The pulse-plating process showed a significantimprovement in the gap fill capability with a reduction in the size of the center void. The pinch-offeffect was also greatly reduced when higherI r was used and an increase in bottom coverage couldalso be seen, resulting in acceptable gap fill with only a small center void in the ICV wafers.© 2004 American Vacuum Society.@DOI: 10.1116/1.1755217#

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I. INTRODUCTION

Complementary metal–oxide–semiconductor compatvertically integrated circuits technology has been develousing the interchip-via~ICV! concept1,2 and there are reportof both chemical-vapor deposited~CVD! tungsten3,4 andCVD copper5 into deep via holes of 15mm depth with CVDTiN acting as the glue/barrier layer. Since Cu electrochecal plating~ECP! technology was successfully establishedthe low cost deposition process for submicron via fillilined with Cu seed and Ta diffusion barrier in advancedinterconnects applications, producing film resistivities,2.0mV cm and showing good gap-filling capabilities,6–10astudy was carried out to investigate the application of theelectroplating process for ICV wafers to achieve good gfill.

Both multistep direct current~dc! and periodic pulse~PP!plating are currently employed for ultralarge scale integradevice applications. It has been reported that the pulse wform process reduces the rate of feature pinch-off at the nand thus reduces center voids, providing better gap fill cability as compared with the dc process.11–14In this article wefocus on the characterization of electroplated Cu filmstained using different current wave forms. The impact onfilm properties, gap fill capability, and the chemical mechacal planarization~CMP! process is discussed.

a!Electronic mail: [email protected]

1108 J. Vac. Sci. Technol. B 22 „3…, MayÕJun 2004 1071-1023 Õ200

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II. EXPERIMENTAL PROCEDURE

In this study, the electroplating was performed in a Noellus Sabre which contained a standard electrolyte andprietary organic additives from Shipley, comprising of 17 gCu, 170 g/l H2SO4, 50 ppm chloride ions, 1 ml/l acceleratoand 25 ml/l suppressor, at 25 °C for both the blanket apatterned wafers using the following recipes:

• ECP#1: multistep dc only;• ECP#2: multistep dc with reverse steps;• ECP#3: PP reverse with higher forward current (I f); and• ECP#4: PP reverse with higher reverse current (I r).The wafers were prepared by depositing 150 nm

seed/25 nm Ta barrier/500 nm SiO2 on 8 in. ~100!-orientedp-type Si substrates. They were then electroplated usingearlier four recipes to a nominal thickness of 1.0mm Cu,

TABLE I. rms roughness and reflectivity of ECP Cu films.

Recipe

rms roughness~nm!Reflectivity/

reflectivity U%Center Edge

ECP#1 13.376 13.111 1.1960/3.51%

ECP#2 10.311 10.116 1.2038/2.24%

ECP#3 27.881 36.981 0.6133/22.44%

ECP#4 93.182 135.63 0.0884/59.70%

11084Õ22„3…Õ1108Õ6Õ$19.00 ©2004 American Vacuum Society

1109 Seah et al. : Characterization of electroplated copper films 1109

FIG. 1. AFM micrographs of ECP Cu films produced using recipes~a! ECP#2 and~b! ECP#3.

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after which the wafers were annealed at 200 °C in a pure2

ambient. The blanket Cu films were characterized usatomic force microscopy~AFM! and x-ray diffraction~XRD!to determine the microstructure of the films, four-point proto measure the sheet resistance (Rs) of the films, FSM7800TC laser scanner to measure the film stress and opprobe to measure the film reflectivity at a wavelength of 4nm relative to the reflectivity of bare Si wafer~unity!. Thedepth profile of trapped additives such as C, O, Cl, S inCu films was examined by secondary ion mass spectrom~SIMS!. They were also CMP polished for 1 min using thAMAT Mirra to determine the polish rate of the films.

The ICV patterned wafers were also fabricated onp-type~100! Si wafers. After the wafers were cleaned using stdard procedures, 2mm SiO2 film was deposited by plasmenhanced chemical vapor deposition and the single dascene of via structure was formed through proper patternetching and cleaning procedures. The 2.532.5 mm2 viaswere obtained using a highly anisotropic plasma etchtechnique, which etched through the entire oxide layer an

FIG. 2. XRD results of annealed ECP Cu films produced using recipes~a!ECP#1,~b! ECP#2,~c! ECP#3, and~d! ECP#4.

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mm deep into the Si substrate. The wafers were then cowith 400 nm Cu seed/25 nm Ta barrier using self-ionizmetal plasma technique and electroplated using the four rpes. They were finally CMP polished to remove the excCu until the Ta layer on the flat field of the wafer was eposed. Focused ion beam~FIB! analysis was carried out toevaluate the gap fill capability.

III. RESULTS AND DISCUSSION

A. Morphology of copper films

Table I lists the root mean square~rms! roughness andreflectivity of the Cu films electroplated from the four diffeent recipes. The roughness of pulse-plated Cu films is foto be at least three times higher than that of dc-plated filThe dc-plated Cu film had a roughness of 10 nm acrossentire wafer using recipe ECP#2 while the pulse-plated fiproduced a roughness of 28 nm at the center of the waferincreased to 37 nm at the edge when deposited using reECP#3. The additional dc reverse steps did not result ivariation in the roughness of the films produced using re

FIG. 3. Stress hysterisis of ECP Cu films.

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J. Vac. Sci. Technol

TABLE II. Sheet resistance and specific resistivity of ECP Cu films.

Recipe

Rs (mV/sq)Change in

Rs(%)

Specific resistivity~mV cm!

As-deposited Postannealed As-deposited Postanne

ECP#1 18.425 14.808 19.6 2.21 1.77ECP#2 18.527 14.777 20.2 2.22 1.77ECP#3 17.484 14.854 15.1 2.10 1.78ECP#4 17.842 15.012 15.9 2.14 1.80

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pes ECP#1 and ECP#2. However, in the case of the pplating process, the film roughness was observed tostrongly dependent on the magnitude of forward and revecurrents. It was found that the roughness of the platedfilm at the wafer center increased from 28 to 93 nm whenI r

changed from smaller thanI f to larger thanI f .This significant variation of the film roughness could

caused by the difference in Cu grain size produced bytwo types of applied current as observed in Fig. 1. The mphology of dc-plated Cu film showed a smoother topograpwith smaller grains of,1.0 mm size@Fig. 1~a!# compared tothat of pulse-plated film which has large Cu grains of.2.0mm size@Fig. 1~b!#. This in term is evident by the significandifference in the reflectivity of the films deposited by dc apulse plating.

The dc-plated films produced using recipes ECP#1ECP#2 had reflectivity of;1.20 compared to a bare Si wafeat a wavelength of 480 nm and the variation in the reflecity across the entire wafer (RefU%) was found to be lessthan 4% but in the case of pulse-plated films, the reflectivmeasured was very low with a large RefU%. Recipe ECP#3had a reflectivity of only 0.61 with a large variation of 22in the reflectivity across the entire wafer and whenI r becamelarger thanI f , as in recipe ECP#4, the film reflectivity wareduced to a value of 0.09 with the RefU% increasing to60%. The observed reflectivity result is well correlated tofilm roughness and grain size observed by AFM sinsmaller grains tend to give smoother morphology and thefore higher surface reflectivity.13

Figure 2 shows the x-ray diffraction patterns obtainedthe Cu films produced using the four recipes. From the nmalized peak heights, it was found that all the Cu filmmainly consisted of111& preferred orientation and the dcplated film had higher Cu~111! intensity than that plated using pulse wave form.

B. Sheet resistance of copper films

The as-depositedRs of both dc- and pulse-plated Cu filmwere different as shown in Table II with dc-plated films haing higher Rs . They were found to be;18.5 and;17.5mV/sq, respectively, corresponding to specific resistivities;2.2 and;2.1 mV cm. This could be due to the fact thapulse-plated deposits showed denser structure~i.e., less po-rosity compared to dc-plated deposits for the same fithickness!.15 Having tighter packing of crystals resulted indenser pulse-plated film and hence a lower as-depositedRs .

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After annealing the Cu films at 200 °C in a pure N2 am-bient, the filmRs was reduced by 15%–20% with dc-platefilm showing greater improvement. The postannealedRs forthe Cu films produced using the four recipes were foundbe similar. They were about 14.8 mV/sq which correspondedto specific resistivity of 1.77mV cm. This value is lower thanthat achieved by Bollmann using CVD Cu5 and is closer tothe bulk resistivity of copper.

C. Stress of copper films

Figure 3 shows the stress hystersis of the Cu films pduced using recipes ECP#2 and ECP#3. It is found that thwas no significant difference in the as-deposited and posnealed stress vector for the dc- and pulse-plated Cu filThe as-deposited stress were 38.8 and 62.7 MPa, andpostannealed stress were 238.7 and 276.1 MPa for fiplated by recipes ECP#2 and ECP#3, respectively. Allfilm stresses were found to be tensile.

However, there were two significant differences betwethe stress hystersis of the dc- and pulse-plated films: mathe first relaxation temperature and the stress level at 200It can be seen from Fig. 3 that dc-plated film underwentfirst relaxation at a temperature of 100 °C and it occurred150 °C for the case of pulse-plated film. The stress of thefilms experienced at 200 °C was found to be compressivethe pulse-plated film had a lower stress value of 126.0 Mcompared to that of dc-plated film which had a stress leve293.9 MPa. The differences observed could again be cauby the fact that pulse-plating resulted in denser deposits cpared to dc process.15 The first relaxation was easier to occin a dc-plated more porous Cu film but it underwent momicrostructural change during grain growth and resultedhigher film stress at high temperature.

D. Polish rate of copper films

Table III shows the polish rate and polish rate nonunifmity across the wafer (U%) for the four Cu films produced

TABLE III. Polish rate of ECP Cu film.

RecipePolish rate~Å/min!

Polish rateU%

ECP#1 6371.6 2.726ECP#2 7289.2 1.874ECP#3 7124.6 2.550ECP#4 210.7 57.892


FIG. 4. Polish profile for ECP Cu filmsproduced using recipes:~a! ECP#2and ~b! ECP#4.

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using all the ECP recipes. All the dc and higherI f pulse-plating processes produced Cu film having an average porate of 7000 Å/min with the polish rateU% less than 3%.However, in the case of the higherI r pulse-plated film, thepolish rate reduced very significantly to only 210 Å/min athe polish rateU% jumped to 58%.

There was also a difference in term of the polish profileshown in Fig. 4. The first three recipes produced films shoing a fluctuating profile across the wafer@Fig. 4~a!# giving anaverage polish rate of 7000 Å/min with an standard deviatof 300 Å but the fourth recipe produced film showing a domprofile @Fig. 4~b!# with the polish rate decreasing from 40Å/min at the center of the wafer to,100 Å/min at the edgeThe higherI r pulse-plated film had very dense electrodepits with very high film roughness~see Table I! and thus moredifficult to be polished, resulted in the dome profile.

E. Purity of copper films

The depth profile of trapped additives~C,O,Cl,S! in theplated Cu films was examined by SIMS and the resultsshown in Fig. 5. The Cu film at the center of the wafeplated using both recipes ECP#2 and ECP#3 did not sany difference in total impurities concentration~6.4E02 and6.1E02 c/s, respectively!. Slightly higher impurities concentration ~8.6E02 c/s! was found at the wafer edge for the filmfrom recipe ECP#2 but the film at the wafer edge produby recipe ECP#3 displayed much higher impurities conctration ~13.5E02 c/s!. The significant difference in the C


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grain size produced by the two recipes as observed in Ficould not be caused by the impurities present in the filalthough higher impurities concentration found in the Cfilm was believed to have resulted in smaller grains beformed due to the pinning effect of the grains thereby spressing their growth rate during annealing.16 This result im-plied that the Cu polish rate was not influenced by the fiimpurities concentration but depended more on the surfroughness.

F. Gap fill capability

Figure 6 shows the effect of dc- and pulse-plating pcesses on the gap fill capability of the ICV wafers. The mtistep dc recipe~i.e., ECP#1! resulted in conformal plating aseen in Fig. 6~a! and it could be observed that there waspinch-off effect at the top of the via due to the Cu seoverhang, resulting in a large center seam. With the adtional dc reverse steps in recipe ECP#2, Fig. 6~b! showed animprovement in gap fill with more Cu being plated at thbottom. However, the result was still not acceptable aslarge center seam still remained. These observations icated that dc plating may not be suitable for the fillingsuch large vias.

In the case of pulse plating, the process showed a sigcant improvement in gap fill capability with a reductionthe size of the center void@Figs. 6~c! and 6~d!#. The pinch-off effect was also greatly reduced and an increase in botcoverage was seen. The center void reduced in size wheI r

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FIG. 5. SIMS profile for Cu films atthe wafer edge produced using recpes:~a! ECP#2 vs~b! ECP#3.

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FIG. 6. FIB pictures showing gap fillresults of Cu films plated using recipe~a! ECP#1,~b! ECP#2,~c! ECP#3, and~d! ECP#4.

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was increased to be greater thanI f . This implies that havinghigher polarization during the reverse plating step wouldgood for gap fill as a result of the reduction of the pinch-effect caused by seed overhang. However, the Cu film pduced would be difficult to CMP polish due to the high filroughness. Therefore, in order to achieve acceptable gain the ICV wafers with only a small conical center void@seeFig. 6~d!#, the Cu electroplating process could be applusing PP reverse wave form and there would be a neeoptimize the ratio of the forward and reverse currents so aavoid having CMP difficulty of the Cu film.

IV. CONCLUSION

The roughness of dc-plated Cu film was found to beleast three times lower than that of pulse-plated film withlatter being strongly dependent on the magnitude of forwand reverse currents. The wafer edge of the pulse-platedposits also exhibited higher film roughness compared tocenter of the wafer. This caused a significant differencereflectivity between the dc- and pulse-plated films. Thedeposited dc- and pulse-plated Cu films were found to hspecific resistivities of;2.2 and;2.1 mV cm, respectively,with a reduction to a similar value of 1.77mV cm after an-nealing at 200 °C.

All the dc and higherI f pulse-plating processes producCu films having an average polish rate of 7000 Å/min wthe polish rateU% less than 3% while the higherI r pulse-plated film showed a very low polish rate of 210 Å/min withe polish rateU% at 58%. The dc and higherI f pulse-platedfilms showed a fluctuating profile across the wafer buthigher I r pulse-plated film resulted in a dome profile. Thmultistep dc plating process was found to be unsuitablethe filling of large vias in the ICV wafers as it resulted

J. Vac. Sci. Technol. B, Vol. 22, No. 3, May ÕJun 2004

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conformal plating and a large center seam was seen duthe pinch-off effect at the top of the via. The pulse-platiprocess showed a significant improvement in gap fill cability with a reduction in the size of the center void. Thpinch-off effect was also greatly reduced when higherI r wasused and an increase in bottom coverage could also be sresulting in acceptable gap fill with only a small center voin the ICV wafers.

ACKNOWLEDGMENTS

The authors would like to thank the Metrology and Faure Analysis groups under the Semiconductor Process Tnologies Department, Institute of Microelectronics for tAFM, FIB and SIMS works and Tachyon Semiconductor fthe joint development of the ICV patterned wafers.

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Characterization of Electroplated Cu films for 3 dimensional advanced packaging