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Digital Integrated CircuitsA Design PerspectiveJan M. Rabaey Anantha Chandrakasan Borivoje Nikoli

Timing IssuesJanuary 2003EE141 Digital Integrated

Circuits2nd

Timing Issues

1

Synchronous Timing

CLK In R1 Cin Combinational Logic Cout R2

Out

EE141 Digital Integrated

Circuits2nd

Timing Issues

2

Timing Definitions

EE141 Digital Integrated

Circuits2nd

Timing Issues

3

Latch ParametersD Q Clk

TClk D tc-q PWm thold td-q tsu

Q

Delays can be different for rising and falling data transitionsEE141 Digital Integrated

Circuits2nd

Timing Issues

4

Register ParametersD Q Clk

TClk D tsu Q tc-q Delays can be different for rising and falling data transitionsEE141 Digital Integrated

thold

Circuits2nd

Timing Issues

5

Clock Uncertainties4 Power Supply 3 Interconnect Devices 6 Capacitive Load 7 Coupling to Adjacent Lines

2

5 Temperature 1 Clock Generation

Sources of clock uncertaintyEE141 Digital Integrated

Circuits2nd

Timing Issues

6

Clock Nonidealities

Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK

Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL

Variation of the pulse width Important for level sensitive clocking

EE141 Digital Integrated

Circuits2nd

Timing Issues

7

Clock Skew and JitterClktSK

Clk

tJS

Both skew and jitter affect the effective cycle time Only skew affects the race margin

EE141 Digital Integrated

Circuits2nd

Timing Issues

8

Clock Skew# of registers Earliest occurrence of Clk edge Nominal /2 Latest occurrence of Clk edge Nominal + /2

Insertion delay Max Clk skew

Clk delay

9

EE141 Digital Integrated

Circuits2nd

Timing Issues

Positive and Negative SkewIn CLK R1 D Q tCLK1 delay (a) Positive skew R1 D Q tCLK1 delay(b) Negative skew10

Combinational Logic

R2 D Q tCLK2delay Combinational Logic

R3D Q

tCLK3

In

Combinational Logic

R2 D Q tCLK2 delay Combinational Logic

R3 D Q tCLK3 CLK

EE141 Digital Integrated

Circuits2nd

Timing Issues

Positive SkewTCLK + d CLK1 1d

TCLK

3

CLK2

2d + th

4

Launching edge arrives before the receiving edge11

EE141 Digital Integrated

Circuits2nd

Timing Issues

Negative SkewTCLK + d

CLK1

1

TCLK

3

CLK2

2

d

4

Receiving edge arrives before the launching edge12

EE141 Digital Integrated

Circuits2nd

Timing Issues

Timing ConstraintsIn R1D Q

R2 Combinational LogicD Q

CLK tc - q

tCLK1 tlogictlogic, cd tc - q, cd tsu, thold

tCLK2

Minimum cycle time: T - = tc-q + tsu + tlogicWorst case is when receiving edge arrives early (positive )EE141 Digital Integrated

Circuits2nd

Timing Issues

13

Timing ConstraintsIn R1D Q

R2 Combinational LogicD Q

CLK tc - q

tCLK1 tlogictlogic, cd tc - q, cd tsu, thold

tCLK2

Hold time constraint: t(c-q, cd) + t(logic, cd) > thold + Worst case is when receiving edge arrives late Race between data and clockEE141 Digital Integrated

Circuits2nd

Timing Issues

14

Impact of JitterCLK

TC LK

t j itter -tji tte r

In

REGS

Combinational Logic t log ic t log ic, cd

CLK tc-q , tc-q, ts u, thold tjitter

cd

EE141 Digital Integrated

Circuits2nd

Timing Issues

15

Longest Logic Path in Edge-Triggered SystemsTSU Clk TClk-Q TLM T

TJI +

Latest point of launching

Earliest arrival of next cycle

EE141 Digital Integrated

Circuits2nd

Timing Issues

16

Clock Constraints in Edge-Triggered SystemsIf launching edge is late and receiving edge is early, the data will not be too late if:

Tc-q + TLM + TSU < T TJI,1 TJI,2 - Minimum cycle time is determined by the maximum delays through the logic

Tc-q + TLM + TSU + + 2 TJI < TSkew can be either positive or negativeEE141 Digital Integrated

Circuits2nd

Timing Issues

17

Shortest PathEarliest point of launching

Clk

TClk-Q TLm

Clk

THData must not arrive before this time

Nominal clock edge

EE141 Digital Integrated

Circuits2nd

Timing Issues

18

Clock Constraints in Edge-Triggered SystemsIf launching edge is early and receiving edge is late:

Tc-q + TLM TJI,1 < TH + TJI,2 + Minimum logic delay

Tc-q + TLM < TH + 2TJI+

EE141 Digital Integrated

Circuits2nd

Timing Issues

19

How to counter Clock Skew?Negative SkewREG

REG

REG

.

REG

log

Out

In

Positive Skew Clock Distribution

Data and Clock Routing20

EE141 Digital Integrated

Circuits2nd

Timing Issues

Flip-Flop Based TimingSkew

Logic delay TSU

Flip-flop delay

Flip -flop

TClk-Q

=0Logic

=1

Representation after M. Horowitz, VLSI Circuits 1996.EE141 Digital Integrated

Circuits2nd

Timing Issues

21

Flip-Flops and Dynamic LogicLogic delay TSU TClk-Q TClk-Q TSU

=0

=1

=0

=1

Logic delay Precharge

Evaluate

Evaluate

Precharge

Flip-flops are used only with static logicEE141 Digital Integrated

Circuits2nd

Timing Issues

22

Latch timingtD-QD Clk Q

When data arrives to transparent latch Latch is a soft barrier

tClk-Q

When data arrives to closed latch Data has to be re-launched

EE141 Digital Integrated

Circuits2nd

Timing Issues

23

Single-Phase Clock with Latches Latch

Logic

Tskl Clk

Tskl

Tskt

Tskt

PW PEE141 Digital Integrated

Circuits2nd

Timing Issues

24

Latch-Based DesignL1 latch is transparent when = 0

L2 latch is transparent when = 1

L1 Latch

Logic

L2 Latch

Logic

EE141 Digital Integrated

Circuits2nd

Timing Issues

25

Slack-borrowingIn L1 D Q a CLB_A t p d,A b L2 D Q c CLB_B t p d,B L1 d D Q e

CLK1

CLK2 TC LK

CLK1

CLK1

CLK2 slack passed to next stage t pd,A a valid tD Q tpd,B t DQ e valid d valid26

b valid c valid

EE141 Digital Integrated

Circuits2nd

Timing Issues

Latch-Based TimingStatic logic

Skew

L1 Latch

Logic

L2 Latch

=1L1 latch

L2 latch

Logic

Long path

=0

Can tolerate skew!Short pathEE141 Digital Integrated

Circuits2nd

Timing Issues

27

Clock Distribution

H-tree

CLK

Clock is distributed in a tree-like fashionEE141 Digital Integrated

Circuits2nd

Timing Issues

28

More realistic H-tree

[Restle98]EE141 Digital Integrated

Circuits2nd

Timing Issues

29

The Grid SystemGCL K Driver

Driver

Driver

GCLK

GCLK

No rc-matching Large powerDriver GCL K

EE141 Digital Integrated

Circuits2nd

Timing Issues

30

Example: DEC Alpha 21164Clock Frequency: 300 MHz - 9.3 Million Transistors Total Clock Load: 3.75 nF Power in Clock Distribution network : 20 W (out of 50) Uses Two Level Clock Distribution: Single 6-stage driver at center of chip Secondary buffers drive left and right side clock grid in Metal3 and Metal4 Total driver size: 58 cm!

EE141 Digital Integrated

Circuits2nd

Timing Issues

31

21164 Clockingtcycle= 3.3ns trise = 0.35ns tskew = 150ps

Clock waveformfinal drivers

2 phase single wire clock, distributed globally 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width

pre-driver

Location of clock driver on dieEE141 Digital Integrated

Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variationTiming Issues32

Circuits2nd

Clock Drivers

EE141 Digital Integrated

Circuits2nd

Timing Issues

33

Clock Skew in Alpha Processor

EE141 Digital Integrated

Circuits2nd

Timing Issues

34

EV6 (Alpha 21264) Clocking 600 MHz 0.35 micron CMOStcycle= 1.67ns

trise = 0.35ns Global clock waveform

tskew = 50ps 2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width

PLL

Local clocks can be gated off to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checkingTiming Issues35

EE141 Digital Integrated

Circuits2nd

21264 Clocking

EE141 Digital Integrated

Circuits2nd

Timing Issues

36

EV6 Clock Resultsps 5 10 15 20 25 30 35 40 45 50 GCLK Skew(at Vdd/2 Crossings)EE141 Digital Integrated

ps 300 305 310 315 320 325 330 335