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Digital Design 2e
Copyright © 2010
Frank Vahid11
Digital Design
Chapter 8:
Programmable Processors
Slides to accompany the textbook Digital Design, with RTL Design, VHDL,
and Verilog, 2nd Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2010.
http://www.ddvahid.com
Copyright © 2010 Frank Vahid
Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf
with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means.
Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors
may obtain PowerPoint source or obtain special use permissions from Wiley – see http://www.ddvahid.com for information.
Digital Design 2e
Copyright © 2010
Frank Vahid2
Introduction
• Programmable (general-purpose) processor– Mass-produced, then programmed to implement different processing tasks
• Well-known common programmable processors: Pentium, Sparc, PowerPC
• Lesser-known but still common: ARM, MIPS, 8051, PIC, AVR– Low-cost embedded processors found in cell phones, blinking shoes, etc.
– Instructive to design a very simple programmable processor• Real processors can be much more complex
8.1
Seatbelt warninglight single-purpose
processor
2x4
e
23
10
c0 c1 c2xt1
reg
xt0 xt2
++
∗ ∗∗
x(t) x(t-1) x(t-2)
Instructionmemory I
Controller
PC IR0
Register fileRF
Data memory D
ALU
n-bit2x1
Seatbelt warning light
program
3-tap FIR filterprogram
Otherprograms
3-tap FIR filtersingle-purpose processor
General-purpose processor
a
Control unit Datapath
Note: Slides with animation are denoted with a small red "a" near the animated items
.
Digital Design 2e
Copyright © 2010
Frank Vahid3
Basic Architecture
• Processing generally consists of:– Loading some data
– Transforming that data
– Storing that data
• Basic datapath: Useful circuit in a programmable processor– Can read/write data memory, where main
data exists
– Has register file to hold data locally
– Has ALU to transform local data
8.2
Register file RF
Data memory D
ALU
n-bit2x1
somehowconnected
to theoutsideworld
Datapath
.
Digital Design 2e
Copyright © 2010
Frank Vahid4
Basic Datapath Operations• Load operation: Load data from data memory to RF
• ALU operation: Transforms data by passing one or two RF register values through
ALU, performing operation (ADD, SUB, AND, OR, etc.), and writing back into RF.
• Store operation: Stores RF register value back into data memory
• Each operation can be done in one clock cycle
Register file RF
Data memory D
ALU
n-bit2x1
Register file RF
Data memory D
ALU
n-bit2x1
Register file RF
Data memory D
ALU
n-bit2x1
Load operation ALU operation Store operation
a
.
Digital Design 2e
Copyright © 2010
Frank Vahid5
Basic Datapath Operations
• Q: Which are valid single-cycle operations for given datapath?– Move D[1] to RF[1] (i.e., RF[1] = D[1])
• A: YES – That's a load operation
– Store RF[1] to D[9] and store RF[2] to D[10]• A: NO – Requires two separate store operations
– Add D[0] plus D[1], store result in D[9]• A: NO – ALU operation (ADD) only works with RF. Requires two load operations
(e.g., RF[0]=D[0]; RF[1]=D[1], an ALU operation (e.g., RF[2]=RF[0]+RF[1]), and a store operation (e.g., D[9]=RF[2])
Register file RF
Data memory D
ALU
n-bit2x1
Register file RF
Data memory D
ALU
n-bit2x1
Register file RF
Data memory D
ALU
n-bit2x1
Load operation ALU operation Store operation
a
.
Digital Design 2e
Copyright © 2010
Frank Vahid6
Basic Architecture – Control Unit
• D[9] = D[0] + D[1] – requires a sequence of four datapath operations:
0: RF[0] = D[0]
1: RF[1] = D[1]
2: RF[2] = RF[0] + RF[1]
3: D[9] = RF[2]
• Each operation is an instruction– Sequence of instructions – program
– Looks cumbersome, but that's the world of programmable processors –Decomposing desired computations into processor-supported operations
– Store program in Instruction memory
– Control unit reads each instruction and executes it on the datapath • PC: Program counter – address of
current instruction
• IR: Instruction register – current instruction
Register file RF
Data memory D
ALU
n-bit2x1
Datapath
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
a
.
Digital Design 2e
Copyright © 2010
Frank Vahid7
Basic Architecture – Control Unit
• To carry out each instruction, the control unit must:– Fetch – Read instruction from inst. mem.
– Decode – Determine the operation and operands of the instruction
– Execute – Carry out the instruction's operation using the datapath
a
RF[0]=D[0]0−>1
R[0]: ?? ���� 99
"load"
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
(a)
Fetch
RF[0]=D[0]
Instruction memory I
Control unit
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
1
(b)
Controller
Decode
Register file RF
Data memory DD[0]: 99
ALU
n-bit2x1
Datapath
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
RF[0]=D[0]1
(c)
Execute
.
Digital Design 2e
Copyright © 2010
Frank Vahid8
Basic Architecture – Control Unit
• To carry out each instruction, the control unit must:– Fetch – Read instruction from inst. mem.
– Decode – Determine the operation and operands of the instruction
– Execute – Carry out the instruction's operation using the datapath
a
RF[1]=D[1}1−>2
R[1]: ?? ���� 102
"load"
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
(a)
Fetch
RF[1]=D[1]
Instruction memory I
Control unit
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
2
(b)
Controller
Decode
Register file RF
Data memory DD[1]: 102
ALU
n-bit2x1
Datapath
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
RF[1]=D[1]2
(c)
Execute
.
Digital Design 2e
Copyright © 2010
Frank Vahid9
Basic Architecture – Control Unit
• To carry out each instruction, the control unit must:– Fetch – Read instruction from inst. mem.
– Decode – Determine the operation and operands of the instruction
– Execute – Carry out the instruction's operation using the datapath
a
RF[2]=RF[0]+RF[1]2−>3
R[2]: ?? ���� 201
"ALU (add)"
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
(a)
Fetch
RF[2]=RF[0]+RF[1]
Instruction memory I
Control unit
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
3
(b)
Controller
Decode
Register file RF
Data memory D
ALU
n-bit2x1
Datapath
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
RF[2]=RF[0]+RF[1]3
(c)
Execute
99 102201
.
Digital Design 2e
Copyright © 2010
Frank Vahid10
Basic Architecture – Control Unit
• To carry out each instruction, the control unit must:– Fetch – Read instruction from inst. mem.
– Decode – Determine the operation and operands of the instruction
– Execute – Carry out the instruction's operation using the datapath
a
D[9]=RF[2]3−>4
R[2]: 201
"store"
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
(a)
Fetch
D[9]=RF[2]
Instruction memory I
Control unit
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
4
(b)
Controller
Decode
Register file RF
Data memory D
ALU
n-bit2x1
Datapath
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
D[9]=RF[2]4
(c)
Execute
D[9]=?? ���� 201
.
Digital Design 2e
Copyright © 2010
Frank Vahid11
Basic Architecture – Control Unit
Fetch
Decode
Init
PC=0
Execute
IR=I[PC]PC=PC+1
Controller
Register file RF
Data memory D
ALU
n-bit2x1
Datapath
Instruction memory I
Control unit
Controller
PC IR
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2]
.
Digital Design 2e
Copyright © 2010
Frank Vahid12
Creating a Sequence of Instructions
• Q: Create sequence of instructions to compute D[3] = D[0]+D[1]+D[2] on earlier-introduced processor
• A1: One possible sequence
• First load data memory locations into register file
• R[3] = D[0]
• R[4] = D[1]
• R[2] = D[2]
(Note arbitrary register locations)
• Next, perform the additions
• R[1] = R[3] + R[4]
• R[1] = R[1] + R[2]
• Finally, store result
• D[3] = R[1]
a
• A2: Alternative sequence
• First load D[0] and D[1] and add them
• R[1] = D[0]
• R[2] = D[1]
• R[1] = R[1] + R[2]
• Next, load D[2] and add
• R[2] = D[2]
• R[1] = R[1] + R[2]
a
• Finally, store result
• D[3] = R[1]
.
Digital Design 2e
Copyright © 2010
Frank Vahid13
Number of Cycles
• Q: How many cycles are needed to execute six instructions using the earlier-described processor?
• A: Each instruction requires 3 cycles – 1 to fetch, 1 to decode, and 1 to execute
• Thus, 6 instr * 3 cycles/instr = 18 cycles
a
.
Digital Design 2e
Copyright © 2010
Frank Vahid14
Three-Instruction Programmable Processor
• Instruction Set – List of allowable instructions and their representation in memory, e.g.,
– Load instruction—0000 r3r2r1r0 d7d6d5d4d3d2d1d0
– Store instruction—0001 r3r2r1r0 d7d6d5d4d3d2d1d0
– Add instruction—0010 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0
8.3
Instruction memory I
0: 0000 0000 00000000
1: 0000 0001 00000001
2: 0010 0010 0000 0001
3: 0001 0010 00001001
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2}
Desired program
a
opcode operands
Instructions in 0s and 1s –
machine code
a
.
Digital Design 2e
Copyright © 2010
Frank Vahid15
Program for Three-Instruction Processor
Register file RF
Data memory D
ALU
n-bit2⋅ 1
Datapath
Instruction memoryI
Control unit
Controller
PC IR
0: 0000 0000 000000001: 0000 0001 000000012: 0010 0010 0000 00013: 0001 0010 00001001
0: RF[0]=D[0]1: RF[1]=D[1]2: RF[2]=RF[0]+RF[1]3: D[9]=RF[2}
Desired program
ComputesD[9]=D[0]+D[1]
.
Digital Design 2e
Copyright © 2010
Frank Vahid16
Program for Three-Instruction Processor
• Another example program in machine code– Compute D[5] = D[5] + D[6] + D[7]
0: 0000 0000 00000101 // RF[0] = D[5]
1: 0000 0001 00000110 // RF[1] = D[6]
2: 0000 0010 00000111 // RF[2] = D[7]
3: 0010 0000 0000 0001 // RF[0] = RF[0] + RF[1]
// which is D[5]+D[6]
4: 0010 0000 0000 0010 // RF[0] = RF[0] + RF[2]
// now D[5]+D[6]+D[7]
5: 0001 0000 00000101 // D[5] = RF[0]
–Load instruction—0000 r3r2r1r0 d7d6d5d4d3d2d1d0
–Store instruction—0001 r3r2r1r0 d7d6d5d4d3d2d1d0
–Add instruction—0010 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0
.
Digital Design 2e
Copyright © 2010
Frank Vahid17
Assembly Code
• Machine code (0s and 1s) hard to work with
• Assembly code – Uses mnemonics
– Load instruction—MOV Ra, d
• specifies the operation RF[a]=D[d]. a must be 0,1, ..., or 15—so R0 means RF[0], R1 means RF[1], etc. d must be 0, 1, ..., 255
– • Store instruction—MOV d, Ra
• specifies the operation D[d]=RF[a]
– • Add instruction—ADD Ra, Rb, Rc
• specifies the operation RF[a]=RF[b]+RF[c]
0: MOV R0, 01: MOV R1, 12: ADD R2, R0, R13: MOV 9, R2
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
Desired program0: 0000 0000 00000000
1: 0000 0001 00000001
2: 0010 0010 0000 0001
3: 0001 0010 00001001
machine code assembly code
.
Digital Design 2e
Copyright © 2010
Frank Vahid18
Control-Unit and Datapath for Three-Instruction
Processor• To design the processor, we can begin with a high-level state machine
description of the processor's behavior
Fetch
Decode
Init
PC:=0
Store
IR:=I[PC]PC:=PC+1
Load Add
RF[ra] :=
RF[rb]+
RF[rc]
D[d]:=RF[ra]RF[ra]:=D[d]
op=="0000" op=="0001" op=="0010"
.
Digital Design 2e
Copyright © 2010
Frank Vahid19
Control-Unit and Datapath for Three-Instruction
Processor• Create detailed connections among components
PC
clr up
16
IR
Id
16
16
Idatardaddr
Controller
Control unit Datapath
RF_W_wr
RF_Rp_addr
RF_Rq_addr
RF_Rq_rd
RF_Rp_rd
RF_W_addr
D_addr 8
D_rd
D_wr
RF_s
alu_s0
addr D
rd
wr256x16
16x16RF
16-bit2x1
W_data R_data
Rp_data Rq_data
W_dataW_addr
W_wr
Rp_addr
Rp_rd
Rq_addr
Rq_rd
0
16
16
16
1616
16
s1
A Bs0 ALU
4
4
4
Fetch
Decode
Init
PC:=0
Store
IR:=I[PC]PC:=PC+1
Load Add
RF[ra] :=
RF[rb]+
RF[rc]
D[d]:=RF[ra]RF[ra]:=D[d]
op=="0000" op=="0001" op=="0010"
PC_clrPC_inc
I_rd IR_ld
@
Digital Design 2e
Copyright © 2010
Frank Vahid20
Control-Unit and Datapath for Three-Instruction
Processor• Convert high-level state machine
description of entire processor to FSM description of controller that uses datapath and other components to achieve same behavior
Fetch
Decode
Init
PC=0
Store
IR=I[PC]PC=PC+1
Load Add
RF[ra] =
RF[rb]+
RF[rc]
D[d]=RF[ra]RF[ra]=D[d]
op=0000 op=0001 op=0010
PCclr up
16IR
Id
16
16
Idatardaddr
Controller
Control unit Datapath
RF_W_wrRF_Rp_addr
RF_Rq_addr
RF_Rq_rd
RF_Rp_rd
RF_W_addr
D_addr 8
D_rd
D_wr
RF_s
alu_s0
addr D
rd
wr256x16
16x16RF
16-bit2x1
W_dataR_data
Rp_data Rq_data
W_dataW_addr
W_wrRp_addr
Rp_rdRq_addr
Rq_rd
0
16
16
16
1616
16
s1
A Bs0 ALU
4
4
4
Fetch
Decode
Init
PC=0PC_ clr=1
Store
IR=I[PC] PC=PC+1
I_rd=1 PC_inc=1IR_ld=1
Load Add
RF[ra] = RF[rb]+
RF[rc]
D[d]=RF[ra]RF[ra]=D[d]
op=0000 op=0001 op=0010
D_addr=d
D_wr=1RF_s=XRF_Rp_addr=raRF_Rp_rd=1
RF_Rp_addr=rbRF_Rp_rd=1
RF_s=0RF_Rq_addr=rcRF_Rq _rd=1RF_W_addr=raRF_W_wr=1alu_s0=1
D_addr=d
D_rd=1RF_s=1RF_W_addr=raRF_W_wr=1
Execute
states
a
ь
Digital Design 2e
Copyright © 2010
Frank Vahid21
A Six-Instruction Programmable Processor
• Let's add three more instructions:– Load-constant instruction—0011 r3r2r1r0 c7c6c5c4c3c2c1c0
• MOV Ra, #c—specifies the operation RF[a]=c
– Subtract instruction—0100 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0
• SUB Ra, Rb, Rc—specifies the operation RF[a]=RF[b] – RF[c]
– Jump-if-zero instruction—0101 ra3ra2ra1ra0 o7o6o5o4o3o2o1o0
• JMPZ Ra, offset—specifies the operation PC = PC + offset if RF[a] is 0
8.4
Շ㉠
Digital Design 2e
Copyright © 2010
Frank Vahid22
Extending the Control-Unit and Datapath1: The load constant instruction requires that the register file be able to load data from IR[7..0], in addition to data from data memory or the ALU output. Thus, we widen the register file’s multiplexer from 2x1 to 3x1, add another mux control signal, and also create a new signal coming from the controller labeled RF_W_data, which will connect with IR[7..0].
2: The subtract instruction requires that we use an ALU capable of subtraction, so we add another ALU control signal.
3: The jump-if-zero instruction requires that we be able to detect if a register is zero, and that we be able to add IR[7..0] to the PC.
3a: We insert a datapath component to detect if the register file’s Rp read port is all zeros (that component would just be a NOR gate).
3b: We also upgrade the PC register so it can be loaded with PC plus IR[7..0]. The adder used for this also subtracts 1 from the sum, to compensate for the fact that the Fetch state already added 1 to the PC.
Datapath
RF_Rp_addr
RF_Rq_addr
RF_Rp_zero
RF_W_addr
D_addr
D_rd
D_wr
RF_s1
RF_W_data
RF_s0
alu_s1
alu_s0
addr D
rd
wr256x16
16x16RF
16-bit3x1
W_data R_data
Rp_data Rq_data
W_dataW_addr
W_wrRp_addr
Rp_rdRq_addr
Rq_rd
0
16
16
16
1616
16
s1s0
12
A Bs1s0
ALU
4
4
4
3a
2
=0
1
18
8
s1
0
0
1
s0
0
1
0
ALU operation
pass A through
A+B
A-B
PCclrld up
16
IRId
16datardaddr
Controller
Control unit
a+b-1
16
∗
∗
+
3b IR[7..0]
PC
_cl
r
PC
_ld
PC
_in
c
IR_
ld
Շ靐
Digital Design 2e
Copyright © 2010
Frank Vahid23
Controller FSM for the Six-Instruction Processor
Fetch
Decode
Init
PC_clr=1
Store
I_rd=1PC_inc=1IR_ld=1
Load Add
D_addr=dD_wr=1RF_s1=XRF_s0=XRF_Rp_addr=raRF_Rp_rd=1
RF_Rp_addr=rbRF_Rp_rd=1RF_s1=0RF_s0=0RF_Rq_add=rcRF_Rq_rd=1RF_W_addr_raRF_W_wr=1alu_s1=0alu_s0=1
D_addr=dD_rd=1RF_s1=0RF_s0=1RF_W_addr=raRF_W_wr=1
SubtractLoad-constant
Jump-if-zero
RF_Rp_addr=rbRF_Rp_rd=1RF_s1=0RF_s0=0RF_Rq_addr=rcRF_Rq_rd=1RF_W_addr=raRF_W_wr=1alu_s1=1alu_s0=0
RF_Rp_addr=raRF_Rp_rd=1
RF_s1=1RF_s0=0RF_W_addr=raRF_W_wr=1
Jump-if-zero-jmp
PC_ld=1
op=0100 op=0101op=0010 op=0011op=0001op=0000
RF
_R
p_
zero
RF
_R
p_
zero
'
Ո뙐
Digital Design 2e
Copyright © 2010
Frank Vahid24
Program for the Six-Instruction Processor
• Example program – Count number of non-zero words in D[4] and D[5]– Result will be either 0, 1, or 2
– Put result in D[9]
PC_clrPC_ld PC_incIR_ld
0011 0000 00000000
0011 0001 00000001
0000 0010 00000100
0101 0010 00000010
0010 0000 0000 0001
0000 0010 00000101
0101 0010 00000010
0010 0000 0000 0001
0001 0000 00001001
MOV R0, #0; // initialize result to 0
MOV R1, #1; // constant 1 for incrementing result
MOV R2, 4; // get data memory location 4
JMPZ R2, lab1; // if zero, skip next instruction
ADD R0, R0, R1; // not zero, so increment result
lab1:MOV R2, 5; // get data memory location 5
JMPZ R2, lab2; // if zero, skip next instruction
ADD R0, R0, R1; //not zero, so increment result
lab2:MOV 9, R0; // store result in data memory location 9
(a) (b)
Ո뙐
Digital Design 2e
Copyright © 2010
Frank Vahid25
Further Extensions to the Programmable
Processor• Typical processor instruction set will
contain dozens of data movement (e.g., loads, stores), ALU (e.g., add, sub), and flow-of-control (e.g., jump) instructions
– Extending the control-unit/datapath follows similarly to previously-shown extensions
• Input/output extensions– Certain memory locations may actually be
external pins
• e.g, D[240] may represent 8-bit input I0, D[255] may represent 8-bit output P7
8.5
256x16 D
W_data R_data
addr
rd
wr
0:
1:
2:
239:
240:
241:
248:
255:
00..0
00..0
I0
I1
P0
P7
Digital Design 2e
Copyright © 2010
Frank Vahid26
Program using I/O Extensions – Recall Chpt 1
C-Program Example• Microprocessors a
common choice to implement a digital system
– Easy to program
– Cheap (as low as $1)
– Available now
I3I4I5I6I7
I2I1I0
P3P4P5P6P7
P2P1P0 void main()
{
while (1) {
P0 = I0 && !I1;
// F = a and !b,
}
}0
F
b
a
1
0
1
0
1
6:00 7:057:06 9:009:01 time
Desired motion-at-night detectorProgrammed
microprocessor
Custom designed
digital circuit
@
Digital Design 2e
Copyright © 2010
Frank Vahid27
Program Using Input/Output Extensions
0: MOV R0, 240 // move D[240], which is the value at pin I0, into R0
1: MOV R1, 241 // move D[241], which is that value at pin I1, into R1
2: NOT R1, R1 // compute !I1, assuming existence of a complement instruction
3: AND R0, R0, R1 // compute I0 && !I1, assuming an AND instruction
4: MOV 248, R0 // move result to D[248], which is pin P0
256x16 D
W_data R_data
addr
rdwr
0:
1:
2:
239:
240:
241:
248:
255:
00..0
00..0
I0
I1
P0
P7
Underlying assembly code for C expression I0 && !I1.
void main()
{
while (1) {
P0 = I0 && !I1;
// F = a and !b,
}
}
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Digital Design 2e
Copyright © 2010
Frank Vahid28
Chapter Summary
• Programmable processors are widely used– Easy availability, short design time
• Basic architecture– Datapath with register file and ALU
– Control unit with PC, IR, and controller
– Memories for instructions and data
– Control unit fetches, decodes, and executes
• Three-instruction processor with machine-level programs– Extended to six instructions
– Real processors have dozens or hundreds of instructions
– Extended to access external pins
– Modern processors are far more sophisticated
• Instructive to see how one general circuit (programmable processor) can execute variety of behaviors just by programming 0s and 1s into an instruction memory
