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Chapter8<1>
DigitalDesignandComputerArchitecture,2nd Edition
Chapter8
DavidMoneyHarrisandSarahL.Harris
Chapter8<2>
Chapter8 ::Topics
• Introduction• MemorySystemPerformanceAnalysis
• Caches• VirtualMemory• Memory-MappedI/O• Summary
Chapter8<3>
Processor MemoryAddressMemWrite
WriteDataReadData
WE
CLKCLK
• Computer performance depends on:– Processor performance– Memory system performance
Memory Interface
Introduction
Chapter8<4>
In prior chapters, assumed access memory in 1 clock cycle – but hasn’t been true since the 1980’s
Processor-MemoryGap
Chapter8<5>
• Make memory system appear as fast as processor
• Use hierarchy of memories• Ideal memory:
– Fast– Cheap (inexpensive)– Large (capacity)
But can only choose two!
MemorySystemChallenge
Chapter8<6>
MemoryHierarchy
Technology Price / GB AccessTime (ns)
Bandwidth(GB/s)
Cache
Main Memory
Virtual Memory
Capacity
Spee
d
SRAM $10,000 1
DRAM $10 10 - 50
SSD $1 100,000
25+
10
0.5
0.1HDD $0.1 10,000,000
Chapter8<7>
Exploitlocalitytomakememoryaccessesfast• TemporalLocality:– Localityintime– Ifdatausedrecently,likelytouseitagainsoon– Howtoexploit: keeprecentlyaccesseddatainhigherlevelsofmemoryhierarchy
• SpatialLocality:– Localityinspace– Ifdatausedrecently,likelytousenearbydatasoon– Howtoexploit: whenaccessdata,bringnearbydataintohigherlevelsofmemoryhierarchytoo
Locality
Chapter8<8>
• Hit: data found in that level of memory hierarchy• Miss: data not found (must go to next level)
Hit Rate = # hits / # memory accesses= 1 – Miss Rate
Miss Rate = # misses / # memory accesses= 1 – Hit Rate
• Average memory access time (AMAT): average time for processor to access dataAMAT = tcache + MRcache[tMM + MRMM(tVM)]
MemoryPerformance
Chapter8<9>
• A program has 2,000 loads and stores• 1,250 of these data values in cache• Rest supplied by other levels of memory
hierarchy• What are the hit and miss rates for the cache?
MemoryPerformanceExample1
Chapter8<10>
• A program has 2,000 loads and stores• 1,250 of these data values in cache• Rest supplied by other levels of memory
hierarchy• What are the hit and miss rates for the cache?
Hit Rate = 1250/2000 = 0.625Miss Rate = 750/2000 = 0.375 = 1 – Hit Rate
MemoryPerformanceExample1
Chapter8<11>
• Suppose processor has 2 levels of hierarchy: cache and main memory
• tcache = 1 cycle, tMM = 100 cycles• What is the AMAT of the program from
Example 1?
MemoryPerformanceExample2
Chapter8<12>
• Suppose processor has 2 levels of hierarchy: cache and main memory
• tcache = 1 cycle, tMM = 100 cycles• What is the AMAT of the program from
Example 1?
AMAT = tcache + MRcache(tMM)= [1 + 0.375(100)] cycles= 38.5 cycles
MemoryPerformanceExample2
Chapter8<13>
• Amdahl’s Law: the effort spent increasing the performance of a subsystem is wasted unless the subsystem affects a large percentage of overall performance
• Co-founded 3 companies, including one called Amdahl Corporation in 1970
GeneAmdahl,1922-
Chapter8<14>
• Highestlevelinmemoryhierarchy• Fast(typically~1cycleaccesstime)• Ideallysuppliesmostdatatoprocessor• Usuallyholdsmostrecentlyaccesseddata
Cache
Chapter8<15>
• Whatdataisheldinthecache?• Howisdatafound?• Whatdataisreplaced?
Focusondataloads,butstoresfollowsameprinciples
CacheDesignQuestions
Chapter8<16>
• Ideally,cacheanticipatesneededdataandputsitincache
• Butimpossibletopredictfuture• Usepasttopredictfuture– temporalandspatiallocality:– Temporallocality: copynewlyaccesseddataintocache
– Spatiallocality: copyneighboringdataintocachetoo
Whatdataisheldinthecache?
Chapter8<17>
• Capacity(C):– numberofdatabytesincache
• Blocksize(b):– bytesofdatabroughtintocacheatonce
• Numberofblocks(B=C/b):– numberofblocksincache:B =C/b
• Degreeofassociativity(N):– numberofblocksinaset
• Numberofsets(S=B/N):– eachmemoryaddressmapstoexactlyonecacheset
CacheTerminology
Chapter8<18>
• CacheorganizedintoS sets• Eachmemoryaddressmapstoexactlyoneset• Cachescategorizedby#ofblocksinaset:–Directmapped: 1blockperset–N-waysetassociative: N blocksperset– Fullyassociative: allcacheblocksin1set
• Examineeachorganizationforacachewith:– Capacity(C =8words)– Blocksize(b =1word)– So,numberofblocks(B =8)
Howisdatafound?
Chapter8<19>
• C =8 words(capacity)• b =1 word(blocksize)• So,B =8(#ofblocks)
Ridiculouslysmall,butwillillustrateorganizations
ExampleCacheParameters
Chapter8<20>
7 (111)
00...00010000
230 Word Main Memory
mem[0x00...00]mem[0x00...04]mem[0x00...08]mem[0x00...0C]mem[0x00...10]mem[0x00...14]mem[0x00...18]mem[0x00..1C]mem[0x00..20]mem[0x00...24]
mem[0xFF...E0]mem[0xFF...E4]mem[0xFF...E8]mem[0xFF...EC]mem[0xFF...F0]mem[0xFF...F4]mem[0xFF...F8]mem[0xFF...FC]
23 Word Cache
Set Number
Address
00...0000000000...0000010000...0000100000...00001100
00...0001010000...0001100000...0001110000...0010000000...00100100
11...11110000
11...1110000011...1110010011...1110100011...11101100
11...1111010011...1111100011...11111100
6 (110)5 (101)4 (100)3 (011)2 (010)1 (001)0 (000)
DirectMappedCache
Chapter8<21>
DataTag
00Tag Set
ByteOffsetMemory
Address
DataHit
V
=
27 3
27 32
8-entry x(1+27+32)-bit
SRAM
DirectMappedCacheHardware
Chapter8<22>
# MIPS assembly code
addi $t0, $0, 5
loop: beq $t0, $0, done
lw $t1, 0x4($0)
lw $t2, 0xC($0)
lw $t3, 0x8($0)
addi $t0, $t0, -1
j loop
done:
DataTagV
00...001 mem[0x00...04]
000
0
0
00Tag Set
ByteOffsetMemory
AddressV
300100...00
100...0000...00
1mem[0x00...0C]mem[0x00...08]
Set 7 (111)Set 6 (110)Set 5 (101)Set 4 (100)Set 3 (011)Set 2 (010)Set 1 (001)Set 0 (000)
Miss Rate = ?
DirectMappedCachePerformance
Chapter8<23>
# MIPS assembly code
addi $t0, $0, 5
loop: beq $t0, $0, done
lw $t1, 0x4($0)
lw $t2, 0xC($0)
lw $t3, 0x8($0)
addi $t0, $t0, -1
j loop
done:
DataTagV
00...001 mem[0x00...04]
000
0
0
00Tag Set
ByteOffsetMemory
AddressV
300100...00
100...0000...00
1mem[0x00...0C]mem[0x00...08]
Set 7 (111)Set 6 (110)Set 5 (101)Set 4 (100)Set 3 (011)Set 2 (010)Set 1 (001)Set 0 (000)
Miss Rate = 3/15= 20%
Temporal LocalityCompulsory Misses
DirectMappedCachePerformance
Chapter8<24>
# MIPS assembly code
addi $t0, $0, 5
loop: beq $t0, $0, done
lw $t1, 0x4($0)
lw $t2, 0x24($0)
addi $t0, $t0, -1
j loop
done:
DataTagV
00...001 mem[0x00...04]
000
0
0
00Tag Set
ByteOffsetMemory
AddressV
300100...01
00
Set 7 (111)Set 6 (110)Set 5 (101)Set 4 (100)Set 3 (011)Set 2 (010)Set 1 (001)Set 0 (000)
mem[0x00...24]
Miss Rate = ?
DirectMappedCache:Conflict
Chapter8<25>
# MIPS assembly code
addi $t0, $0, 5
loop: beq $t0, $0, done
lw $t1, 0x4($0)
lw $t2, 0x24($0)
addi $t0, $t0, -1
j loop
done:
DataTagV
00...001 mem[0x00...04]
000
0
0
00Tag Set
ByteOffsetMemory
AddressV
300100...01
00
Set 7 (111)Set 6 (110)Set 5 (101)Set 4 (100)Set 3 (011)Set 2 (010)Set 1 (001)Set 0 (000)
mem[0x00...24]
Miss Rate = 10/10= 100%
Conflict Misses
DirectMappedCache:Conflict
Chapter8<26>
DataTag
Tag SetByte
OffsetMemoryAddress
Data
Hit1
V
=
01
00
32 32
32
DataTagV
=
Hit1Hit0
Hit
28 2
28 28
Way 1 Way 0
N-WaySetAssociativeCache
Chapter8<27>
# MIPS assembly code
addi $t0, $0, 5
loop: beq $t0, $0, done
lw $t1, 0x4($0)lw $t2, 0x24($0)
addi $t0, $t0, -1
j loop
done:
DataTagV DataTagV
0 0
00
0
00
0
Way 1 Way 0
Set 3Set 2Set 1Set 0
Miss Rate = ?
N-WaySetAssociativePerformance
Chapter8<28>
# MIPS assembly code
addi $t0, $0, 5
loop: beq $t0, $0, done
lw $t1, 0x4($0)lw $t2, 0x24($0)
addi $t0, $t0, -1
j loop
done:
DataTagV DataTagV
00...001 mem[0x00...04]00...10 1mem[0x00...24]
00
0
00
0
Way 1 Way 0
Set 3Set 2Set 1Set 0
Miss Rate = 2/10 = 20%
Associativity reducesconflict misses
N-WaySetAssociativePerformance
Chapter8<29>
DataTagV DataTagV DataTagV DataTagV DataTagV DataTagV DataTagV DataTagV
Reduces conflict missesExpensive to build
FullyAssociativeCache
Chapter8<30>
• Increaseblocksize:– Blocksize,b =4 words– C =8words– Directmapped(1blockperset)– Numberofblocks,B =2 (C/b =8/4=2)
DataTag
00Tag
ByteOffsetMemory
Address
Data
V
00011011
BlockOffset
32 32 32 32
32
Hit
=
Set
27
27 2
Set 1Set 0
SpatialLocality?
Chapter8<31>
DataTag
00Tag
ByteOffsetMemory
Address
Data
V
00011011
BlockOffset
32 32 32 32
32
Hit
=
Set
27
27 2
Set 1Set 0
CachewithLargerBlockSize
Chapter8<32>
addi $t0, $0, 5
loop: beq $t0, $0, done
lw $t1, 0x4($0)
lw $t2, 0xC($0)
lw $t3, 0x8($0)addi $t0, $t0, -1
j loop
done:
Miss Rate = ?
DirectMappedCachePerformance
Chapter8<33>
addi $t0, $0, 5
loop: beq $t0, $0, done
lw $t1, 0x4($0)
lw $t2, 0xC($0)
lw $t3, 0x8($0)addi $t0, $t0, -1
j loop
done:
00...00 0 11
DataTag
00Tag
ByteOffsetMemory
Address
Data
V
00011011
BlockOffset
32 32 32 32
32
Hit
=
Set
27
27 2
Set 1Set 000...001 mem[0x00...0C]
0mem[0x00...08] mem[0x00...04] mem[0x00...00]
Miss Rate = 1/15 = 6.67%
Larger blocksreduce compulsory missesthrough spatial locality
DirectMappedCachePerformance
Chapter8<34>
• Capacity:C• Blocksize:b• Numberofblocksincache:B =C/b• Numberofblocksinaset:N• Numberofsets:S =B/N
OrganizationNumber of Ways
(N)Number of Sets
(S = B/N)Direct Mapped 1 B
N-Way Set Associative 1 < N < B B / N
Fully Associative B 1
CacheOrganizationRecap
Chapter8<35>
• Cacheistoosmalltoholdalldataofinterestatonce• Ifcachefull:programaccessesdataX&evictsdataY• Capacitymiss whenaccessYagain• HowtochooseYtominimizechanceofneedingitagain?• Leastrecentlyused(LRU)replacement:theleastrecently
usedblockinasetevicted
CapacityMisses
Chapter8<36>
• Compulsory: firsttimedataaccessed• Capacity: cachetoosmalltoholdalldataofinterest
• Conflict: dataofinterestmapstosamelocationincache
Misspenalty: timeittakestoretrieveablockfromlowerlevelofhierarchy
TypesofMisses
Chapter8<37>
DataTagV0
DataTagV0
0
0
0
0
U
0 0
00
00
Way 1 Way 0
Set 3 (11)Set 2 (10)Set 1 (01)Set 0 (00)
# MIPS assembly
lw $t0, 0x04($0)lw $t1, 0x24($0)lw $t2, 0x54($0)
LRUReplacement
Chapter8<38>
DataTagV0
DataTagV0
0
0
0
0
U
mem[0x00...04]1 00...000mem[0x00...24] 100...010
00
00
DataTagV0
DataTagV0
0
0
0
0
U
mem[0x00...54]1 00...101mem[0x00...24] 100...010
00
01
(a)
(b)
Way 1 Way 0
Way 1 Way 0
Set 3 (11)Set 2 (10)Set 1 (01)Set 0 (00)
Set 3 (11)Set 2 (10)Set 1 (01)Set 0 (00)
# MIPS assembly
lw $t0, 0x04($0)lw $t1, 0x24($0)lw $t2, 0x54($0)
LRUReplacement
Chapter8<39>
• Whatdataisheldinthecache?– Recentlyuseddata(temporallocality)– Nearbydata(spatiallocality)
• Howisdatafound?– Setisdeterminedbyaddressofdata– Wordwithinblockalsodeterminedbyaddress– Inassociativecaches,datacouldbeinoneofseveralways
• Whatdataisreplaced?– Least-recentlyusedwayintheset
CacheSummary
Chapter8<40>
• Bigger caches reduce capacity misses• Greater associativity reduces conflict misses
Adapted from Patterson & Hennessy, Computer Architecture: A Quantitative Approach, 2011
MissRateTrends
Chapter8<41>
• Bigger blocks reduce compulsory misses• Bigger blocks increase conflict misses
MissRateTrends
Chapter8<42>
• Largercacheshavelowermissrates,longeraccesstimes
• Expandmemoryhierarchytomultiplelevelsofcaches
• Level1:smallandfast(e.g.16KB,1cycle)• Level2:largerandslower(e.g.256KB,2-6cycles)
• MostmodernPCshaveL1,L2,andL3cache
MultilevelCaches
Chapter8<43>
IntelPentiumIIIDie
Chapter8<44>
• Givestheillusionofbiggermemory• Mainmemory(DRAM)actsascacheforharddisk
VirtualMemory
Chapter8<45>
• Physical Memory: DRAM (Main Memory)• Virtual Memory: Hard drive
– Slow, Large, Cheap
MemoryHierarchy
Technology Price / GB AccessTime (ns)
Bandwidth(GB/s)
Cache
Main Memory
Virtual Memory
Capacity
Spee
d
SRAM $10,000 1
DRAM $10 10 - 50
SSD $1 100,000
25+
10
0.5
0.1HDD $0.1 10,000,000
Chapter8<46>
Read/WriteHead
MagneticDisks
Takes milliseconds to seek correct location on disk
HardDisk
Chapter8<47>
• Virtualaddresses– Programsusevirtualaddresses– Entirevirtualaddressspacestoredonaharddrive– SubsetofvirtualaddressdatainDRAM– CPUtranslatesvirtualaddressesintophysicaladdresses
(DRAMaddresses)– DatanotinDRAMfetchedfromharddrive
• MemoryProtection– Eachprogramhasownvirtualtophysicalmapping– Twoprogramscanusesamevirtualaddressfordifferentdata– Programsdon’tneedtobeawareothersarerunning– Oneprogram(orvirus)can’tcorruptmemoryusedby
another
VirtualMemory
Chapter8<48>
Cache Virtual MemoryBlock Page
Block Size Page Size
Block Offset Page Offset
Miss Page Fault
Tag Virtual Page Number
Physical memory acts as cache for virtual memory
Cache/VirtualMemoryAnalogues
Chapter8<49>
• Pagesize: amountofmemorytransferredfromharddisktoDRAMatonce
• Addresstranslation: determiningphysicaladdressfromvirtualaddress
• Pagetable: lookuptableusedtotranslatevirtualaddressestophysicaladdresses
VirtualMemoryDefinitions
Chapter8<50>
Most accesses hit in physical memoryBut programs have the large capacity of virtual memory
Virtual&PhysicalAddresses
Chapter8<51>
AddressTranslation
Chapter8<52>
• System:– Virtualmemorysize:2GB=231 bytes– Physicalmemorysize:128MB=227 bytes– Pagesize:4KB=212 bytes
VirtualMemoryExample
Chapter8<53>
• System:– Virtualmemorysize:2GB=231 bytes– Physicalmemorysize:128MB=227 bytes– Pagesize:4KB=212 bytes
• Organization:– Virtualaddress:31 bits– Physicaladdress:27 bits– Pageoffset:12 bits– #Virtualpages=231/212 =219 (VPN=19bits)– #Physicalpages=227/212 =215 (PPN=15bits)
VirtualMemoryExample
Chapter8<54>
• 19-bitvirtualpagenumbers• 15-bitphysicalpagenumbers
VirtualMemoryExample
Chapter8<55>
VirtualMemoryExample
Whatisthephysicaladdressofvirtualaddress0x247C?
Chapter8<56>
VirtualMemoryExampleWhatisthephysicaladdressofvirtualaddress 0x247C?– VPN= 0x2– VPN0x2mapstoPPN 0x7FFF– 12-bitpageoffset:0x47C– Physicaladdress=0x7FFF47C
Chapter8<57>
• Pagetable– Entryforeachvirtualpage– Entryfields:• Validbit: 1ifpageinphysicalmemory• Physicalpagenumber: wherethepageislocated
Howtoperformtranslation?
Chapter8<58>
001 0x00001 0x7FFE00
001 0x0001001 0x7FFF00
V
VirtualAddress 0x00002 47C
Hit
PhysicalPage Number
1219
15 12
VirtualPage Number
Page
Tab
le
PageOffset
PhysicalAddress 0x7FFF 47C
VPN is index into page table
PageTableExample
Chapter8<59>
001 0x00001 0x7FFE00
001 0x0001001 0x7FFF00
VPhysical
Page Number
Page
Tab
le
What is the physical address of virtual address 0x5F20?
PageTableExample1
Chapter8<60>
001 0x00001 0x7FFE00
001 0x0001001 0x7FFF00
V
VirtualAddress 0x00005 F20
Hit
PhysicalPage Number
1219
15 12
VirtualPage Number
Page
Tab
le
PageOffset
PhysicalAddress 0x0001 F20
What is the physical address of virtual address 0x5F20?– VPN = 5– Entry 5 in page table
VPN 5 => physical page 1
– Physical address: 0x1F20
PageTableExample1
Chapter8<61>
001 0x00001 0x7FFE00
001 0x0001001 0x7FFF00
V
VirtualAddress 0x00007 3E0
Hit
PhysicalPage Number
19
15
VirtualPage Number
Page
Tab
le
PageOffset
What is the physical address of virtual address 0x73E0?
PageTableExample2
Chapter8<62>
001 0x00001 0x7FFE00
001 0x0001001 0x7FFF00
V
VirtualAddress 0x00007 3E0
Hit
PhysicalPage Number
19
15
VirtualPage Number
Page
Tab
le
PageOffset
What is the physical address of virtual address 0x73E0?– VPN = 7– Entry 7 is invalid– Virtual page must be
paged into physical memory from disk
PageTableExample2
Chapter8<63>
• Pagetableislarge– usuallylocatedinphysicalmemory
• Load/storerequires2mainmemoryaccesses:– onefortranslation(pagetableread)– onetoaccessdata(aftertranslation)
• Cutsmemoryperformanceinhalf– Unlesswegetclever…
PageTableChallenges
Chapter8<64>
• Smallcacheofmostrecenttranslations• Reduces#ofmemoryaccessesformostloads/storesfrom2 to1
TranslationLookaside Buffer(TLB)
Chapter8<65>
• Pagetableaccesses:hightemporallocality– Largepagesize,soconsecutiveloads/storeslikelytoaccesssamepage
• TLB– Small:accessedin<1cycle– Typically16- 512entries– Fullyassociative– >99%hitratestypical– Reduces#ofmemoryaccessesformostloads/storesfrom2to1
TLB
Chapter8<66>
Hit1
V
=
01
15 15
15
=
Hit1Hit0
Hit
19 19
19
VirtualPage Number
PhysicalPage Number
Entry 1
1 0x7FFFD 0x0000 1 0x00002 0x7FFF
VirtualAddress 0x00002 47C
1219
VirtualPage Number
PageOffset
VVirtual
Page NumberPhysical
Page Number
Entry 0
12PhysicalAddress 0x7FFF 47C
TLB
Example2-EntryTLB
Chapter8<67>
• Multipleprocesses(programs)runatonce• Eachprocesshasitsownpagetable• Eachprocesscanuseentirevirtualaddressspace
• Aprocesscanonlyaccessphysicalpagesmappedinitsownpagetable
MemoryProtection
Chapter8<68>
• Virtualmemoryincreasescapacity• Asubsetofvirtualpagesinphysicalmemory• Pagetablemapsvirtualpagestophysicalpages– addresstranslation
• ATLB speedsupaddresstranslation• Differentpagetablesfordifferentprogramsprovidesmemoryprotection
VirtualMemorySummary
Chapter8<69>
• ProcessoraccessesI/Odevicesjustlikememory (likekeyboards,monitors,printers)
• EachI/Odeviceassignedoneormoreaddress
• Whenthataddressisdetected,dataread/writtentoI/Odeviceinsteadofmemory
• AportionoftheaddressspacededicatedtoI/Odevices
Memory-MappedI/O
Chapter8<70>
• AddressDecoder:– Looksataddresstodeterminewhichdevice/memorycommunicateswiththeprocessor
• I/ORegisters:– HoldvalueswrittentotheI/Odevices
• ReadData Multiplexer:– SelectsbetweenmemoryandI/Odevicesassourceofdatasenttotheprocessor
Memory-MappedI/OHardware
Chapter8<71>
Processor MemoryAddressMemWrite
WriteDataReadData
WE
CLK
TheMemoryInterface
Chapter8<72>
Processor MemoryAddressMemWrite
WriteData
ReadDataI/ODevice 1
I/ODevice 2
CLK
EN
EN
Address Decoder
WE
WEM
RD
sel1:0
WE2
WE1 CLK
000110
CLK
Memory-MappedI/OHardware
Chapter8<73>
• SupposeI/ODevice1isassignedtheaddress0xFFFFFFF4–Writethevalue42toI/ODevice1– ReadvaluefromI/ODevice1andplacein$t3
Memory-MappedI/OCode
Chapter8<74>
• Writethevalue42toI/ODevice1(0xFFFFFFF4)addi $t0, $0, 42
sw $t0, 0xFFF4($0)
Processor MemoryAddressMemWrite
WriteData
ReadDataI/ODevice 1
I/ODevice 2
CLK
EN
EN
Address Decoder
WE
WEM
RD
sel1:0
WE2
WE1 = 1
CLK
000110
CLK
Memory-MappedI/OCode
Chapter8<75>
• ReadthevaluefromI/ODevice1andplacein$t3lw $t3, 0xFFF4($0)
Processor MemoryAddressMemWrite
WriteData
ReadDataI/ODevice 1
I/ODevice 2
CLK
EN
EN
Address Decoder
WE
WEM
RD
sel1:0 = 01
WE2
WE1 CLK
000110
CLK
Memory-MappedI/OCode
Chapter8<76>
• EmbeddedI/OSystems– Toasters,LEDs,etc.
• PCI/OSystems
Input/Output (I/O)Systems
Chapter8<77>
• Examplemicrocontroller:PIC32– microcontroller– 32-bitMIPSprocessor– low-levelperipheralsinclude:• serialports• timers• A/Dconverters
EmbeddedI/OSystems
Chapter8<78>
// C Code
#include <p3xxxx.h>
int main(void) {
int switches;
TRISD = 0xFF00; // RD[7:0] outputs
// RD[11:8] inputs
while (1) {
// read & mask switches, RD[11:8]
switches = (PORTD >> 8) & 0xF;
PORTD = switches; // display on LEDs
}
}
DigitalI/O
Chapter8<79>
• Exampleserialprotocols– SPI: SerialPeripheralInterface– UART: UniversalAsynchronousReceiver/Transmitter
– Also:I2C,USB,Ethernet,etc.
SerialI/O
Chapter8<80>
SPI:SerialPeripheralInterface• MasterinitiatescommunicationtoslavebysendingpulsesonSCK
• MastersendsSDO(SerialDataOut)toslave,msb first• Slavemaysenddata(SDI)tomaster,msb first
Chapter8<81>
UART:UniversalAsynchronousRx/Tx
• Configuration:– startbit(0),7-8databits,paritybit(optional),1+stopbits(1)– datarate:300,1200,2400,9600,…115200baud
• LineidlesHIGH(1)• Commonconfiguration:
– 8databits,noparity,1stopbit,9600baud
Chapter8<82>
// Create specified ms/us of delay using built-in timer#include <P32xxxx.h>
void delaymicros(int micros) {if (micros > 1000) { // avoid timer overflow
delaymicros(1000); delaymicros(micros-1000);
} else if (micros > 6){
TMR1 = 0; // reset timer to 0 T1CONbits.ON = 1; // turn timer onPR1 = (micros-6)*20; // 20 clocks per microsecond
// Function has overhead of ~6 us IFS0bits.T1IF = 0; // clear overflow flagwhile (!IFS0bits.T1IF); // wait until overflow flag set
}}
void delaymillis(int millis) {while (millis--) delaymicros(1000); // repeatedly delay 1 ms
} // until done
Timers
Chapter8<83>
• Neededtointerfacewithoutsideworld• Analoginput: Analog-to-digital(A/D)conversion– Oftenincludedinmicrocontroller– N-bit:convertsanaloginputfromVref--Vref+ to0-2N-1
• Analogoutput:– Digital-to-analog(D/A)conversion
• Typicallyneedexternalchip(e.g.,AD558orLTC1257)• N-bit:convertsdigitalsignalfrom0-2N-1 toVref--Vref+
– Pulse-widthmodulation
AnalogI/O
Chapter8<84>
Pulse-WidthModulation(PWM)
• Averagevalueproportionaltodutycycle
• Addhigh-passfilteronoutputtodeliveraveragevalue
Chapter8<85>
OtherMicrocontrollerPeripherals
• Examples– CharacterLCD– VGAmonitor– Bluetoothwireless– Motors
Chapter8<86>
PersonalComputer(PC)I/OSystems
• USB:UniversalSerialBus– USB1.0releasedin1996– standardizedcables/softwareforperipherals
• PCI/PCIe:PeripheralComponentInterconnect/PCIExpress– developedbyIntel,widespreadaround1994– 32-bitparallelbus– usedforexpansioncards(i.e.,soundcards,videocards,etc.)
• DDR:double-dataratememory
Chapter8<87>
PersonalComputer(PC)I/OSystems
• TCP/IP:TransmissionControlProtocolandInternetProtocol– physicalconnection:EthernetcableorWi-Fi
• SATA:harddriveinterface• Input/Output (sensors,actuators,microcontrollers,etc.)– DataAcquisitionSystems(DAQs)– USBLinks