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VHDL Data TypesPredefined types

bit '0' or '1' boolean FALSE or TRUE integer an integer in the range (231 1) to +(231 1)

(some implementations support a wider range) real floating-point number in the range 1.0E38 to +1.0E38 character any legal VHDL character including upper- and

lowercase letters, digits, and special characters (each printable character must be enclosed in single quotes;e.g., 'd','7','+')

time an integer with units fs, ps, ns, us, ms, sec, min, or hr

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Data Type Conversion VHDL is a strongly typed language

Signal and variable data types cannot be mixed

No automatic type conversion is performed

If signals and variables of multiple types need to be used, explicit

type conversion should be performed

Overloaded operators can be defined in libraries

Copyright Dr. Lizy John, The University of Texas at Austin

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Predefined VHDL OperatorsGrouped into seven classes: 1. Binary logical operators: and or nand nor xor xnor 2. Relational operators: = /= < >= 3. Shift operators: sll srl sla sra rol ror 4. Adding operators: + & (concatenation)5. Unary sign operators: + 6. Multiplying operators: * / mod rem 7. Miscellaneous operators: not abs **

When parentheses are not used, operators in class 7 havehighest precedence


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OperatorsClass 1 operators and the not operator can be applied to bits, booleans,

bit-vectors and boolean vectors

Result of relational (class 2) operator is a boolean (TRUE or FALSE)= and /= can be applied to almost any type

Other relational operators can be applied to numeric, enumerated andsome array types

If A=5, B=4, and C=3,(A >= B) and (B

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Shift operatorsThe shift operators can be applied to any bit_vector or boolean_vector.

If A is a bit_vector equal to "10010101":

A sll 2 is "01010100" (shift left logical, filled with '0') A srl 3 is "00010010" (shift right logical, filled with '0') A sla 3 is "10101111" (shift left arithmetic, filled with right bit)

A sra 2 is "11100101" (shift right arithmetic, filled with left bit) A rol 3 is "10101100" (rotate left) A ror 5 is "10101100" (rotate right)


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Arithmetic operatorsThe + and operators can be applied to integer or real numeric o pe rands.

The + and operators are not defined for bits or bit-vectors.That is why we had to make a full adder by specifically creating carry and

sum bits for each bit.

However, several standard libraries do provide functions for + and thatcan work on bit-vectors

If we use such a library, we can perform addition using the statementC

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Arithmetic operatorsThe & operator can be used to concatenate two vectors

"010" & '1' is "0101""ABC" & "DEF" is "ABCDEF".

The * and / operators perform multiplication and division on integer orfloating-point operands.

The rem and mod operators calculate the remainder and modulus for

integer operands.

The ** operator raises an integer or floating-point number to an integer power, and abs finds the absolute value of a numeric operand.


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Overloaded operatorsIn standard VHDL, some operations are valid only for certain data types.

For other data types, use overloading to create an overloaded

operator.

Concept of "function overloading" as in many general-purpose languages.

Two or more functions may have the same name, so long as the parameter

types are sufficiently different enough to distinguish which function isactually intended.

Overloaded functions can also be created to handle operations involvingheterogeneous data types.


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VHDL LibrariesIEEE std_logiclibrary IEEE; use IEEE.STD_LOGIC_1164.ALL;

IEEE numeric bitlibrary IEEE; use IEEE.numeric_bit.ALL;

IEEE numeric stdlibrary IEEE; use IEEE.numeric_std.ALL;

BITLIB is a custom library used in the book


These are IEEE standards

Despite its name, this isnot an IEEE standard

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Numeric bit libraryIEEE standard

To get bit vector use type unsigned. (Unsigned means anunsigned vector)

Conversion functions:TO_INTEGER(A) converts an unsigned vector A to an

integer

TO_UNSIGNED(B,N) converts an integer to an unsignedvector of length N


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Numeric bit libraryProvides overloaded operator to add integer to unsigned, butnot to add a bit to unsigned.

If A and B are unsigned, A+B+1 is allowed

Sum

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Simple Synthesis Example library IEEE;

use IEEE.numeric_bit.ALL;

entity Q1 is

port(A, B: in bit;C: out bit);

end Q1;

architecture Q1 of Q1 is begin

process (A) begin

C

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Synthesizer Output


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Simulation versus synthesis

library IEEE; use IEEE.numeric_bit.ALL;

entity Q1 is

port(A, B: in bit;C: out bit);

end Q1;

architecture Q1 of Q1 is begin

process (A) begin

C

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Synthesizer Output

Synthesizer still produces OR gateDiscrepancy with simulation

May be blessing hereMoral: Do not ignore synthesizer warnings makesure they are harmless


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Synthesis Examplelibrary IEEE; use IEEE.numeric_std.ALL; entity Q3 is

port(A,B,F, CLK: in bit; D: out bit);

end Q3;

architecture Q3 of Q3 is signal C: bit; begin

process(Clk) begin

if (Clk=1 and Clkevent) then C

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Synthesis Examplelibrary IEEE; use IEEE.numeric_bit.ALL; entity Q3 is

port(A,B,F, CLK: in bit; D: out bit);

end Q3;

architecture Q3 of Q3 is signal C: bit; begin

process(Clk)

begin if (Clk=1 and Clkevent) then C

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Hardware corresponding to VHDL code

Latches in addition to gates


When synthesizer generates latches,Check whether intentional latches or undesirable ones

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Example VHDL code that will not synthesize library IEEE; use IEEE.numeric_std.ALL;

entity nosyn is port(A,B, CLK: in bit;

D: out bit);end no-syn;

architecture no-syn of no-syn is begin

process(Clk) variable C: bit; begin

if (Clk='1' and Clk'event) then C := A and B;

end if; end process;

end no-syn;


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Example VHDL code that will not synthesize library IEEE; use IEEE.numeric_std.ALL;

entity nosyn is port(A,B, CLK: in bit;

D: out bit);end no-syn;

architecture no-syn of no-syn is begin

process(Clk) variable C: bit; begin

if (Clk='1' and Clk'event) then C := A and B;

end if; end process;

end no-syn;


This code will not synthesize because output D is never assigned

Results in warnings:Input is never used.Input is never used.Input is never used.

Output is never assigned

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2-to-1 Multiplexer

-- conditional signal assignmentstatement

F

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Conditional signal assignment

General formsignal_name

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Cascaded 2-to-1 MUXes

F

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4-to-1 Multiplexer using concurrent stmt

F = A'B'I 0 + A'B I 1 + A B'I2 + A B I 3

F

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4-to-1 Multiplexer using select

F = A'B'I 0 + A'B I 1 + A B'I2 + A B I 3

sel

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4-to-1 Multiplexer using processes

Inside process, sequential stmt needs to be used Eg: Case

case Sel is when 0 => F F F F

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Cyclic Shift Register

process (CLK)beginif CLK'event and CLK = '1'then Q1

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Register with Synchronous Clear and Load

process (CLK)beginif CLK'event and CLK = '1' then if CLR = '1' then Q

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Left Shift Register with Synchronous Clearand Load

process (CLK)begin

if CLK'event and CLK = '1' then if CLR ='1' then Q

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VHDL Code for a Simple SynchronousCounter

signal Q: unsigned(3 downto 0);-----------process (CLK)beginif CLK' event and CLK = '1' then if ClrN = '0' then Q

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74163 counter

74163 is available in TTL and CMOS.What does TTL stand for?What does CMOS stand for?


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74163 counter

Control Signals Next StateClrN LdN PT Q 3+ Q 2+ Q 1+ Q 0+

0 X X 0 0 0 0 (clear)1 0 X D 3 D2 D1 D0 (parallel load)1 1 0 Q 3 Q 2 Q 1 Q 0 (no change)1 1 1 present state + 1 (increment count)

If T = 1, the counter generates a carry (Cout) in state 15, soCout = Q 3 Q2 Q 1 Q0 T


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74163 Counter Model 1 library IEEE;2 use IEEE.numeric_bit. ALL;

5 entity c74163 is 6 port (LdN, ClrN, P, T, ClK: in bit ;7 D: in unsigned (3 downto 0);8 Cout: out bit ; Qout: out unsigned (3 downto 0) );9 end c74163;10 architecture b74163 of c74163 is

11 signal Q: unsigned (3 downto 0); -- Q is the counter register12 begin 13 Qout

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Two 74163 Counters Cascaded to Form an 8- bit Counter


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VHDL for 8-bit Counter 1 library IEEE;2 use IEEE.numeric_bit. ALL;

5 entity eight-bit-counter is 6 port (ClrN,LdN,P,T1,Clk: in bit ;7 Din1, Din2: in unsigned (3 downto 0);8 Count: out integer range 0 to 255;9 Carry2: out bit );10 end eight-bit-counter;11 architecture cascaded-counter of eight-bit-counter is 12 component c7416313 port (LdN, ClrN, P, T, Clk: in bit ;14 D: in unsigned (3 downto 0);15 Cout: out bit ; Qout: out unsigned (3 downto 0) );

16 end component ; 17 signal Carry1: bit ;18 signal Qout1, Qout2: unsigned (3 downto 0);19 begin 20 ct1: c74163 port map (LdN,ClrN,P,T1,Clk,Din1,Carry1, Qout1);21 ct2: c74163 port map (LdN,ClrN,P,Carry1,Clk,Din2,Carry2,Qout2);22 Count

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Synthesis of VHDL Code from Shift register


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Synthesis Tips

A VHDL synthesizer cannot synthesize delays.Clauses of the form " after time-expression" will

be ignored by most synthesizers, but somesynthesizers require that after clauses be removed.initial values are ignored by the synthesizer.A reset signal should be provided if the hardwaremust be set to a specific initial state.


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Synthesis Tips

If the range of an integer is not specified, the

synthesizer will assume the maximum number of bits, usually 32. Thus

signal count: integer range 0 to 7;

would result in a 3-bit counter, butsignal count: integer;

could result in a 32-bit counter.


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Unwanted latchesVHDL signals retain their current values until they are

changed.if X = '1' then B

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Different Levels of abstraction of a NANDdevice


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A block diagram with A, B, C as inputsand F=ab + bc as output


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Two implementations of F=ab + bc


F=ab+bc simply describes the functionality,whereas the 2 structures specify how F is realized.

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Block diagram of sequential machine

BCD to Excess-3 Code Converter


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Behavioral Model for Excess-3 CodeConverter

entity Code_Converter is Port ( X, CLK : in bit Z : out bit );

end Fig2_13;

architecture Behavioral of Code_Converter is signal State, Nextstate: integer := 0;

begin process (State,X) --Combinational Network begin case State is when 0 => if X='0' then Z

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Code Converter(contd) when 3 => if X='0' then Z

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Waveforms for Code Converter

wave CLK X State NextState Zforce CLK 0 0, 1 100 -repeat 200

force X 0 0, 1 350, 0 550, 1 750, 0 950, 11350run 1600


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Behavioral Model for Excess-3 ConverterUsing a Single Process

library IEEE;use IEEE.numeric_bit.ALL;

entity SM1_2 is port (X, CLK: in bit;

Z: out bit);end SM1_2;

architecture Table of SM1_2 is signal State, Nextstate: integer := 0;

begin process begin

case State is

when 0 =>if X='0' then Z

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Behavioral Model for Excess-3 ConverterUsing a Single Process (Contd)

when 2 =>if X='0' then Z

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Sequential Machine Model Using Equations -- The following state assignment was used:

-- S0-->0; S1-->4; S2-->5; S3-->7; S4-->6; S5-->3; S6-->2entity SM1_2 is

port (X,CLK: in bit;Z: out bit);

end SM1_2;architecture Equations1_4 of SM1_2 is

signal Q1,Q2,Q3: bit;begin

process (CLK)begin

if CLK='1' then -- rising edge of clockQ1

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Structural Model of Sequential Machine The following is a STRUCTURAL VHDL description of

-- the excess 3 converter

library UNISIM;use UNISIM.Vcomponents.ALL;

entity SM1_2 is

port (X,CLK: in bit;Z: out bit);

end SM1_2;


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Structural Model of Sequential Machine

architecture Structure of SM1_2 is signal A1,A2,A3,A5,A6,D3: bit:='0';signal Q1,Q2,Q3: bit:='0';signal Q1N,Q2N,Q3N, XN: bit:='1';

begin I1: Inverter port map (X,XN);G1: Nand3 port map (Q1,Q2,Q3,A1);G2: Nand3 port map (Q1,Q3N,XN,A2);G3: Nand3 port map (X,Q1N,Q2N,A3);G4: Nand3 port map (A1,A2,A3,D3);FF1: DFF port map (Q2N,CLK,Q1,Q1N);

FF2: DFF port map (Q1,CLK,Q2,Q2N);FF3: DFF port map (D3,CLK,Q3,Q3N);G5: Nand2 port map (X,Q3,A5);G6: Nand2 port map (XN,Q3N,A6);G7: Nand2 port map (A5,A6,Z);

end Structure;


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Variables and Signals

A variable declaration has the formvariable list_of_variable_names : type_name [ :=initial_value];

A signal declaration has the form

signal list_of_signal_names : type_name [ := initial_value ]; Variables are updated using a variable assignment statement ofthe formvariable_name := expression;Consider a signal assignment of the formsignal_name

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Process Using Variables andSimulation Output

entity dummy isend dummy;

architecture var of dummy is signal trigger, sum:

integer:=0;begin process variable var1: integer:=1;variable var2: integer:=2;variable var3: integer:=3;begin

wait on trigger;var1 := var2 + var3;var2 := var1;var3 := var2;sum

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entity dummy is end dummy;

architecture var of dummy issignal trigger, sum: integer:=0;

beginprocess

variable var1: integer:=1;variable var2: integer:=2;variable var3: integer:=3;begin

var1 := var2 + var3;var2 := var1;var3 := var2;sum

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architecture var of dummy issignal trigger, sum:

integer:=0;begin process (trigger) variable var1: integer:=1;variable var2: integer:=2;variable var3: integer:=3;begin

var1 := var2 + var3;var2 := var1;var3 := var2;sum

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Process Using Signals andSimulation Output


architecture sig of dummy is signal trigger, sum: integer:=0;signal sig1: integer:=1;signal sig2: integer:=2;signal sig3: integer:=3;

begin process begin

sig1

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Process Using Signals andSimulation Output


architecture sig of dummy issignal trigger, sum: integer:=0;signal sig1: integer:=1;

signal sig2: integer:=2;signal sig3: integer:=3;begin

process begin

process( trigger);sig1

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Constants A common form of constant declaration is

constant constant_name : type_name :=constant_value;

A constant delay1 of type time having the value of 5 nscan be defined as

constant delay1 : time := 5 ns;


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Arrays

To create array - declare an array type and declare an array object

Example of declaring an array type: A one-dimensional array type named SHORT_WORD:

type SHORT_WORD is array (15 downto 0) of bit;

SHORTWORD is the name of the type

Now, one can declare array objects of type SHORT_WORD as follows: signal DATA_WORD: SHORT_WORD; variable ALT_WORD: SHORT_WORD := "0101010101010101"; constant ONE_WORD: SHORT_WORD := ( others => '1');

All bits set to 1 by (others => 1)


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Arrays

The array type and array object declarations have thegeneral forms

type array_type_name is array index_range ofelement_type; signal array_name: array_type_name [ :=initial_values ];


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Matricestype matrix4x3 is array (1 to 4, 1 to 3) of integer;

variable matrixA: matrix4x3 := ((1, 2, 3), (4, 5, 6),(7, 8, 9), (10,11,12));

The variable matrixA , will be initialized to1 2 34 5 6

7 8 910 11 12matrixA(3,2) references 8


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Unconstrained array typeWhen an array type is declared, the dimensions of thearray may be left undefined. This is referred to as anunconstrained array type . For example, type intvec is array (natural range ) of integer;signal intvec5: intvec(1 to 5) := (3,2,6,8,1);

Two dimensional arraytype matrix is array (natural range , natural

range ) of integer;


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Parity Code Generator using LUT

LUT contents for a parity code generator Input (LUT Address=ABCD) Output (LUT Data=PQRST)

A B C D P Q R S T 0 0 0 0 0 0 0 0 10 0 0 1 0 0 0 1 00 0 1 0 0 0 1 0 10 0 1 1 0 0 1 1 10 1 0 0 0 1 0 0 00 1 0 1 0 1 0 1 10 1 1 0 0 1 1 0 00 1 1 1 0 1 1 1 01 0 0 0 1 0 0 0 01 0 0 1 1 0 0 1 1

1 0 1 0 1 0 1 0 11 0 1 1 1 0 1 1 01 1 0 0 1 1 0 0 11 1 0 1 1 1 0 1 01 1 1 0 1 1 1 0 01 1 1 1 1 1 1 1 1


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Parity Code GeneratorParity code generator using LUT method

library IEEE; use IEEE.numeric_bit. all ; entity parity_gen is

port (X: in unsigned(3 downto 0); Y: out unsigned(4 downto 0)); end parity_gen;

architecture Table of parity_gen istype OutTable is array(0 to 15) of bit;

signal ParityBit: bit; constant OT: OutTable :=('1','0','0','1','0','1','1','0','0','1','1','0','1','0','0','1');

begin ParityBit

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More on Array TypesPredefined unconstrained array types in VHDL include bit_vectorand string, which are defined as follows:

type bit_vector is array (natural range ) of bit; type string is array (positive range ) of character;

The characters in a string literal must be enclosed in doublequotes.constant string1: string(1 to 29) := This string is 29

characters.

A bit_vector literal may be written either as a list of bitsseparated by commas or as a string. For example,('1','0','1','1','0') and "10110" are equivalent forms. The followingdeclares a constant A that is a bit_vector with a range 0 to 5. constant A : bit_vector(0 to 5) := "101011";


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Loops in VHDL infinite loop

The general form for an infinite loop is

[loop-label:] loop sequential statements

end loop [loop-label]; An exit statement of the form

exit ; or exit when condition;may be included in the loop.

The loop will terminate when the exit statement is executed, providedthat the condition is TRUE.


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While Loop

Type of loop where loop index can be manipulated byhe programmer

The general form of a while loop is

[loop-label:] while condition loop

sequential statements end loop [loop-label];


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VHDL Functions A function executes a sequential algorithm and returns a single valueto the calling program.

function rotate_right (reg: bit_vector)return bit_vector is

begin

return reg ror 1; end rotate_right;The general form of a function declaration is

function function-name (formal-parameter-list)return return-type is [declarations]

begin sequential statements -- must include return return-value;

end function-name;The general form of a function call is

function_name (actual-parameter-list)


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Function example code without aloop

-- This function takes a 4-bit vector-- It returns a 5-bit code with even parity

function parity (A: bit_vector(3 downto 0); B: bit_vector(4downto 0))return bit_vector is

variable parity: bit;begin parity := a(0) xor a(1) xor a(2) xor a(3)

B:= A & parityreturn B;end parity;


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Add Function-- This function adds 2 4-bit vectors and a carry.--Returns 5 bit sum; Illustrates function creation and use of loop

function add4 (A,B: bit_vector(3 downto 0); carry: bit)return bit_vector is

variable cout: bit;variable cin: bit := carry;variable sum: bit_vector(4 downto 0):="00000";begin loop1: for i in 0 to 3 loop

cout := (A(i) and B(i)) or (A(i) and cin) or (B(i) and cin);

sum(i) := A(i) xor B(i) xor cin;cin := cout;end loop loop1;sum(4):= cout;return sum;end add4;


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Add Function CallThe total simulation time required to execute the add4 function is zero.

Not even delta time is required, since all the computations are doneusing variables

The function call is of the form add4( A, B, carry )

A and B may be replaced with any expressions that evaluate to bit_vectors with dimensions 3 downto 0, and carry may be replacedwith any expression that evaluates to a bit. For example, the statement

Z

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VHDL Procedures

The form of a procedure declaration is procedure procedure_name (formal-parameter-

list) is [declarations]

begin sequential statements

end procedure-name;The formal-parameter-list specifies the inputs andoutputs to the procedure and their types. Aprocedure call is a sequential or concurrentstatement of the form

procedure_name (actual-parameter-list);


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VHDL Procedures

Write a procedure Addvec ,which will add two N -bit vectors and a carry,and return an N -bit sum and a carry.

We will use a procedure call of the form Addvec ( A, B, Cin, Sum, Cout, N);

where A , B , and Sum are N -bit vectors, Cin and Cout are bits, and N is an integer.


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Function returning an arrayfunction squares(Number_arr: FourBitNumbers;

length: integer) return squareNumbers is

variable SN: squareNumbers; variable temp_integer: integer;

begin loop1: for i in 0 to length loop

temp_integer := to_integer(Number_arr(i))* to_integer(Number_arr(i));

SN(i) := to_unsigned(temp_integer,8); end loop loop1; return SN; end squares;


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Procedure to add bit-vectorsprocedure Addvec

(Add1,Add2: in bit_vector;Cin: in bit;signal Sum: out bit_vector;

signal Cout: out bit;n:in positive) isvariable C: bit;

beginC := Cin;for i in 0 to n-1 loop

Sum(i)

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Parameters for Subprogram Calls Actual Parameter

Mode Class Procedure Call Function Call

in1 constant2 expression expressionsignal signal signalvariable variable n/a

out/inout signal signal n/avariable3 variable n/a

1 default mode for functions 2 default for in mode 3 default forout/inout mode


Class, mode and type of each parameter must be specifiedClass constant, signal, variable; Mode in, out, inout ; type data type

Note: Function parameter cannot be variable; return is not via in parameter

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ASSERT and report statements

The ASSERT statement checks to see if a certain condition is true, andif not causes an error message to be displayed. One form of the assertstatement is:

assert boolean-expressionreport string-expressionseverity severity-level;

Boolean expression is the condition being checked

If condition not met, assertion violation; simulator reports it

If condition true, no message


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Severity statement

severity severity-level;

4 severity levels note, warning, error, failure

Include one of these to indicate the degree to which the violationaffects the model

Action taken for the severity level depends on the simulator

If the assert clause is omitted, then the report is always made. Thusthe statement:

report "ALL IS WELL";


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Use of ASSERT and REPORT: Check Setuptime and hold time violations of flip-flop

check: process begin

wait until (Clkevent and CLK=0);

assert (D'stable(setup_time))report ("Setup time violation")severity error;

wait for hold_time;

assert (D'stable(hold_time))report ("Hold time violation")severity error;

end process check; Copyright Dr. Lizy John, The University of Texas at Austin

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STABLE: Attribute that returns a signal

S'STABLE [(time)]* Boolean signal that istrue if S had no eventsfor the specified time

This attribute is used in the example to check setuptime and hold violation of a flip-flop.


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Test Benches

Assert and Report Statements are very useful forcreating test benches

Test Benches VHDL code to provide inputs to themodel under test, receive outputs from model andcompare with expected answer

Assert statement is meaningful only for simulation

Synthesizers often assume that assertion violation doesnot exist

Documents

Chapter 566566