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Chapter 4.Chapter 4. Post Layout Simulationy
IC CAD 실험 Analog part
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Analog circuit designg g
TR level circuit designCadence layout editor 를이용한손으
TR level circuit design
TR l l i l ti
로하는~layout, Hspice, cadence 를이용한 post layout simulation
TR level simulation
Layout
Post layout simulation
Fabrication
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Hierarchical layouty
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Hierarchical layouty
Block 1 Block 2 Block 3 Block 4
BlockBlock 3-1
Block 5Block 6Block 7
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Post layout simulationy
Differential ring VCO layout of differential ring VCO
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Post layout simulationy
Posim
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Cadence Layout editor y
Example> Inverter layout & post layout simulation
[ICCAD@train##]/user1/train##/ > mkdir cadence[ICCAD@train##]/user1/train##/ > cd cadence[ICCAD@train##]/user1/train##/ cadence> sourceic
[ICCAD@train##]/user1/train##/ cadence> icfb &
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Cadence Layout editor y
Example> Inverter layout & post layout simulation
Chapter 4 library 만든후,Tech file 등물려온후,Pre-simulation및 LVS를위Pre simulation 및 LVS 를위한 inverter schmetic제작
PMOS : 750nm/50nmNMOS : 250nm/50nm
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Cadence Layout editor y
Example> Inverter layout & post layout simulation
Inverter layout 을위한layout editor 실행
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Cadence Layout editor y
Example> Inverter layout & post layout simulation
단축키 I 를눌러서 ch3 에만들어져있는 PMOS 와NMOS layout 을불러올수있다.
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Cadence Layout editor y
Example> Inverter layout & post layout simulation
단축키 Shift+F를눌러서실제패턴을볼수있다.
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Cadence Layout editor y
Example> Inverter layout & post layout simulation
M + F3 을통해 move option 을연후, PMOS의패턴을PMOS 의패턴을upside down 으로바꿔준후, gate 를겹쳐준다준다.
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Cadence Layout editor y
Example> Inverter layout & post layout simulation
함께묶여야할 node 끼리metal 1 을통해서묶어준다.
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Cadence Layout editor y
Example> Inverter layout & post layout simulation
DRC 를수행하여, error 를 check 하고수정한다.Error 가나는이유는각자다를테니, 알아서내용을보고수정하도록한다.Inverter cell 에서수정이불가능한 error 의경우, chapter 3 의NMOS, PMOS 의 layout 을열어서수정후저장하면, chapter 4
의 가변inverter 의 NMOS, PMOS 가변하게된다.
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Cadence Layout editor y
Example> Inverter layout & post layout simulation
Label 을생성해준후, LVS 를수행하여, 제대로연결이되었는지를확인한다.
ddvdd
outin
vss
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Cadence Layout editor y
Example> Inverter layout & post layout simulation웃는얼굴나올때까지수정하라, 마찬가지로inverter cell 내에서고칠수없는 의경우수없는 error 의경우NMOS 와 PMOS cell 을열어서수정해야한다.
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Post layout simulationy
Example> Inverter layout & post layout simulationLayout editor, Calibre Run REX (기생성분의추출)
Rule file 은알아서불려온다. LVS 와사용법은거의비슷하며 input와사용법은거의비슷하며, input
layout tab 에서 export from schematic viewer, layout viewer 를 check해준다를 check 해준다.
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Post layout simulationy
Example> Inverter layout & post layout simulation
inverter.pex.netlist 기생성분이없는네트리스트inverter.pex.netlist.inv.pxi 기생성분의연결형태를정의inverter pex netlist pex 기생성분의형태를정의inverter.pex.netlist.pex 기생성분의형태를정의
Subckt이만들어졌다! (되도록이면, 이름을 inverter 에서( ,inverter_posim으로바꿔주도록한다.)
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Post layout simulationy
Example> Inverter layout & post layout simulation
각각의 pex data 들을 hspice폴더로 copy 후, 기생성분이추가된 inverter 에대한transient sweep 을시도해보자! 비교를위해서, schematic editor 를통해만들었던 inverter 또한 sp file 을추출하여, 같은환경으로 simulation 하여보자!p***** Differential Amplifier Simulation *****.include 'PMOS_VTL.inc'.include 'NMOS_VTL.inc'.include 'inverter_ch4.sp'.include 'inverter.pex.netlist'
.OPTIONS POST NODE LIST
V1 vdd vss 1V1 vdd vss 1V2 vss 0 0
vin in vss pulse(0 1 0.1n 0.1n 0.1n 100n 200n)x_inv in out vdd vss inverterx inv2 out out2 vdd vss inverterx_inv2 out out2 vdd vss inverter
x_invp in outp vss vdd inverter_posimx_invp2 outp outp2 vss vdd inverter_posim
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.tran 1p 1u
.END
Post layout simulationy
Example> Inverter layout & post layout simulation
O t t에약간의Output 에약간의차이가보이게된다.
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