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Chapter 3
Scan Architectures and Techniques
1
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Chapter 3
Scan Architectures and Techniques
Figure 3-1 Introduction to Scan-based Testing
Chip under Test with Full-Scan
- >1,000,000 gates
- >5,000,000 faults
- >10,000 flip-flops
- < 500 chip pins
* > 2,000 gates/pin
- > 1,000 sequential depth
* > 2M = 21000
- >1,000,000 gates
- >5,000,000 faults
- > no effective flip-flops
- < 500 + 10,000 chip pins
* > 95.23 gates/pin
- > no sequential depth
* > 2M = 20 = 1
A deep sequential circuit
A combinational circuit
Chip under Test without Scan
Chapter 3
Scan Architectures and Techniques
2
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
QD
QD
QD
input1input2
input3
clk
input5
output2
output1
Combinational &
Figure 3-2 An Example Non-Scan Circuit
Sequential Logic
QN
input4
input6QD
1 2 3 4
Sequential Depth of 4
Combinational Width of 6
26+4 = 1024 Vectors
Chapter 3
Scan Architectures and Techniques
3
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
input1input2
input3
input5
output2
output1
Combinational-Only Logic
Figure 3-3 Scan Effective Circuit
input4
input6
TPO2TPI4
TPI3
TPI2
TPI1
TPO4TPO3
TPO1
TPI5A no-clock, combinational-only circuit with:
6 inputs plus 5 pseudo-inputs and2 outputs plus 4 pseudo-outputs
D D
D
D Q
Q
QN
Chapter 3
Scan Architectures and Techniques
4
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-4 Flip-Flop versus Scan Flip-Flop
Regular D Flip-Flop
D Q
CLK
QN
D Q
clk
DQ
SDI
SE
CLK
QN
D Q
clk
SDO
Scannable D Flip-Flop
SDO
Chapter 3
Scan Architectures and Techniques
5
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-5 Example Set-Scan Flip-Flops
Set-Scan D Flip-Flop
DQ
CLK
QN
D Q
clk
SDI
SE
SET
DQ
SE
SDI
CLK
QN
D Q
clk
SDO
Set-Scan D Flip-Flop
SET
SDO
with Set at Higher Priority
with Scan-Shift at Higher Priority
Chapter 3
Scan Architectures and Techniques
6
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
QD
QD
QD
input1input2
input3
clk
input5
output2
output1
Combinational and
Figure 3-6 An Example Scan Circuit with a Scan Chain
Sequential Logic
QN
input4
input6QD
SDI
SE
SE
SDI
SE
SDI
SE
SDI
SE
scanin
SDO
SDO SDO
SDO scanout
1 0 1 1
4-Bit Scan Vector
Chapter 3
Scan Architectures and Techniques
7
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-7 Scan Element Operations
The scan cell provides observability and controllability of the signal path by conducting the four transfer functions of a scan element.
Operate: D to Q through port a of the input multiplexer:allows normal transparent operation of the element.
Scan Sample: D to SDO through port a of the input multiplexer:gives observability of logic that fans into the scan element.
Scan Load/Shift: SDI to SDO through the b port of the multiplexer: used to serially load/shift data into the scan chain while simultaneously unloading the last sample.
Scan Data Apply: SDI to Q through the b port of the multiplexer:allows the scan element to control the value of the output, therebycontrolling the logic driven by Q.
Scannable D Flip-Flop
DQ
SDI
SE
CLK
QN
SDO
D Q
clk
a
b
Chapter 3
Scan Architectures and Techniques
8
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-8 Example Scan Test Sequencing
DQ
SDI
SE=1
CLK
QN
SDO
D Q
clk
Scan Apply Mode (Last Shift)
DQ
SDI
CLK
QN
SDO
D Q
clk
Functional Operation Mode
DQ
SDI
SE=1
CLK
QN
SDO
D Q
clk
Scan Shift Load/Unload Mode
DQ
SDI
SE=0
CLK
QN
SDO
D Q
clk
Scan Sample Mode
While the clock is low,apply test data to SDIand Place SE = 1
From normal operation:
At the rising edge of the clock,test data will be loaded
Apply clocks for scan length
When chain is loaded, the lastshift clock will apply scan data
While the clock is low,place SE = 0
Normal circuit response will beapplied to D
The next rising edge of the clock
Return to Load/Shift mode tounload circuit response sample
NOTE: unloading is simultaneouswith loading the next test
Repeat operations until all vectorshave been applied
NOTE: the chip’s primary inputsmust be applied during the scanapply mode (after the last shift)
will sample D
SE=0
Chapter 3
Scan Architectures and Techniques
9
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-9 Example Scan Testing Timing
The First Shift Out
The Scan Sample
The Last Shift In
CLK
SE
The Output Pin Strobe
Faults Exercised Interval
SHIFTDATA
SHIFTDATA
FAULTEXERCISE
SHIFTDATA
SHIFTDATA
SAMPLEDATA
Scan Enable De-assert Scan Enable Assert
Chapter 3
Scan Architectures and Techniques
10
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-10 Safe Scan Shifting
Driven ContentionDuring Scan Shifting
D Q
CLK
Q D
CLK
Q D
CLK
Asynchronous or SynchronousSignals with Higher Priority
than Scan—or Non-Scan Elements
D Q
CLKCLR
HOLDSET
Gated Clock Nets
t_seB
D Q
CLK
D Q
CLKCLR
HOLDSET
f_seB
f_seB
Provide a Forced Mutual Exclusivity
Provide a Blocking Signal
Provide an Enable Signal
clock treedistribution
force the clock on
Chapter 3
Scan Architectures and Techniques
11
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
t_seBde-asserted
Figure 3-11 Safe Scan Vectors
The First Shift Out
The Scan Sample
The Last Shift In
CLK
SE
Faults Exercised Interval
t_seB
Driven Contentionduring the Capture Cycle
D Q
CLK
D Q
CLK
Q D
CLK
Q D
CLK
a tristate scan enable may bea separate signal that has
slightly different timing thanthe flip-flop SE
Chapter 3
Scan Architectures and Techniques
12
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-12 Partial Scan
input1input2
input3
input5
output2
output1
Combinational-Only Logic
input4
input6
TPI3
TPI2
TPI1
TPO4TPO3
TPO1
TPI5A clocked, sequential circuit with depth=1:
6 inputs plus 4 pseudo-inputs and2 outputs plus 3 pseudo-outputs
D D
D
D Q
Q
QN
Chapter 3
Scan Architectures and Techniques
13
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
One LongScan Chain
ManyVariable Length
Scan Chains
ManyBalanced
Scan Chains
One Channel
Each Vector is 1000 Bits LongSo 5 Vectors Are 5000 Bits of Tester Memory
10 Non-Balanced
Vector Data
An Example Using a Chip with 1000 Scan Bits and 5 Scan Vectors
Vector DataVector DataVector DataVector DataVector DataVector DataVector Data
10 BalancedChannels
100
Channels
100100100100100100100
100100100100100100100100
100100100100100100100100
100100100100100100100100
Each Vector Is 100 Bits Long—So 500 Bits of Tester Memory
Vector DataVector DataVector DataVector DataVector DataVector DataVector DataVector Data
Each Vector Is 180 Bits Long—So 900 Bits of Tester MemoryDifferences from Longest Chain (180) Are Full of X’s—Wasted Memory
No Wasted Memory Space
XXXXXXXX
XXX
XXXXXX
X
12080
10011090
18020
100
XXXXXXXX
XXX
XXXXXX
X
XXXXXXXX
XXX
XXXXXX
X
XXXXXXXX
XXX
XXXXXX
X
12080
10011090
18020
100
12080
10011090
18020
100
12080
10011090
18020
100
X’s on all Other Channelsnot actively used for parallel pin data
10001000 1000 1000Vector Data
XXXX
XXXX
XXXX
XXXX
100100
100100
Vector DataVector Data
100100
100100
100100
100100
100100
100100
Vector DataVector Data
Red Space Is Wasted Tester Memory
Figure 3-13 Multiple Scan Chains
Chapter 3
Scan Architectures and Techniques
14
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-14 The Borrowed Scan Interface
Pad
AnyBidir
Functional Normal Input
Parallel Scan
SEInput
Q
Borrowed DC Scan Input on Bidirectional Pin
CombinationalLogic D
SInput to Chip
to Logic
Input Scan Interface—May Resolve to Functional during Sample Interval
Output Data Path
Output Enable
Pad
SEOutput
Q
Borrowed DC Scan Output on Bidirectional Pin
D
S
Output Scan Interface—May Resolve to Functional during Sample Interval
Input Data Path Is a
CombinationalLogic Blocked during Scan Shift
with bus_se
ScanDataInput
Pin
Captures Directly fromthe Input Pin Duringthe Shift Operation
Captures through theCombinational Logic
during the Sample Operation
AnyBidirPins
a
b
Added Scan Output Mux with bus_se or scan_mode
CombinationalLogic
Functional Output Enable with bus_se or scan_mode added
ScanData
Output
CombinationalLogic
Don’t Careduring Scan Shift
Last Scan Shift Bitfrom Scan Chain
Normal Outputfrom Logic
SEInput
Q
D
S SE on InputBlocks Data
or scan_mode
SE
Chapter 3 Scan Architectures and Techniques 15
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-15 Clocking and Scan
Analog Digital 1 Digital 2
Raw VCOClock
VCO
Counters &Dividers
On-Chip Clock Generation Logic
• Scan Bypass Clocks
• Scan Testing an On-Chip Clock Source
Bypass Clocks
Chapter 3 Scan Architectures and Techniques 16
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-16 Scan-Based Design Rules
Driven Contentionduring Scan Shifting
D Q
CLK
Q D
CLK
Q D
CLK
Asynchronous or SynchronousSignals with Higher Priority
than Scan—or Non-Scan Elements
D Q
CLKCLR
HOLDSET
Gated Clock Nets
t_seB
D Q
CLK
D Q
CLKCLR
HOLDSET
f_seB
f_seB
Provide a Forced Mutual Exclusivity
Provide a Blocking Signal
Provide a Blocking Signal
Chapter 3 Scan Architectures and Techniques 17
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-17 DC Scan Insertion
Basic Netlist Scan InsertionElement Substitution
Ports, Routing & Connection of SE
Ports, Routing & Connection of SDI-SDO
ExtrasTristate “Safe Shift” Logic
Asynchronous “Safe Shift” Logic
Gated-Clock “Safe Shift” Logic
Multiple Scan Chains
Scan-Bit Re-Ordering
All Scan Chains (Clocks) Shift
Last Shift
Only One Clock DomainConducts a Sample Clock
All Non-SamplingClock DomainsInhibit Sample
Clock Pulse
Clock Considerations
Chapter 3 Scan Architectures and Techniques 18
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-18 Stuck-At Scan Diagnostics
1
0
1
1
0
0
0
1
0
0
1
1
0
1
1
0
1
0
0
1
0
1
0
0
0
1
1
1
1
0
1
1
0
0
0
1
0
0
1
1
0
1
1
0
1
0
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
0
Scan Fail Data Presented atChip Interface AutomaticallyImplicates the Cone of Logic
at One Flip-Flop
Multiple Fails under theSingle Fault Assumption
Implicate GatesCommon to BothCones of Logic
Chapter 3 Scan Architectures and Techniques 19
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-19 At-Speed Scan Goals
Basic Purpose
• Frequency Assessment
• Pin Specifications
• Delay Fault Content
Cost Drivers
• No Functional Vectors
• Fewer Overall Vectors
• Deterministic Grade
Chapter 3 Scan Architectures and Techniques 20
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-20 At-Speed Scan Testing
The Transition Capture
The Transition Launch
The Last Shift In
CLK
Transition Generation Interval
The First Shift Out
Faults Exercised Interval
SE
T_SE
Bus_SE
F_SE
Separate Scan Enables for Tristate Drivers,Clock Forcing Functions, Logic Forcing
Functions, Scan Interface Forcing Functions,and the Scan Multiplexor Control
Because the Different Elements HaveDifferent Timing Requirements
Chapter 3 Scan Architectures and Techniques 21
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-21 At-Speed Scan Architecture
Pad
AnyBidirPin
Normal Input
Parallel Scan
SEInput
Q
Borrowed Scan Input with Scan Head Register
CombinationalLogic D
S
DInput
Q
Driven ContentionDuring Scan Shifting
D Q
CLK
Q D
CLK
Q D
CLK
Asynchronous or Synchronous Signalswith Higher Priority than Scan
or Non-Scan Sequential Elements
D Q
CLK
CLR
HOLDSET
t_seB
D Q
CLK
D Q
CLK
CLR
HOLDSET
f_seB
Input to Chip
to Logic
At-Speed Assert and De-Assert
At-Speed Assert and De-Assert
At-Speed Scan Interface—Resolves to Functional During Sample Interval
Output Data Path Blocked during Scan Shift
Output Enable with bus_se
Chapter 3 Scan Architectures and Techniques 22
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-22 At-Speed Scan Interface
Pad
AnyBidir
Functional Normal Input
Parallel Scan
SEInput
Q
Borrowed AC Scan Input on Bidirectional Pin
CombinationalLogic D
SInput to Chip
to Logic
Input Scan Interface—Resolves to Functional during Sample Interval
Output Data Path
Output Enable
CombinationalLogic Blocked during Scan Shift
with at-speed bus_se
ScanDataInput
Pin
Captures Directly fromthe Input Pin Duringthe Shift Operation
Captures through theCombinational Logic
during the Sample Operation
DInput
Q
Head
Pad
SEOutput
Q
Borrowed AC Scan Output on Bidirectional Pin
D
S
Output Scan Interface—Resolves to Functional During Sample Interval
Input Data Path Is a
AnyBidirPin
a
b
Added Scan Output Mux with bus_se
CombinationalLogic
Functional Output Enable with bus_se Added
ScanData
Output
CombinationalLogic
Don’t Careduring Scan Shift
Last Scan Shift Bitfrom Scan Chain
Normal Outputfrom Logic
SEInput
Q
D
S SE on InputBlocks Data
DOutput
Q
Tails
Chapter 3 Scan Architectures and Techniques 23
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-23 Multiple Scan and Timing Domains
FastLogic
SlowLogic
Legal ATPGTransfer
Illegal ATPGTransfer
Only Fast-to-SlowLegal ATPG Transfer
AppliedSlow Clock
AppliedFast Clock
Last ScanShift Edge
Fast to SlowTransfers
Fast to SlowTransfers
Slow to FastTransfers
Fast ScannableSystem Registers
Slow ScannableSystem Registers
The Clock Domains and Logic Timingshould be crafted so that the very nextrising edge after the launch or last shift
is the legal capture edge
Clock AScan Enable A
Clock BScan Enable B
Chapter 3 Scan Architectures and Techniques 24
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-24 Clock Skew and Scan Insertion
D
SDI
Q
scannedflip-flop
D
SDI
Q D
SDI
Q
CombinationalLogic
CombinationalLogic
Cross Domain Clock Skew must be managed to less than the fastest
120 ps
165 ps
CombinationalLogic
150 ps
D
SDI
Q
scannedflip-flop
D
SDI
Q D
SDI
Q
CombinationalLogic
CombinationalLogic
Second Clock Domain—All Elements on Same Clock Tree
120 ps
165 ps
CombinationalLogic
150 ps
300ps+
First Clock Domain — All Elements on Same Clock Tree
CLK
SE
Cross DomainClock Skew
CLK
SE
flip-flop update time in the launching clock domain
If it is not, then the receiving flip-flop may receive new-newscan data before the capture clock arrives
To prevent this outcome, constrain the ATPG tool to onlysample one clock domain at a time during the sample interval
Chapter 3 Scan Architectures and Techniques 25
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-25 Scan Insertion for At-Speed Scan
Design Flow Chart
ModelSimulation
Synthesis
Timing
Place
Mask
Verification
Analysis
andRoute
andFab
SiliconTest
Scan ModeBus_SE
Tristate_SE
Scan Shift SEClock Force_SE
Scan DataSpecification
Determination
Logic Force_SEArchitectureDevelopment
SpecificationDevelopment
ConnectionInsertion
Bus_SE: Tristate_SE:
Scan Mode:
Force_SE:
Scan Enable (SE): Scan Shift
Force_SE: Clock Force States
Scan Interface Control
Fixed “Safe” Logic
Logic Forced States
Internal Tristates
Scan Chain BitRe- Ordering
Behavior
Gates
Mask
Silicon
Chapter 3 Scan Architectures and Techniques 26
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-26 Critical Paths for At-Speed Testing
In3
Static Timing Analysis Provides Path Description
Isolated Combinational LogicAll Fan-in to Endpoint Is
U35
U36
U37
U39In4
In2
In1
D QR1D QR2
Out1
A
B
A
A
B
A
B
B
of Identified Critical Path from the Q-Output of R1to the Device Output Pin—Out1
1>0
1>0
0>1
0>1
X
0
0
0
1
0
Accounted at this EndpointFanout to other Endpoints is Evaluated atThose Endpoints
U38A
B1
Period = 20ns : Output Strobe @ 15nsIncremental
DelayCumulative
DelayClk 2.2ns Skew Amb.R1.Q 0.0ns 0.0nsU35.AU35.ZU37.AU37.ZU38.AU38.ZOut1
0.1ns3.2ns0.2ns2.2ns0.1ns
2.1ns2.2ns5.4ns5.6ns7.8ns7.9ns
Dly=10.1 Slk=4.9ns
2.1ns
Path ElementDescription
Timing Analysis Report
Chapter 3 Scan Architectures and Techniques 27
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-27 Logic BIST
Chip with Full-Scan
LFSR - PRPG: pseudo-random pattern generation
D Q D Q D Q
CLK
LFSR - MISR: multiple input signature register
D Q
CLK
and X-Management
D Q D Q
1 1 1Seed
X3 X2 X1 X0
Polynomial: X3 + X +1 = X3 + X1 + X0 = 23 + 21 + 20 = 11
111011001100010101110111
Chapter 3 Scan Architectures and Techniques 28
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 3-28 Scan Test Fundamentals Summary
Direct Observability of Internal NodesDirect Controllability of Internal NodesEnables Combinational ATPG
Scan Testing Methodology
More Efficient VectorsHigher Potential Fault CoverageDeterministic Quality MetricEfficient Diagnostic Capability
Advantages
ConcernsSafe ShiftingSafe SamplingPower ConsumptionClock SkewDesign Rule Impact on Budgets
AC and DC Compliance