Chapter 2: Technology Know-How: From Silicon to DevicesChapter 2: Technology Know-How: From Silicon to Devices Scheible, ls of ign r ic its 2.1 Fundamentals of IC Fabrication 2020

Chapter 2: Technology Know-How: From Silicon to Devices

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2.1 Fundamentals of IC Fabrication

2.2 Base Material Silicon

2.3 Photolithography

2.4 Imaging Errors

2.5 Applying and Structuring Oxide Layers

2.6 Doping

2.7 Growing and Structuring Silicon Layers

2.8 Metallization

2.9 CMOS Standard Process


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2.1 Fundamentals of IC Fabrication2.2 Base Material Silicon2.3 Photolithography

2.3.1 Fundamentals2.3.2 Photoresist2.3.3 Photomasks and Exposure2.3.4 Alignment and Alignment Masks2.3.5 Reference to Physical Design

2.4 Imaging Errors2.4.1 Overlay Errors2.4.2 Edge Shifts2.4.3 Diffraction Effects2.4.4 Reference to Physical Design

2.5 Applying and Structuring Oxide Layers2.5.1 Thermal Oxidation2.5.2 Oxidation by Deposition2.5.3 Oxide Structuring by Etching2.5.4 Local Oxidation2.5.5 Reference to Physical Design

2.6 Doping2.6.1 Background2.6.2 Diffusion2.6.3 Ion Implantation2.6.4 Reference to Physical Design


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2.7 Growing and Structuring Silicon Layers2.7.1 Homoepitaxy2.7.2 Heteroepitaxy and Polysilicon2.7.3 Reference to Physical Design

2.8 Metallization2.8.1 Fundamentals2.8.2 Metallization Structures Without Planarization 2.8.3 Metallization Structures with Planarization2.8.4 Reference to Physical Design

2.9 CMOS Standard Process2.9.1 Fundamentals: The Field-Effect Transistor2.9.2 Process Options2.9.3 FEOL: Creating Devices2.9.4 BEOL: Connecting Devices


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Monocrystal

(b)

Molden mass

Seed crystal

Monocrystal

Poly silicon

Seed crystal

Heater

(a)

Molden mass

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Positive photoresist

Adjust photomask Exposure Development

(a) (b) (c)

Developed photoresist

(d)

Negative photoresist

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Reflector

Light source

Condensor lens(es)

Reticle(photomask)

Projection lens(es)

Wafer

Positioner table

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Die Die Die

Die Die Die

Scribe lines

Rightalignmentmark

Leftalignment

markAlignment mark

Photomaskopening

Structure on wafer(from previous layer)

Reticle

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layer 1

(a) (b) (d)

layer 2

(c)

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Metal1

Contact

Layout structure

Design ruleMinimal enclosureMetal1 vs. Contact

Structure on wafer

(real)

Layers

(desired)

Overlayerror

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Structure in layout Structure on photomask

(copy of layout)

Structure on wafer

Structure on photomask

with pre-sizing

(a)

(b)

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No OPC Rule-based OPC Model-based OPC

Structure in photoresist

OPC photomasklayout

Punchedserif

Desired layout structure

Hammer heads

LES

Decreasing ratio structure size / wavelength

Diffraction effects:Line-end shortening (LES)Corner rounding (CR)

CR

LES

CR

Optical proximitycorrection (OPC)

Addedserif

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Silicon

After thermal oxidationBefore thermal oxidation

56%

44%

Silicon

Oxide

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Silicon

(a) (b) Oxidation (c) Deposit photoresist

(d) Adjust photomask (e) Exposure (f) Development

(g) Oxide etch (h) Remove photoresist (i)

Structured oxide

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Wet etching Dry etching (RIE)

Silicon

Oxide

Photo resist

Undercut

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(a)

Oxide steps

(b) (c)

Remaining stepson silicon surface

Level 1 Level 2

SiO2

Si x x

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Silicon

Pad oxide

Nitride Nitride mask etch Oxidation Bird‘s beak

Step

(a) (b) (c) (d)

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Nitride mask etchingSilicon etching

Local oxidation

Silicon

Pad oxide

Nitride

(a) (b) (c) (d)

Nitride removalOxide clear etching

Removal 56%

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n-type p-type semiconductor

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Si

Layout structure

Diffusing dopant atoms

Outdiffusion

Dopant atoms

Dopant concentrationC/C(0)

t1 10 t1 100 t1

1 2 3 Depth z [μm]

100

10-1

10-2

10-3

10-4

SiO2

0

z

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Lorentz force

Mass separator (magnetic field)

Linear accelerator

Ion source

Capacitor plates(electrical field)

Aperture

Required ion beam

Wafer

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High energy dopant ions

Dopant concentrationC/C(zimp)

t1 10 t1 100 t1

1 2 3 z [μm]

100

10-1

10-2

10-3

10-4

Si

Depth of implant zimp

(a)

Si

Small outdiffusion

z

(b)

Scatteringoxide

Fotoresist

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Dopant concentration (logarithmic)

Depth

p-n

p

n+

Vertical p-n junctions

p-n

pn+

Vertical p-n junctions

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(a1) n-implant

(b) Before epitaxial growth

Developedfotoresist

(a2) n-diffusion

Scatter oxide

Silicon

Structuredoxide

Silicon

(c) After epitaxial growth

n-epi

p-silicon

Abrupt p-n junctionRemove resistRemove oxideHealing

Remove oxide

n-

n+n-buried layerp

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(a)

Photoresist

(b) (c)

Si substrate or epi

(n or p)

Oxide (SiO2) Silicon structured byshallow trench isolation (STI)

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(a)

Si epi(n or p)

Photoresist

(b) (c) (d)

Oxide (SiO2)Polysilicon Silicon structured by

deep trench isolation (DTI)

Si substrate(n or p)

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Silicon

(a) Poly deposition

SiliconSilicon

(b) Photoresist (c) Exposure

(d) Development (e) Poly etch (f) Remove photoresist

Silicon

Silicon Silicon Silicon

Oxide

Poly

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Contact

Metal-1Via-1Metal-2Via-2Metal-3Via-3Metal-4

Poly

Silicon substrate

1st routing layer pair

2nd routing layer pair

3rd routing layer pair

4th routing layer pair

….

….

….

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Step 1: 1st interlevel oxide deposit

Step 3: metal 1 deposit

Step 2: contact hole etch

Step 4: metal 1 etch

Step 5: 2nd interlevel oxide deposit

Step 7: metal 2 deposit

Step 6: via 1 hole etch

Step 8: metal 2 etch

Weakness

Contact hole Via holeForbiddenvia hole

Too weak

Initial state after FEOL

FOX (here LOCOS)Silicon

Poly

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Remove photoresist,deposit barrier

Trench etch Deposit copper

Oxide

Silicon

Structured photoresist

CMP, deposit nitride

Nitride Copper

(a) (b) (c) (d)

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Step1: First oxide, step 2: Nitride

Step3: Nitride etch (via1 mask)

Step 4: Second oxide

Step 5: Oxide etch (metal-1 mask)

Step 7: Deposit barrier + copper seed

Step 8: Deposit copper

Step 9: CMP, step 10: Nitride

Metal-1 Contacts

Initial state after metal-1 of BEOL

Silicon

FOX (here STI)

Poly

Interlevel oxide (ILO)

Step 6: Nitride etch

Trenches and via holes

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DB GS

n-channel

0 V

VGB = Vth VDS

n+ n+p+

p

Field

Gate oxide (GOX)

Backgate / bulk

Poly gate

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- -

+ + + + + ++ + + + + +

+

Holes are majority carrier

Electronsare majority carrier

Electrons are minoritycarrier

+ + + ++

Holes areminoritycarrier

-108

106

104

102

n-

n

n+

1012

1016

1014

1018

108

1010

106

104

102

p-

p

p+

1012

1016

1014

1018

1010

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Single-well process Twin-well process Triple-well process

NMOS PMOS NMOS PMOS NMOS PMOS

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Oxide

(c) n-implant

(b) Nitride etch

PhotoresistNitride

p--substrate

Pad oxide

(a) Photolithgraphy (mask Nwell) (d) Diffusion incl. LOCOS

(e) p-implant (self-aligned)

(f) Diffusion, CMP

Bird‘s beak

p-well n-well

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(a) Photolithography (mask STI)

(b) Shallow trench etch

(c) Shallow trench oxidation, CMP

STI

(d) Gate oxide, polysilicon deposit

(e) Photolithography (mask Poly)

(f) Polysilicon etch

STI STIPoly gates

Polysilicon

Trenches

Gate oxidePhotoresist

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(a) Photolithography (mask NSD)

(b) n-implant (LDD)

(c) Photolithography (mask PSD)

(d) p-implant (LDD)

Self alignment Self alignment

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(a) Oxidation by CVD (b) Oxide etch

Spacers

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(a) Photolithography (mask NSD) (c) Photolithography (mask PSD)

(b) n+-implant (d) p+-implant

(e) Diffusion

NMOS-FET PMOS-FET

Self alignment Self alignment

LDD LDD

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Documents

Chapter 2: Technology Know-How: From Silicon to DevicesChapter 2: Technology Know-How: From Silicon to Devices Scheible, ls of ign r ic its 2.1 Fundamentals of IC Fabrication 2020