Chapter 2: Static Timing Analysis

Chapter 2: Static Timing Analysis

Massoud PedramDept. of EE

University of Southern California

M. Pedram

Background Gate Delay Analysis

K-factor Approximation Effective Capacitance Approach

Wire-Load Delay Analysis Interconnect Modeling Transmission Line Equations Elmore Delay S2P Approach

Appendices

Outline

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Does the design meet a given timing requirement?!!

How fast can I run the design?!!!

Motivation

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What’s the problem? Delays on signals due to wires no longer

negligible Modern designs must meet tight timing

specifications Layout tools must guarantee these timing

specifications How can we address the problem during

physical design? By ignoring it, mostly Implicitly, qualitatively

We try to make layout area small and wires short We rely on cell libraries with many cell drivers strengths We employ accurate, yet efficient, timing analysis tools We develop timing-aware design optimization

methodologies, flows and tools

The Problem and Its “Solution”

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Mid 80 Scenario Most of the input to

output delay of the logic is due to gate delay

Mid 90 Scenario Half of input to output

delay of the logic is due to wire delay

Today’s Scenario Most of input to output

delay of the logic is due to wire delay

20% delay

80% delay

50% delay

50% delay

85% delay

15% delay

Background

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With higher chip speeds and densities on the horizon, getting quick and accurate feedback on signal delays during design has become a critical issue. With ever-increasing time-to-market pressures, designers must be able to:

Analyze timing early and often throughout the design process by using high-fidelity and efficient timing analysis tools

Decrease the number of independent optimization steps in the design cycle (unification-based approach)

Eliminate the time spent debugging erroneous timing results

Have the capability to make design changes that can be re-timed quickly without having to entirely re-run static timing analysis from scratch in a separate environment

Ensure that all intermediate timing analysis results correlate well with the final timing results

Verify the delay and timing of the finished product

Guidelines to Meet Timing

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The circuit delay in VLSI circuits consists of two components:

The 50% propagation delay of the driving gates (known as the gate delay)

The delay of electrical signals through the wires (known as the interconnect delay)

A B C

Inv 1 Inv 2

BCABAC DelayDelayDelay

Input-to-Output Propagation Delay

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The gate delay and the output transition time are functions of both input slew and the output load

Gate/Cell

T in

Cload

( , )in loadGate Delay f T C

( , )in loadOutput Transition Time f T C

Gate Delay and Output Transition Time

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General Model of a Cell

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in

Wp

Wn

CM

out

in

Wp

Wn

CM

out

Cdiff Cload

Vin Vout

Cout

Definitions

VinVout

Time

Gate Delay

90%

10%

Output Transition Time

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Output Response for Different Loads

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Output transition time as a function of input transition time and output load

Output Transition Time

2 2.4 2.8 3.2 3.6 4

x 10-10

5

6

7

8

9

10

11 x 10-11

Size=69 Cout=23fFSize=48 Cout=15fFSize=90 Cout=18fF

Input Transition Time (s)

Ou

tpu

t T

ran

siti

on t

ime

(s)

10-10

1 1.4 1.8 2.2 2.6 3

x 10-14

6

7

8

9

10

11 x 10-11

Size=60 Tin=300pSSize=81 Tin=350pSSize=45 Tin=200pS

Ou

tpu

t T

ran

siti

on t

ime

(s)

CLoad (F)10-14

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Three approaches for gate propagation delay computation are based on:

Delay look-up tables K-factor approximation Use of a Thevenin equivalent circuit composed of a voltage

source and a resistance in series with the gate load. Although the first approach is currently in wide use

especially in the ASIC design flow, the third approach promises to be more accurate when the load is not purely capacitive. This is because it directly captures the interaction between the load and the gate/cell structure. The resistance value in the Thevenin model is strongly dependent on the input slew and output load and requires output voltage fitting.

ASIC Cell Delay Model

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What is the delay when Cload is 505f F and Tin is 90pS?

Cload (fF)

Tin

(pS)

0 5 10 500 505 51050

70

90

110

310

330

115pS

Table Look-Up Method

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According to above, we can write the output transition time as a function of input transition time and output load as a polynomial functions with curve fitting. As an example, consider:

A similar equation (with different coefficients, of course, gives the gate delay

2( )1 2 3 4 5T k k C T k k C k Coutput load in load load

K-factor Approximation

2 2.4 2.8 3.2 3.6 4

x 10-10

5

6

7

8

9

10

11 x 10-11

Size=69 Cout=23fFSize=48 Cout=15fFSize=90 Cout=18fF

Input Transition Time (s)

Ou

tpu

t T

ran

siti

on t

ime

(s)

10-10

1 1.4 1.8 2.2 2.6 3

x 10-14

6

7

8

9

10

11 x 10-11

Size=60 Tin=300pSSize=81 Tin=350pSSize=45 Tin=200pS

Out

put

Tra

nsit

ion

tim

e (s

)

CLoad (F)10-14

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One Dimensional Table( 1) 1

( )2 2

( ) 1 2

2 11

2 1

1 2 2 122 1

2 1 1 2 2 1( )2 1 2 1

t C tr r

t C tr r

t C a C ar

t tr raC C

t C t Cr raC C

t t t C t Cr r r rt C Cr L LC C C C

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Two Dimensional Table

( , ) 1 2 3 4

( ) /1 4 11 3 2 1 2 1 2 1 2 2( ) /2 3 1 4 1 1 2 2 2

3 ( ) /2 1 4 1 1 2 3 24 ( ) /1 2 3 4

( )( )1 2 1 2

D C t k k C k t k C tin L in L in

D C t D C t D C t D C t WkD t D t D t D t Wk

k D C D C D C D C Wk D D D D W

W C C t t

D1

D4D3

D2

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Gate /Cell

T in

2 31 2 3( ) .....inY s A s A s A s 2 2 2 3 3

1 2 2 2( ) ( ) .....inY s C C s R C s R C s

22 232 2

1 1 233 32

AA AC A R C

A AA

Gate /Cell

Tin R

C1

C2

Using Taylor Expansion around s = 0

Second-order RC- Model

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Gate /Cell

Tin R

C1

C2

1 2( , , , )inGate Delay f T C R C

This equation requires creation of a four-dimensional table to achieve high accuracy

This is however costly in terms of memory space and computational requirements

Second-order RC- Model (Cont’d)

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The “Effective Capacitance” approach attempts to find a single capacitance value that can be replaced instead of the RC- load such that both circuits behave similarly during transition

Gate /Cell

Tin R

C1

C2

Gate /Cell

T in

Ceff

Effective Capacitance Approach

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Output Response for Effective Capacitance

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Effective Capacitance (Cont’d)

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0<k<1

Gate /Cell

Tin R

C1

C2

21 kCCCeff

Because of the shielding effect of the interconnect resistance , the driver will only “see” a portion of the far-end capacitance C2

R

k = 1

R

∞k = 0

Gate /Cell

T in

Ceff

Effective Capacitance (Cont’d)

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Effective Capacitance for Different Resistive Shielding

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Assumption: If two circuits have the same loads and output transition times, then their effective capacitances are the same. In other words, the effective capacitance is only a function of the output transition time and the load

GATE 2

Tin2 R

C1

C2

GATE 1

Tin1 R

C1

C2

Macy’s Approach

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0 1 21

1

CC

C

2CR

Tout

21 CC

Ceff

Normalized Effective Capacitance Function

Macy’s Approach (Cont’d)

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1. Compute from C1 and C2

2. Choose an initial value for Ceff

3. Compute Tout for the given Ceff and Tin

4. Compute

5. Compute from and

6. Find new Ceff

7. Go to step 3 until Ceff converges

GATE 1

Tin1 R

C1

C2

21

1

CC

C

2CR

Tout

21 CC

Ceff

Macy’s Iterative Solution

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C2

R

C1

RdTR

M

Gate /Cell

Tin R

C1

C2

' '

( ) 0

( )

( )

tddR

RM

tddR R

R

Vt B Ae Cosh t t T

TV t

VT Ae Cosh t T t

T

USC’s Approach

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TR

Rd

Ceff

N

Gate /Cell

T in

Ceff

) 0

( )

(1 )

d eff

R

d eff d eff

t

R Cddd eff d eff R

R

N T t

R C R CddR d eff R

R

Vt R C R C e t T

T

V t

VT R C e e T t

T

USC’s Approach (Cont’d)

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1 2

( )1

( )( )

(1 )d eff

t

eff t

R C

Cosh te

CoshC C C

e

See expressions for , , and in the paper by Abbaspour/Pedram

This is a non-Linear algebraic equation, which must be solved by iteration

A good initial value for Ceff can speed up the procedure to find the answer

Eff_Cap Equation

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Initial Guess

21 CRR

RCC

d

deff

(b) driver size=100l,TR= 200pS

(C1=15fF, C2=20fF)

0 20 40 60 8015

20

25

30

35

0 20 40 60 8015

20

25

30

35

(a) driver size=500l,TR=100pS C

eff (f

F)

Rp (K) Rp (K)

Cef

f (f

F)

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1. Start with the initial guess for Ceff

2. Obtain t0-50% based on values of Ceff and TR

3. Obtain Rd based on values of Ceff and TR

4. Compute a new value of Ceff from the Eff_Cap equation

5. Record the previous value of t0-50% . Find current t0-50% based on the new Ceff and given TR

6. Compare the previous and current values of t0-50% from step 5

7. If not within acceptable tolerance, then return to step 3 until t0-50% converges

8. Report t50% propagation delay and t0-80% from the table

USC’s Iterative Solution

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So far, we have only discussed the gate delay How do we calculate the interconnect delay? Precise delay calculation needs transmission line

analysis

Interconnect Analysis

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Transmission Line Equations

Drop across R and L is :

Current through C and G is :

The resulting equation is as follows:

V IRI L

x t

I VGV C

x t

2 2( )

2 2V V V

RGV RC LG LCtx t

Infinitesimal Model of a Transmission Line

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Lumped Model of a Transmission Line

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Impedance of an Infinite Line

An infinite length of RLCG transmission line has an impedance:

Driving a line terminated in Z0 is the same as driving Z0

In general, Z0 is complex and frequency dependent.

For LC lines, Z0 is real and independent of frequency and is given by:

0R Ls

ZG Cs

0L

ZC

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Simple Transmission Line Models

Generally speaking, G=0 Ideal Lumped Wires (purely C, R or L)

Pure C section: most short signal lines and short sections of low-impedance transmission lines

Pure R section: on-chip power supply wires Pure L section: off-chip power supply wires and short

sections of high-impedance transmission lines RC Transmission Lines

Long on-chip wires; L=0; Diffusion Equation Lossless LC Transmission Lines

Most off-chip wires; R=0; Wave equation Reflections and the Telegrapher’s equation

Lossy RLC Transmission Lines Wave attenuation and DC attenuation Combined traveling wave and diffusive response The skin effect

R

C

R L

C

L

C

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Low-Frequency RC Line, 24AWG Twisted Pair

R=0.08 /m, C=40 pF/m and L=400 nH/m f0=R/(2L)=33Khz Below f0, Line is RC with

Above f0, Line is LC with

1290.08 400 10 2

0 1240 10 2

fjZ

fj

1000Z

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Lossy RC Transmission Lines

Most real lines dissipates power. The loss is due to resistance of the conductor and conductance of the insulators.

RC lines are an extreme case: R >> L Propagation is governed by the diffusion

equation: Typical of on-chip wires:

R=150k/m L=600nH/m f=40Ghz

2

2V V

RCtx

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Step Response of a Lossy RC Line

Signal is dispersed as it propagates down the line:

R increases with length, d C increases with length, d Delay and rise time are

proportional to RC and then increases with d2

In many cases the degradation of the rise time caused by the diffusive nature of RC lines as much a problem as the delay

20.4

2

t d RCd

t d RCr

Delay:

Rise Time:

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Lossless LC lines If R and G are negligible, then line is lossless

(i.e., no heat generation and the line is governed by the wave equation)

Waves propagate in both directions without any loss

Line is described by its impedance and velocity2 2

2 2

max( , ) 0, ( , ) ,max

11 22( ) 0

V VLC

x t

x xxV x t V t V x t V x tf rv v

Lv LC Z

C

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Reflections and the Telegrapher’s Equation in a Lossless LC Line

When a traveling wave reaches the end of the line with impedance Z0 terminated in an impedance ZT, then it is reflected

Telegrapher’s equation relates the magnitude and phase of the incident wave to those of the reflected wave as follows:

Kr = Ir/Ii = Vr/Vi = (ZT-Z0)/(ZT+Z0) Some common terminations

Open-circuit Short-circuit Matched

Source termination and multiple reflections

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Lossy RLC Transmission Lines LC lines with resistance in

conductors and conductance in dielectrics:

Combined traveling wave and diffusive response

The amplitude of the traveling wave is reduced exponentially with distance along the line

For a line with matched termination, the steady-state response is attenuated by a DC amount proportional to the inverse of the length of the line

Disperses the signal Fast rise due to traveling wave

behavior Slow tail due to diffusive relaxation

Resistance (due to the skin effect) and conductance (due to dielectric absorption) are in fact dependent on the frequency. Both effects result in increased attenuation at higher frequencies

exp( )d

J

Skin effect: High frequency current density falls off exponentially within depth into conductor

1/ 2( )f

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Step Response of 1 meter of 8mil Stripguide

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Lumped RC Model for On-chip Wires

Rv1(t)vs(t)

C

Impulse response and Step Response of a lumped RC circuit

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RC Model (cont’d)

Transfer Function of RC Networks

1( ) 1/ 11( )

1( ) 1/ 1 1

2 2( ) 1 ( ) ( ) ...0 2 ...0 1 2

1 1 11 2( ) 1 ...2( ) ( )

v s sC sRCH sv s R sC sRCs

sRC

H s RC s RC sfor sm m s m s

for s H s s ssRC RC RC

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RC Model: Important Notes

Impulse response: 1 1 1 1 2( ) (1 ....)22!( )

t

RCh t e t tRC RC RC RC

0 0

0 0

0

( ) ( ) ( ) 1

0 0

( ) ( )( ) ( )

0 0

( ) ( 1) ( )

0

s s

s s

s

sth t dt h t e dt H s

d dsth t tdt h t e dt H s RCds ds

kdk kh t t dt H s mkkds

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A B C

Inv 1 Inv 2

( ) 1

t

RCV t e

R

C

V(t)1v

What is the time constant for more complex circuits?

Time Constant=RC

Elmore Delay

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,T R Cdelay i downstream ii on path

Tdelay,4=R1(C1+C2+C3+C4+C5)+R2(C2+C4+C5)+R4C4

Elmore Delay (Cont’d)

Resistance-oriented Formula:

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The Elmore delay is negative of the first moment of the impulse response, -m1

If the impulse response is symmetric, then –m1 = tmedian

However, in RC network, tmedian < -m1

Thus, the Elmore delay gives an upper bound of the delay

Elmore Delay (Cont’d)

(1) ( ) ( ) 0.50 0

mediantm th t dt and h t dt

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Elmore Delay Approximation

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3-pole Reduced Order Approximation

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The Elmore delay is the metric of choice for performance-driven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated

However, for deep submicron technologies (DSM), the accuracy of the Elmore delay is insufficient

Stable 2-Pole RC delay calculation (S2P)

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Let Y(s) be an driving point admittance function of a general RC circuit. Consider its representation in terms poles and residues:

where q is the exact order of the circuit

Moments of Y(s) can be written as:

( ) 0

1

qknY s k

s pnn

01

1

qknm ii ipnn

Driving Point Admittance

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Yi

i Ri

Li

Ci

Yj

j

1, 1,1 2

2, , , , , 1, 1, 2,

1 1

m m Ci j ik k

m m R m m L m m R C m L C m kk i k j i l i k l j i l i k l j i i k i i i k i

l l

2 3( ) ....1, 2, 3,Y s sm s m s mi i i i

Recursive Calculation of Moments of Y(s)

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The first moment of the impulse response, H(s), is known as Elmore delay which is shown before

The computation of the additional moments beyond the first moment comes with very little incremental cost. This process can be implemented using a vectorized path tracing algorithm like the one described in the paper “RICE:Rapid Interconnect circuit evaluation using AWE”

Moments of Impulse Response

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Moments of H(s)

Moments of H(s) are coefficients of the Taylor’s Expansion of H(s) about s=0

0

1( ) ( )! s

jdjm H sjj ds

0 0 0

2 31 12 3( ) ( ) ( ) ( ) ...0 2 32! 3!s s s

d d dH s H s H s s H s s H s

ds ds ds

(0) (1) 2 (2) 3 (3) ...m sm s m s m

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S2P Algorithm1. Compute m1, m2, m3 and m4 for Y(s)2. Find the two poles at the driving point admittance as

follows:

3. To match the voltage moments at the response nodes, solve the Vandermonde equations to get the following result:

4. The S2P approximation is then expressed as:

Notice that m0* and m1*

are the moments of H(s). m0* is the Elmore delay.

S2P Algorithm

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Appendix I: Characteristics of Moments

1 1 ( 1)2 2 3 3( ) ( ) ( ) 1 ... ( )2! 3! !0 0 0

0

jst jH s h t e dt h t st s t s t dt s t h t dt

jj

(0) ( )0

(1) ( )0

1(2) 2 ( )2! 0

1(3) 3 ( )3! 0

.........

( 1)( ) ( )! 0

m h t dt

m th t dt

m t h t dt

m t h t dt

jj jm t h t dt

j

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Appendix II: Pade Approximation

Pade approximation of the transfer function H(s) is a rational function as shown below:

2( ) ...0 1 2 1( ) ( ) ( ), 2( ) 1 ...1 2

1( ) ( )(0) (1) 2 (2) ( ).....( ) ( )

2 ...0 1 22 (0) (1) 2 (2)(1 ... ) .....1 2

pP s a sa s a s ap p p qH s H s O sp q qQ sq sb s b s bq

p qP s s r sp p q p qm sm s m s mQ s Q sq q

pa sa s a s apqsb s b s b m sm s mq

( ) 1 ( )p q p q p qs m s r s

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Pade Approximation (Cont’d)

(0) (1) (2) ( 1) ( )...(1) (2) (3) ( ) ( 1)... 1... ... ... ... ... ...

( 2) ( 1) ( ) (2 3) (2 2)... 1( 1) ( ) ( 1) (2 2) (2 1)0...

(0)0

1

q qm m m m mbqq qbm m m m mq

q q q q qbm m m m mbq q q q qm m m m m

a m

a

(1) (0)

1(2) (1) (0)

2 1 2...

min( , )( )( )

1

m m b

a m m b m b

p qp jap m p m b j

i

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Appendix III: RLC Model

Underdamped

R L

C

vs(t) v1(t)1

,2

2( )1 2 2( 2 )

R

L LC

v s vdds s s

Overdamped

Critically damped

Step Response

2 2 2 21 1 1 1

( ) 11 2 2 2 22 2 2 2

t tv t v e edd

2, / 4or L R C

2, / 4or L R C

( ) 1 ( 1)1tv t v t edd

2 2 2, / 4or L R C d

( ) ( )( ) 11 2 2d d

j jj t j td dv t v e edd j jd d

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Voltage across the Capacitance

Inductance changes the behavior of the voltage from underdamped to overdamped

Vc(

t)

Time(s)

L=0.0nH

L=1.0nH

L=2.0nH

R L

CvL(t)

vC(t)

vR(t)

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Voltage across the Resistance

VR(t

)

Time(s)

L=0.0nH

L=1.0nH

L=2.0nH

R L

CvL(t)

vC(t)

vR(t)

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Voltage across the Inductance

R L

CvL(t)

vC(t)

vR(t)

Time(s)

VL(

t )

L=0.0nH

L=1.0nH

L=2.0nH