Embed Size (px)
Citation preview
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Chapter 2 <1>
Digital Design and Computer Architecture, 2nd Edition
Chapter 2
David Money Harris and Sarah L. Harris
Chapter 2 <2>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Introduction• Boolean Equations• Boolean Algebra• From Logic to Gates• Multilevel Combinational Logic• X’s and Z’s, Oh My• Karnaugh Maps• Combinational Building Blocks• Timing
Chapter 2 :: Topics
Chapter 2 <3>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
A logic circuit is composed of:• Inputs• Outputs• Functional specification• Timing specification
inputs outputsfunctional spec
timing spec
Introduction
Chapter 2 <4>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Nodes– Inputs: A, B, C– Outputs: Y, Z– Internal: n1
• Circuit elements– E1, E2, E3– Each a circuit
A E1
E2
E3B
C
n1
Y
Z
Circuits
Chapter 2 <5>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Combinational Logic– Memoryless– Outputs determined by current values of inputs
• Sequential Logic– Has memory– Outputs determined by previous and current values
of inputs
inputs outputsfunctional spec
timing spec
Types of Logic Circuits
Chapter 2 <6>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Every element is combinational• Every node is either an input or connects
to exactly one output• The circuit contains no cyclic paths• Example:
Rules of Combinational Composition
Chapter 2 <7>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Functional specification of outputs in terms of inputs
• Example: S = F(A, B, Cin)
Cout = F(A, B, Cin)
AS
S = A B CinCout = AB + ACin + BCin
BCin
CL Cout
Boolean Equations
Chapter 2 <8>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Complement: variable with a bar over it A, B, C• Literal: variable or its complement A, A, B, B, C, C• Implicant: product of literals ABC, AC, BC• Minterm: product that includes all input
variables ABC, ABC, ABC• Maxterm: sum that includes all input variables (A+B+C), (A+B+C), (A+B+C)
Some Definitions
Chapter 2 <9>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Y = F(A, B) =
• All equations can be written in SOP form• Each row has a minterm• A minterm is a product (AND) of literals• Each minterm is TRUE for that row (and only that row)• Form function by ORing minterms where the output is TRUE • Thus, a sum (OR) of products (AND terms)
Sum-of-Products (SOP) Form
A B Y0 00 11 01 1
0101
minterm
A BA BA B
A B
mintermname
m0m1m2m3
Chapter 2 <10>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Sum-of-Products Form
Y = F(A, B) =
Sum-of-Products (SOP) Form• All equations can be written in SOP form• Each row has a minterm• A minterm is a product (AND) of literals• Each minterm is TRUE for that row (and only that row)• Form function by ORing minterms where the output is TRUE • Thus, a sum (OR) of products (AND terms)
A B Y0 00 11 01 1
0101
minterm
A BA BA B
A B
mintermname
m0m1m2m3
Chapter 2 <11>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Sum-of-Products Form
Y = F(A, B) = AB + AB = Σ(1, 3)
Sum-of-Products (SOP) Form• All equations can be written in SOP form• Each row has a minterm• A minterm is a product (AND) of literals• Each minterm is TRUE for that row (and only that row)• Form function by ORing minterms where the output is TRUE • Thus, a sum (OR) of products (AND terms)
A B Y0 00 11 01 1
0101
minterm
A BA BA B
A B
mintermname
m0m1m2m3
Chapter 2 <12>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Y = F(A, B) = (A + B)(A + B) = Π(0, 2)
• All Boolean equations can be written in POS form• Each row has a maxterm• A maxterm is a sum (OR) of literals• Each maxterm is FALSE for that row (and only that row)• Form function by ANDing the maxterms for which the
output is FALSE• Thus, a product (AND) of sums (OR terms)
Product-of-Sums (POS) Form
A + BA B Y
0 00 11 01 1
0101
maxterm
A + BA + BA + B
maxtermname
M0M1M2M3
Chapter 2 <13>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• You are going to the cafeteria for lunch– You won’t eat lunch (E) – If it’s not open (O) or– If they only serve corndogs (C)
• Write a truth table for determining if you will eat lunch (E).
O C E
0 00 11 01 1
Boolean Equations Example
Chapter 2 <14>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• You are going to the cafeteria for lunch– You won’t eat lunch (E) – If it’s not open (O) or– If they only serve corndogs (C)
• Write a truth table for determining if you will eat lunch (E).
O C E
0 00 11 01 1
0010
Boolean Equations Example
Chapter 2 <15>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN SOP & POS Form
• SOP – sum-of-products
• POS – product-of-sums
O C E0 00 11 01 1
mintermO CO CO CO C
O + CO C E
0 00 11 01 1
maxterm
O + CO + CO + C
Chapter 2 <16>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• SOP – sum-of-products
• POS – product-of-sums
O + CO C E
0 00 11 01 1
0010
maxterm
O + CO + CO + C
O C E0 00 11 01 1
0010
minterm
O CO CO C
O C
E = (O + C)(O + C)(O + C)
= Π(0, 1, 3)
E = OC
= Σ(2)
SOP & POS Form
Chapter 2 <17>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Axioms and theorems to simplify Boolean equations
• Like regular algebra, but simpler: variables have only two values (1 or 0)
• Duality in axioms and theorems:– ANDs and ORs, 0’s and 1’s interchanged
Boolean Algebra
Chapter 2 <18>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN Boolean Axioms
Chapter 2 <19>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• B 1 = B• B + 0 = B
T1: Identity Theorem
Chapter 2 <20>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
1 =
=
B
0B
B
B
• B 1 = B• B + 0 = B
T1: Identity Theorem
Chapter 2 <21>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• B 0 = 0• B + 1 = 1
T2: Null Element Theorem
Chapter 2 <22>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
0 =
=
B
1B
1
0
• B 0 = 0• B + 1 = 1
T2: Null Element Theorem
Chapter 2 <23>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• B B = B• B + B = B
T3: Idempotency Theorem
Chapter 2 <24>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
B =
=
B
BB
B
B
• B B = B• B + B = B
T3: Idempotency Theorem
Chapter 2 <25>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• B = B
T4: Identity Theorem
Chapter 2 <26>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
= BB
• B = B
T4: Identity Theorem
Chapter 2 <27>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• B B = 0• B + B = 1
T5: Complement Theorem
Chapter 2 <28>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
B =
=
B
BB
1
0
• B B = 0• B + B = 1
T5: Complement Theorem
Chapter 2 <29>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN Boolean Theorems Summary
Chapter 2 <30>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN Boolean Theorems of Several Vars
Note: T8’ differs from traditional algebra: OR (+) distributes over AND (•)
( )
Chapter 2 <31>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Y = AB + AB
Simplifying Boolean EquationsExample 1:
Chapter 2 <32>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Y = AB + AB = B(A + A) T8 = B(1) T5’ = B T1
Simplifying Boolean EquationsExample 1:
Chapter 2 <33>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Y = A(AB + ABC)
Example 2:
Simplifying Boolean Equations
Chapter 2 <34>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Y = A(AB + ABC) = A(AB(1 + C)) T8 = A(AB(1)) T2’ = A(AB) T1
= (AA)B T7 = AB T3
Example 2:
Simplifying Boolean Equations
Chapter 2 <35>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Y = AB = A + B
• Y = A + B = A B
AB
Y
AB Y
AB
Y
AB Y
DeMorgan’s Theorem
Chapter 2 <36>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Backward:– Body changes– Adds bubbles to inputs
• Forward:– Body changes– Adds bubble to output
AB
YAB
Y
AB
YAB
Y
Bubble Pushing
Chapter 2 <37>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
AB
YCD
• What is the Boolean expression for this circuit?
Bubble Pushing
Chapter 2 <38>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
AB
YCD
• What is the Boolean expression for this circuit?
Y = AB + CD
Bubble Pushing
Chapter 2 <39>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
AB
C
D
Y
• Begin at output, then work toward inputs• Push bubbles on final output back • Draw gates in a form so bubbles cancel
Bubble Pushing Rules
Chapter 2 <40>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
AB
C Y
D
Bubble Pushing Example
Chapter 2 <41>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
AB
C Y
D
no outputbubble
Bubble Pushing Example
Chapter 2 <42>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
bubble oninput and outputA
B
C
D
Y
AB
C Y
D
no outputbubble
Bubble Pushing Example
Chapter 2 <43>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
AB
C
D
Y
bubble oninput and outputA
B
C
D
Y
AB
C Y
D
Y = ABC + D
no outputbubble
no bubble oninput and output
Bubble Pushing Example
Chapter 2 <44>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Two-level logic: ANDs followed by ORs• Example: Y = ABC + ABC + ABC
BA C
Y
minterm: ABC
minterm: ABC
minterm: ABC
A B C
From Logic to Gates
Chapter 2 <45>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Inputs on the left (or top)• Outputs on right (or bottom)• Gates flow from left to right• Straight wires are best
Circuit Schematics Rules
Chapter 2 <46>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Wires always connect at a T junction• A dot where wires cross indicates a
connection between the wires• Wires crossing without a dot make no
connection
wires connectat a T junction
wires connectat a dot
wires crossingwithout a dot do
not connect
Circuit Schematic Rules (cont.)
Chapter 2 <47>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
A1 A0
0 00 11 01 1
Y3 Y2 Y1 Y0A3 A2
0 00 00 00 0
0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
A0
A1
PRIORITYCiIRCUIT
A2
A3
Y0
Y1
Y2
Y3
• Example: Priority Circuit Output asserted
corresponding tomost significantTRUE input
Multiple-Output Circuits
Chapter 2 <48>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
0
A1 A0
0 00 11 01 1
0
00
Y3 Y2 Y1 Y0
0000
0011
0100
A3 A2
0 00 00 00 0
0 0 0 1 0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
0001
1110
0000
0000
1 0 0 01111
0000
0000
0000
1 0 0 01 0 0 0
A0
A1
PRIORITYCiIRCUIT
A2
A3
Y0
Y1
Y2
Y3
• Example: Priority Circuit Output asserted
corresponding tomost significantTRUE input
Multiple-Output Circuits
Chapter 2 <49>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
A1 A0
0 00 11 01 1
0000
Y3 Y2 Y1 Y0
0000
0011
0100
A3 A2
0 00 00 00 0
0 0 0 1 0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
0001
1110
0000
0000
1 0 0 01111
0000
0000
0000
1 0 0 01 0 0 0
A3A2A1A0Y3
Y2
Y1
Y0
Priority Circuit Hardware
Chapter 2 <50>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
A1 A0
0 00 11 01 1
0000
Y3 Y2 Y1 Y0
0000
0011
0100
A3 A2
0 00 00 00 0
0 0 0 1 0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
0001
1110
0000
0000
1 0 0 01111
0000
0000
0000
1 0 0 01 0 0 0
A1 A0
0 00 11 XX X
0000
Y3 Y2 Y1 Y0
0001
0010
0100
A3 A2
0 00 00 00 1
X X 1 0 0 01 X
Don’t Cares
Chapter 2 <51>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Contention: circuit tries to drive output to 1 and 0– Actual value somewhere in between– Could be 0, 1, or in forbidden zone– Might change with voltage, temperature, time, noise– Often causes excessive power dissipation
• Warnings: – Contention usually indicates a bug.
– X is used for “don’t care” and contention - look at the context to tell them apart
A = 1
Y = X
B = 0
Contention: X
Chapter 2 <52>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Floating, high impedance, open, high Z• Floating output might be 0, 1, or
somewhere in between– A voltmeter won’t indicate whether a node is floating
Tristate Buffer
E A Y0 0 Z0 1 Z1 0 01 1 1
A
E
Y
Floating: Z
Chapter 2 <53>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Floating nodes are used in tristate busses– Many different drivers– Exactly one is active at once
en1
to bus
from bus
en2
to bus
from bus
en3
to bus
from bus
en4
to bus
from bus
shared busprocessor
video
Ethernet
memory
Tristate Busses
Chapter 2 <54>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Boolean expressions can be minimized by combining terms
• K-maps minimize equations graphically• PA + PA = P
C 00 01
0
1
Y
11 10AB
1
1
0
0
0
0
0
0
C 00 01
0
1
Y
11 10AB
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
B C0 00 11 01 1
A0000
0 00 11 01 1
1111
11000000
Y
Karnaugh Maps (K-Maps)
Chapter 2 <55>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
C 00 01
0
1
Y
11 10AB
1
0
0
0
0
0
0
1
B C0 00 11 01 1
A0000
0 00 11 01 1
1111
11000000
Y
• Circle 1’s in adjacent squares• In Boolean expression, include only
literals whose true and complement form are not in the circle
Y = AB
K-Map
Chapter 2 <56>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
C 00 01
0
1
Y
11 10AB
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
1
B C Y0 0 00 1 01 01 1 1
Truth Table
C 00 01
0
1
Y
11 10ABA
0000
0 0 00 1 01 0 01 1 1
1111
K-Map
3-Input K-Map
Chapter 2 <57>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
C 00 01
0
1
Y
11 10AB
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
1 0
B C Y0 0 00 1 01 01 1 1
Truth Table
C 00 01
0
1
Y
11 10ABA
0000
0 0 00 1 01 0 01 1 1
1111
0
1
1
1
0
0
0
K-Map
Y = AB + BC
3-Input K-Map
Chapter 2 <58>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Complement: variable with a bar over it A, B, C• Literal: variable or its complement A, A, B, B, C, C• Implicant: product of literals ABC, AC, BC• Prime implicant: implicant corresponding
to the largest circle in a K-map
K-Map Definitions
Chapter 2 <59>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Every 1 must be circled at least once• Each circle must span a power of 2 (i.e. 1, 2,
4) squares in each direction• Each circle must be as large as possible• A circle may wrap around the edges• A “don't care” (X) is circled only if it helps
minimize the equation
K-Map Rules
Chapter 2 <60>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
01 11
01
11
10
00
00
10AB
CD
Y
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110111
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
100000
4-Input K-Map
Chapter 2 <61>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
01 11
1
0
0
1
0
0
1
101
1
1
1
1
0
0
0
1
11
10
00
00
10AB
CD
Y
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110111
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
100000
4-Input K-Map
Chapter 2 <62>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
01 11
1
0
0
1
0
0
1
101
1
1
1
1
0
0
0
1
11
10
00
00
10AB
CD
Y
Y = AC + ABD + ABC + BD
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110111
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
100000
4-Input K-Map
Chapter 2 <63>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110X11
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
XXXXXX
01 11
01
11
10
00
00
10AB
CD
Y
K-Maps with Don’t Cares
Chapter 2 <64>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110X11
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
XXXXXX
01 11
1
0
0
X
X
X
1
101
1
1
1
1
X
X
X
X
11
10
00
00
10AB
CD
Y
K-Maps with Don’t Cares
Chapter 2 <65>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
0
C D0 00 11 01 1
B0000
0 00 11 01 1
1111
1
110X11
YA00000000
0 00 11 01 1
0000
0 00 11 01 1
1111
11111111
11
XXXXXX
01 11
1
0
0
X
X
X
1
101
1
1
1
1
X
X
X
X
11
10
00
00
10AB
CD
Y
Y = A + BD + C
K-Maps with Don’t Cares
Chapter 2 <66>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Multiplexers• Decoders
Combinational Building Blocks
Chapter 2 <67>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Selects between one of N inputs to connect to output
• log2N-bit select input – control input• Example: 2:1 Mux
Multiplexer (Mux)
Y0 00 11 01 1
0101
0000
0 00 11 01 1
1111
0011
0
1
S
D0Y
D1
D1 D0S Y01 D1
D0
S
Chapter 2 <68>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
2-<68>
• Logic gates– Sum-of-products form
Y
D0
S
D1
D1
Y
D0
S
S 00 01
0
1
Y
11 10D0 D1
0
0
0
1
1
1
1
0
Y = D0S + D1S
• Tristates– For an N-input mux, use N
tristates– Turn on exactly one to
select the appropriate input
Multiplexer Implementations
Chapter 2 <69>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
A B Y0 0 00 1 01 0 01 1 1
Y = AB
00
Y0110
11
A B
• Using the mux as a lookup table
Logic using Multiplexers
Chapter 2 <70>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
A B Y0 0 00 1 01 0 01 1 1
Y = AB
A Y
0
1
0 0
1
A
BY
B
• Reducing the size of the mux
Logic using Multiplexers
Chapter 2 <71>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
2:4Decoder
A1
A0
Y3Y2Y1Y000
011011
0 00 11 01 1
0001
Y3 Y2 Y1 Y0A0A1
0010
0100
1000
• N inputs, 2N outputs• One-hot outputs: only one output HIGH at
once
Decoders
Chapter 2 <72>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
Y3
Y2
Y1
Y0
A0A1
Decoder Implementation
Chapter 2 <73>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
2:4Decoder
AB
00011011
Y = AB + AB
Y
ABABABAB
Minterm
= A B
• OR minterms
Logic Using Decoders
Chapter 2 <74>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
A
Y
Time
delay
A Y
• Delay between input change and output changing
• How to build fast circuits?
Timing
Chapter 2 <75>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
A
Y
Time
A Y
tpd
tcd
• Propagation delay: tpd = max delay from input to output
• Contamination delay: tcd = min delay from input to output
Propagation & Contamination Delay
Chapter 2 <76>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Delay is caused by– Capacitance and resistance in a circuit– Speed of light limitation
• Reasons why tpd and tcd may be different:– Different rising and falling delays– Multiple inputs and outputs, some of which are
faster than others– Circuits slow down when hot and speed up when
cold
Propagation & Contamination Delay
Chapter 2 <77>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
AB
C
D Y
Critical Path
Short Path
n1
n2
Critical (Long) Path: tpd = 2tpd_AND + tpd_OR
Short Path: tcd = tcd_AND
Critical (Long) & Short Paths
Chapter 2 <78>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• When a single input change causes an output to change multiple times
Glitches
Chapter 2 <79>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
AB
C
Y
00 01
1
Y
11 10AB
1
1
0
1
0
1
0
0
C
0
Y = AB + BC
• What happens when A = 0, C = 1, B falls?
Glitch Example
Chapter 2 <80>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
A = 0B = 1 0
C = 1
Y = 1 0 1
Short Path
Critical Path
B
Y
Time
1 0
0 1
glitch
n1
n2
n2
n1
Glitch Example (cont.)
Chapter 2 <81>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
00 01
1
Y
11 10AB
1
1
0
1
0
1
0
0
C
0
Y = AB + BC + ACAC
B = 1 0Y = 1
A = 0
C = 1
Fixing the Glitch
Chapter 2 <82>
COM
BIN
ATIO
NAL
LO
GIC
DES
IGN
• Glitches don’t cause problems because of synchronous design conventions (see Chapter 3)
• It’s important to recognize a glitch: in simulations or on oscilloscope
• Can’t get rid of all glitches – simultaneous transitions on multiple inputs can also cause glitches
Why Understand Glitches?
