Chapter 2 Digital Circuits (TTL and CMOS) (Based on ...€¦ · 6.2.8 Fanout: Fanout is a number ... VOHmin of the driver gate > VIHmin of the driven gate VOLmax of the driver

EE201L_ClassNotes_Ch2.fm

1/15/07 EE201L Class Notes - Chapter #2 Page 1 / 40C Copyright 2007 Gandhi Puvvada

Chapter 2Digital Circuits (TTL and CMOS)

(Based on Chapter 3 Digital Circuits in Wakerly)

1 Logic Signals and physical phenomena representing them

Compared to ANALOG, DIGITAL STORAGE and RETRIEVAL and DIGITAL COMPUTATION are more RELIABLE and REPEATABLE because of the NOISE IMMUNITY of digital circuits.

Representation of digital signals (1, 0) in different technologies: (Table 3.1 of Wakerly)

TTL

CMOS 0-1.5V

0-0.8V

3.5-5.0V

2.0-5.0V



2 Logic Signal Levels: Consider TTL logic signal levels.

0 - 0.8V represents signal LOW condition (i.e. LOGIC 0).So, whether the signal is 0.3V or 0.5V or 0.7V, it is UNAMBIGUOUSLY interpreted by any gate receiving this signal as LOW or LOGIC 0.0V ZERO VOLTS is the IDEAL value for LOGIC 0.5V FIVE VOLTS is the IDEAL value for LOGIC 1.

A gate, apart from performing its LOGIC FUNCTION, serves as a BUFFER AMPLIFIER to REGENERATE "WEAK" (not so ideal) input signals into "STRONG" (nearly ideal) output signals.

As can be seen from the Table 3.1 on the previous page, logic can be implemented in a variety of technologies. In fact logic gates can be implemented in pneumatic and hydraulic systems for special purpose applications in hazardous areas in petrochemi-cal plants. For this course, we need to study only TTL and CMOS (mostly TTL).

2.8VLogic 1

3.2VLogic 1

3.6VLogic 1

Noise

OhmicDrop

2.6VLogic 1

0.4VLogic 0

Note: Any signal in the range of 2.0V-5.0V is an ACCEPTABLEHIGH (LOGIC 1) at the input of any TTL gate.



3 Major Logic families: TTL and CMOS

TTL (Transistor-Transistor Logic): Introduced in 1960. Became very popular but gradually replaced by CMOS.

CMOS (Complementary Metal-Oxide Semiconductor): Uses both NMOS and PMOS transistors in complementary fashion.Supplanted TTL, thanks to its superior speed and low power consumption.

Some more families:NMOS (N-Channel Metal-Oxide Semiconductor): Uses only NMOS transistors.

ECL (Emitter Coupled Logic): Very fast bipolar logic but consumes too much power and hence not used.

4 Subfamilies:

TTL and CMOS have several subfamilies some consuming more power and faster and some consuming less power and slower.

The low-voltage subfamilies use an operating voltage lower than 5V. For example, 3.3V LVTTL (low-voltage TTL) and 1.8V LVCMOS (low-voltage CMOS).

5 Various CRITERIA to choose a particular logic family to suit an application:

SPEEDPOWER DISSIPATIONCOSTAVAILABILITY (popularity and breadth)FANOUT (Load Handling Capability)



6 TTL Characteristics:

We cover here only the EXTERNAL CHARACTERISTICS of TTL gates.The internal design details are not in the scope of this course.

6.1 VOLTAGE and CURRENT:

Question: Is a signal a VOLTAGE or a CURRENT ?

Answer:

Analogy between an electrical system and a hydraulic system:VOLTAGE is similar to ______________ water PRESSURE / water FLOW.CURRENT is similar to ______________ water PRESSURE / water FLOW.

Difference between a 12V CAR BATTERY and a stack of eight 1.5V D-CELLs?

Difference between ordinary Alkaline rechargeable batteries you use in a calcula-tor and the heavy duty NiMH (Nickel-Metal Hydride) batteries used in Digital Cameras?

For electric wires, where/when do you need more insulation

and when do you need thicker copper wire?

When you travel to Europe, before plugging in your Blow Dryer into the outlet near the bathroom sink, you need to know its VOLTAGE requirement and its CURRENT requirement.

1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V12 V



Which of the two (VOLTAGE and CURRENT) a fixed item and which is a variable?

Car batteries are usually rated 12V 400A.What happens if you are just using a small cabin light?

Ohms law: I = V / R

Please understand the difference between current capability of the battery and the actual current delivered to a specific load.



6.2 EXTERNAL CHARACTERISTICS of TTL gates represent the parameters of the gates you (the board-level designer) need to know to successfully complete your design. They vary from family to family. We chose to cover TTL characteristics.

6.2.1 SUPPLY VOLTAGE VCC = 5V 0.25V (Max 5.25V, Min. 4.75V)

6.2.2 VOH and VIH For HIGH signal, HIGHER the BETTER!

6.2.3 VOL and VIL For LOW signal, LOWER the BETTER!

+-

VOH VIH

MINIMUM (GUARANTEED)HIGH OUTPUT VOLTAGE

2.4V

MINIMUM VOLTAGEGUARANTEED TO BERECOGNIZED AS "HIGH" INPUT

2.0VCompatibilityRequirementVOH > VIH

VOL VIL

MAXIMUM LIMIT OFOUTPUT VOLTAGE FOR

0.4V

MAXIMUM VOLTAGEGUARANTEED TO BERECOGNIZED AS "LOW" INPUT

0.8VCompatibilityRequirementVOL < VIL

LOW LEVEL OUTPUT



6.2.4 IOH and IIH Capability shall be as _______ (high/low) as possible. Demand shall be as _______ (high/low) as possible.

6.2.5 IOL and IIL

Note the SIGN CONVENTION. Current into the gate is considered positive. Hence we needed to use the modulus operator in the compatibility statements above.

IOH IIH

MAXIMUM ACCEPTABLECURRENT LOADING

- 0.4mA

MAXIMUM CURRENTCONSUMPTION WHEN INPUT IS AT HIGH LEVEL

+ 40uACompatibilityRequirementIOH > IIH

(= MINIMUM ASSURED CURRENT OUTPUT CAPABILITY) UNDER HIGH LEVEL CONDITION

Capability should exceed demand.Sour

cing

Capab

ility

IOL IIL

MAXIMUM ACCEPTABLECURRENT LOADING

+ 16mA

MAXIMUM CURRENT"THROWN OUT" WHEN INPUT IS AT LOW LEVEL BY

- 1.6mACompatibilityRequirementIOL > IIL

(= MINIMUM ASSURED CURRENT SINKING CAPABILITY) UNDER LOW LEVEL CONDITION

Capability should exceed demand.Sink

ing

Capab

ility

THE INPUT STAGE



Direction of currents IOL and IIL:

The direction of currents IOL and IIL may be confusing because it is counter-intuitive.Our intuition tells us that the current shall flow in the direction of the signal propagation. But, remember that the CURRENT is NOT the SIGNAL; VOLTAGE is the SIGNAL.

To understand the direction of current flow, let us take an analogy of a pneumatic system with a signal driver and a signal receiver. The signal here is the air pressure. The signal driver either turns on the blower to convey a high pressure signal or the vacuum pump to convey a low pressure signal.

Similar to the fact that the air flows away from the signal receiver towards the signal driver during the low pressure signal transmission, the current, during low voltage signal transmission between logic gates, flows from the receiving gate to the driving gate.

6.2.6 NOISE MARGINS:

SIGNAL DRIVER SIGNAL RECEIVERSignal: HIGH PRESSUREAIR FLOW IOH IIH

Signal: LOW PRESSUREAIR FLOW IOL IIL

Blower

Vacuum pump

0V (ideal low)

5V (ideal high)

VOHmin = 2.4VVIHmin = 2.0V

VILmax = 0.8V

VOLmax = 0.4VVOLtypical = 0.2V

VOHtypical = 3.6VHigh-StateDC Noise Margin =VOHmin - VIHmin =2.4V - 2.0V = 0.4V

Low-StateDC Noise Margin =V - V = V - V = V

VOH VIH

Noise Margin = VOHmin - VIHmin = 2.4V - 2.0V = 0.4V

High-State Noise Margin

VOL VIL

Noise Margin = V - V

= V - V = V

Low-State Noise MarginSignal levelambiguous



6.2.7 Propagation delays

After an input change, for the output to change, the gate takes some time. This is called propagation delay. For logic gates, there are TWO delay parameters (not just ONE!).

tpHL = Time taken by the OUTPUT to go

from HIGH to LOW after a corresponding event at the input (whatever it is).

tpLH = Time taken by the OUTPUT to go

from LOW to HIGH after a corresponding event at the input (whatever it is).

Note: The suffixes, HL and LH in tpHL and tpLH refer to OUTPUT TRANSITIONS.

6.2.8 Fanout:

Fanout is a number indicating how many gates (how many gate inputs) can be driven by one gate (one gate output).

The driving gate shall be capable of conveying both HIGH state and LOW state signals by meeting the current demands of the driven gates.

6.2.9 FAN-IN: Similar to FANOUT, there is a term called FAN-IN. It specifies the number of inputs coming into the gate. If a logic family is said to have a fan-in of 4 if in general the maximum number of inputs on gates in that family is 4. While in principle, you can think of an 8-input NAND gate, in practice, it is built using two 4-input NAND gates, a 2-input NOR gate, and an inverter.

A B

A

B

tpHL tpLH

Driving Gate

Dri

ven

gate

s

FANOUT = minimum of IOHmax{ } ; {IIHmax

IOLmaxIILmax

}the ratios

= minimum of -400 uA{ } ; {+40uA

+16mA-1.6mA } = 10

for

STA

ND

AR

D T

TL

Fig. 3-17 from Wakerly



7 TTL Subfamilies:

Two major series of TTL chips based on operating conditions:

74 Series: Industrial grade ICs for operation at 00 to 700C

54 Series: Premium grade ICs for operation at -550 to +1250C for mainly military and space applications.

Within each of the above series there are several subfamilies which mainly differ in their DELAY (SPEED) and the amount of POWER they consume. Speed can easily be improved if you are allowed to consume more power. However, we want less delay and less power. Hence the POWER-DELAY PRODUCT is used as a figure of merit comparing designs.

Inverters from obsolete families:

7404 STANDARD TTL74L04 L = Low Power (consumes less power compared to Standard TTL)

Also slower than 74 series.)74H04 H = High Speed (Faster but consumes more power)

Inverters from TTL families existing in design in 1980’s (Schottky families):

74S04 S = Schottky These are much faster than the Standard TTL without too much increase in power consumption

74LS04 LS = Low Power Schottky

74AS04 AS = Advanced Schottky (Faster than Schottky)74ALS04 ALS = Advanced Low Power Schottky (Faster than 74LS)74F04 F = Fast (between 74AS and 74ALS)



The following table lists the characteristics of the above 5 subfamilies (from Wakerly).

8 Compatibility among various families/subfamilies of chips

Signal Voltage Compatibility requirement:

VOHmin of the driver gate > VIHmin of the driven gateVOLmax of the driver gate < VILmax of the driven gate

Normally there is no problem with this among the subfamilies of a family. However usually signal voltage compatibility does not exist across different families. For example the worst case TTL HIGH output (VOHmin of 2.4V) is not suitable as HIGH

input to a CMOS gate (VIHmin of 3.5V). In such cases, a pull-up resistor or a special level

shifting circuits are used to convert signals from one family to signal suitable as inputs to another family.Voltage compatibility may exist among subfamilies, but sometimes noise margins may differ. (Example: VOHmin of any subfamily is higher than VIHmin of any subfamily but the difference between them

may change depending on the two subfamilies involved. Case 1: 2.7 - 2.0 = 0.7V; Case 2: 2.4 - 2.0 = 0.4V.Note: VOHmin of standard TTL (plain 74 series) is only 2.4V.)



Current specs vary a lot even among subfamilies. Hence the FANOUT number applies only within a subfamily (and not across subfamilies). Hence, if you are using gates from a variety of subfamilies in one circuit, it is necessary that we perform a current capacity check as shown below.

Current Capacity Check: The driver gate shall have enough current output

capability to meet sum of the demands of all the receiving gates.

9 Some IC packages:

Driving Gate

Dri

ven

gate

s| IOHmax | >= Σ | IIHmax |

| IOLmax | >= Σ | IILmax |

1 14

87

14-pin DIP (Dualinline) package

PLCCPlastic Leaded Chip Carrier

PGAPin Grid Array

GND

VCC

BGABall Grid Array



10 Typical manufacturer’s data sheet for the 74LS00 (Try "google" to find the complete data sheet on the web).



11 CMOS logic families (sec. 3.8 in Wakerly 4th ed.):

4000-series CMOS: Slow and obsolete74HC HC = High-speed CMOS74HCT HCT = High-speed CMOS, TTL Compatible

An input of 2.1V is ambiguous to (or may be treated as low by) an HC device. where as, it is clearly high for TTL and HCT devices.

74AHC AHC = Advanced High-speed CMOS (advanced = faster than the HC)

74AHCT AHCT = Advanced High-speed CMOS, TTL Compatible

Fig. 3-61 Transfer Characteristics of HC and HCT inverters.Fig. 3-60 Input and output levels for CMOS devices using 5V supply: (a) HC; (b) HCT

Note 1uAIIH/IIL

VILmaxVIHmin

morecurrent

TTL Load =

Table 3.6 Input specifications for CMOS families with VCC between 4.5 and 5.5V

Table 3.7 Output specifications for CMOS families with VCC between 4.5 and 5.5V

Note: The question of TTL compatibility araises only with the VILmax and VIHmin specifications.

(Output specs are same for HC/HCT; they are same for AHC/AHCT also.



AC/ACT (Advanced CMOS) have much higher current drive capability (IOH/IIL).They are particularly useful to drive heavy DC loads.The VOHmin and VOLmax for most CMOS families (HC, HCT, AHC, AHCT, AC, ACT)

are specified for a CMOS load on its output (less load current) as well as TTL load.

FCT (Fast CMOS TTL compatible) is TTL compatible and is similar to ACT but the raise and fall times are deliberately slowed down to reduce "analog" transmission line reflection problems. FCT-T (Fast CMOS TTL compatible with TTL VOH) has reduced VOH . While

the VOH of FCT (or AC or ACT) is superior to TTL, the VOH of FCT-T is made similar to

TTL. The idea is to limit the swing (VOL to VOH or VOH to VOL) so that both power

consumption and switching noise problems are reduced. Consider the analogy of a water-hammer to understand switching noise.

12 Digilent board D2XL with Xilinx FPGA XC2S30 TQ144 (Students are not responsible for this

item)

The Xilinx Spartan 2 FPGA XC2S30 has an internal core running at 2.5V. Technology used might be some proprietary MOS tech-nology (mostly CMOS/NMOS). The FPGA has two power supply connections: VCCINT ( = 2.5V) to power the core and VCCO (= 1.5V or 2.5V or 3.3V depending on the type of I/O the user wishes to connect to the FPGA).

Note that the CMOS logic has voltage parameters distributed symmetrically over 0 to Vcc.

Fig. 3-62 Comparison of logic levels

Note: All voltage parameters for 5V TTL and 3.3V LVTTL are the same!

XilinxFPGAXC2S30

VCCINTVCCO

2.5V3.3V



Digilent have connected 3.3V to the VCCO so that both LVTTL and regular 5V TTL I/O can be connected.The digilent board D2XL and the associated DIO1 board use 74HC series gates (74HC244, 74HC14). However, you can attach regular 5V TTL such as 74LS04 as Input/output. Some details from the Xilinx data sheet are given below.



13 Exercise:

13.1 Manufacturer Smith offers TTL devices with VOHmin = 2.7VManufacturer Bates offers TTL devices with VOHmin = 2.4VWhose devices are better? Smith / Bates

13.2 Manufacturer ABC offers TTL devices with VILmax = 0.7VManufacturer XYZ offers TTL devices with VILmax = 0.9VWhose devices are better? ABC / XYZNote: Best low is 0.0V.

13.3 Consider the digital comparator on the right. Input X is driven by 4.6V.Input Y is driven by 3.8V.Which output will be TRUE? X > Y / X = Y / X < Y

13.4 Is it better to have wide noise margin or narrow noise margin? Wide / NarrowHigh State Noise Margin = V - VLow State Noise Margin = V - V

13.5 Given that three inverters connected in series as shown below, label and find the values for each of the 6 delays in the waveform.

13.6 Which of the following are NOT usually found in a data sheet? Cross them off.

VIHmin / VIHmax; VILmin / VILmax; VOHmin / VOHmax; VOLmin / VOLmax;

IIHmin / IIHmax; IILmin / IILmax; IOHmin / IOHmax; IOLmin / IOLmax;

13.7 You know that VOLmax = 0.8V. Give a typical value of the same. VOLtyp = _____V.

13.8 Do you use AC (Alternating Current) or DC (Direct Current) to power your ICs? AC / DC

X

Y

X > YX = YX < Y

4.6V

3.8V

A

B

C

D

A

tpHL = 1.5nstpLH = 2.2ns



B C D



13.9 Buffers are used to make weak signals stronger.

Buffers are also used at the entry to a subsystem so that the loads in the subsystem are handled by the buffer. Example: Address buffer at the entry to an add-on PCI card.

A buffer can be compared to a Power Steering in a car.

If you compare a buffer in TTL gates or a power booster in a power-assisted steering with an amplifier, what exactly is amplified?

In a buffer in TTL gates, is VOLTAGE amplified? Example: 0.7V becomes 0.7 x 4 = 2.8V?

In a power booster in a power-assisted steering, is rotational displacement amplified?Example: Compared to a manual steering, a power-assisted steering causes the wheels to rotate more?!

Buffer

A10

uPBA10

Address line A10

ProcessorSubsystem

PCI Card #1

BA10 BB1_A10

inte

rnal

load

s

PCI Card #8

BA10 BB8_A10

inte

rnal

load

s

PCB trace(Lengthy and Highly Capacitive)

From the "HowStuffWorks" web page



13.10 A manufacturer has designed a NEW series of digital gates 74USCxxx. Note: these need not be compatible with any existing series of gates.

He tested a number of inverters (74USC04) and plotted their INPUT/OUTPUT characteristic.

Given below is the "SPREAD" of the plots. Help him write the four voltage specs.State min or max for each. Provide a 0.1V process tolerance margin over and above the band of characteristics shown.

13.11 In the design below, we have cascaded two inverters (with slightly different specs to make a non-inverting buffer. Find the four voltage specs for the resulting non-inverting buffer.Use "max" or "min" for each of the specs.

Is the above 74_new_04 superior or inferior (or superior in some specs and inferior in some other specs) than the 74LS04? ____________________________________________________

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

VIH = _____________ V

VIL = _____________ V

VOH = _____________ V

VOL = _____________ V

A B C

A C

VIH = 2.0VVIL = 0.8V

VOH = 2.7VVOL = 0.5V

VIH = 1.9VVIL = 0.9V

VOH = 2.9VVOL = 0.3V

74LS04 74_new_04

resulting non-inverting buffer

VIH = VVIL = V

VOH = VVOL = V



14 Transfer Characteristics of TTL gates

14.1 Transfer Characteristic = a plot of output voltage signal vs. input voltage signal

Which of the following is the closest representation of the Transfer Characteristic of a TTL inverter?

14.2 The TTL inverter 74LS04 has a transfer characteristic which looks like the one shown on the side.

The actual kinks in the shape are due to the nonlinear behavior of a bipolar transistor.We are NOT interested in these details, but given a choice, would you like to reshape the characteristic as "A" or "B"?

VI VO

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)A B



Consider aspects such as larger VILmax and lower VIHmin which possibly lead to wider noise margins.

Given as input, which one of the will produce n

and which would produce n ?

Which is preferable and why?

Also consider the characteristic being touchy (very sensitive) to noise.

14.3 Transmission of a digital signal over a long (> 1 foot) of a ribbon cable or a PCB trace:

Ideal

Due to resistanceand capacitanceof the ribbon cable,signals get rounded.

Noise can further creep in.

Behavior #1

Behavior #2

Behavior #3

time

Vol

tage

VI

VT Single Threshold

time

Vol

tage

VO

time

Vol

tage

VO



14.4 So finally do you want to reshape the characteristic to look like "A" or "B" ?

14.5 We want the advantage of "B" shown in "Behavior #2" namely turning rounded signals into sharp signals, but at the same time, we do not want the disadvantage of "Behavior #3" namely noise amplification.

That is where a schmitt trigger input gate with two thresholds has an advantage.

14.6 Unlike an ordinary inverter such as 74LS04 which has a single threshold (VT = ~ 1.3V), a schmitt trigger inverter 74LS14 has two thresholds: a positive going threshold VT+ = ~1.7V a negative going threshold VT- = ~0.9V

The difference between the two thresholds,VT+ - VT- = 1.7V - 0.9V = 0.8V is called the hysteresis.

If the input was low and is now rising up (but in a noisy environment), the schmitt-trigger input device (such as a 74LS14 inverter or a 4-input NAND 74LS13) will not treat the input as having gone HIGH until there is a substantial evidence at the input namely the crossing of the VT+ in the positive direction. Once the input crosses VT+ in the positive direction, the output switches and then onwards the VT+ has no significance. Only when there is a substantial evidence at the input to indicate that the input has gone really low by crossing VT-, in the negative direction, the output switches again. This hysteresis helps to filter noise as can be seen in the diagrams below.

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

VT+VT-Dir

ectio

n of

the

arro

ws i

s im

port

ant!

Dictionary (http://dictionary.reference.com/browse/hysteresis) definition of the word hysteresis:

1. the lag in response exhibited by a body in reacting to changes in the forces, esp. magnetic forces, af-fecting it. 2. the phenomenon exhibited by a system, often a ferromagnetic or imperfectly elastic material, in whichthe reaction of the system to changes is dependent upon its past reactions to change.



TTL

VT+ = ~1.7V

VT- = ~0.9V

74LS13

74LS00

VT = ~1.3V

Figures 3-25, 3-47 and 3-48from Wakerly (4th Edition)

VT+ = 2.9V

VT- = 2.1VVT = 2.5V



14.7 Schmitt-trigger inverter response to triangular wave input (your lab experiment)

14.8 Schmitt-trigger applications:

14.8.1When TTL signals have to travel long distances (more than 1 foot, for example from one PCB to another PCB through ribbon cable) the receiving device input shall be schmitt-trigger input type.

VI

VO

VT+VT-

A10

uPBA10

Address line A10

ProcessorSubsystem

PCI Card #1

BA10 BB1_A10

inte

rnal

load

sPCB trace(Lengthy and Highly Capacitive)

Note

PCI Card #8

BA10 BB8_A10

inte

rnal

load

sNote

Noise can easilyget into the signal here

From www.ti.com 74LS241 buffer application



14.8.2 In RESET circuits

14.8.3To square-up slowly varying signals

14.9 Recognizing a schmitt-trigger input device:

In the symbols for devices with schmitt-trigger input, they show the hysteresis symbol:

VCC

RESET

t

VCVC

Node IN VT+

Any noise at the Node INcan potentially cause theRESET signal to go up anddown if we use an ordinarybuffer to produce RESET.

Note: 74S04

S = Schottky (not Schmitt-trigger)There is no special letter in the

that it has schmitt-trigger input. device number to indicate

Note or

From Texas Instruments (www.ti.com) Octal tri-state buffer 74LS241



15 Exercise:

15.1 Which of the following is the closest representation of the Transfer Characteristic of a TTL schmitt-trigger inverter 74LS14?

15.2 In the design below, we have cascaded two schmitt-trigger inverters (with identical specs to make a non-inverting schmitt-trigger buffer.

Which of the above four is the closest representation of the Transfer Characteristic of the resulting non-inverting schmitt-trigger buffer?

15.3 To produce the desired non-inverting schmitt-trigger buffer, is it necessary to use both schmitt-trigger type inverters in the cascade or is it enough to use one schmitt-trigger type inverter and one ordinary inverter? ________ (both / one)If one is adequate, which one of them shall be a schmitt-trigger type inverter?__________________ (first / second / either).

15.4 If you use both schmitt-trigger type inverters in the cascade, and if they have slightly different VT+ and VT-, the resulting non-inverting schmitt-trigger buffer would have VT+ and VT-, which are _____________________________________( same as the first inverter / same as the second inverter / average of the two sets of specs).

15.5 "schmitt-trigger" is an attribute to describe the behavior at the ___________________ (input/output/input and output) of the gate.

VI VO

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

Note

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

Note

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

Note

1 2 3 4 5

1

2

3

4

5

Input (VI)

Out

put (

VO

)

Note

Arrows differ Arrows differ

A B C D

VI VO

Documents

Chapter 2 Digital Circuits (TTL and CMOS) (Based on ...€¦ · 6.2.8 Fanout: Fanout is a number ... VOHmin of the driver gate > VIHmin of the driven gate VOLmax of the driver