Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

Chapter 10Finite State Machines Synthesis

SKEE2263 Digital Systems

Mun’im/Ismahani/Izam

FEE, Universiti Teknologi Malaysia

April 15, 2016

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

Table of Contents

1 Design Process

2 Single-Mode Counters

3 Multimode Counters

4 Sequence Detectors

5 Multi-Sequence Detectors

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

FSM Design Process

Step Description

Conceptualize Understand the statement of the specification.

Capture the FSM Translate the problem into state diagram. Determinethe number of states required, inputs,outputs and state transitions.

Encode the states Assign a unique binary number to each state.

Create the state table Create a truth table for the combinational logic fornext state generation and output decoding.

Extract the equations Express the logic circuits as Boolean equations.

Implement the FSM Enter and verify the design.

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

Counters

Definition of counters:Starts from a particular stateGoes thru fixed sequence of statesReturns to initial stateRepeats indefinitely

Most counters (but not all) are Medvedev state machinesMedvedev machine have not output logic.Register outputs = system outputs.

Single-mode counters:The only input is the clock signal

Multi-mode counters:Has input to select mode of operation

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

2-bit Binary Counter

Binary Countersn state variables ⇒ 2n sequential states

Binary 2-bit counter : straight binary sequence 0→1→2→3→0

00

10

11 01

Present State Next State

Q1 Q0 Q+1 Q+

0

0 0 0 10 1 1 01 0 1 11 1 0 0

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

2-bit Binary Counter

Present State Next State

Q1 Q0 Q+1 Q+

0

0 0 0 10 1 1 01 0 1 11 1 0 0

Q+1 = Q1 ⊕Q0

Q+0 = Q′

0

D Q Q1

D Q Q0

Clock

Q

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

Counter with Arbitrary Sequence

Counter next states can benon-sequentialNumber of states can be <2n

All valid:0→3→1→2→0,0→1→3→2→0,0→1→3→0

00

11 01

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

Counter with Arbitrary Sequence

Present State Next State

Q1 Q0 Q+1 Q+

0

0 0 0 10 1 1 11 0 × ×1 1 0 0

Q+1 = Q′

1Q0

Q+0 = Q′

1

D Q Q1

D Q Q0

Clock

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

Definition

Multi-Mode CounterA counter whose counting sequence depends not only on theclock but also on some other control signal(s).

Examples:Counts up or downCounts in binary or Gray sequenceIncrements either +1 or -2Counts up or holds count value

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

3-bit Up/Down Counter

100101

110

111 001000

011

010

0

0

00

0

0

11

1

1 1

1

00

1

1

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

3-bit Up/Down Counter

Present State Input Next State

Q2 Q1 Q0 U Q+2 Q+

1 Q+0

0 0 0 0 1 1 10 0 0 1 0 0 10 0 1 0 0 0 00 0 1 1 0 1 00 1 0 0 0 0 10 1 0 1 0 1 10 1 1 0 0 1 00 1 1 1 1 0 01 0 0 0 0 1 11 0 0 1 1 0 11 0 1 0 1 0 01 0 1 1 1 1 01 1 0 0 1 0 11 1 0 1 1 1 11 1 1 0 1 1 01 1 1 1 0 0 0

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

3-bit Up/Down Counter

Q+2 = Q′

2Q′1Q

′0U

′ +Q′2Q1Q0U +Q2Q1Q

′0 +Q2Q0U

′ +Q2Q′1U

Q+1 = Q′

1Q′0U

′ +Q′1Q0U +Q1Q

′0U +Q1Q0U

′

Q+0 = Q′

0

Several ways to realize the design:Logic gates: complex wiringMuxDecoderROMBehavioral Verilog: easiest

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

How to Design a Sequence Detector

Start with the expected sequence first.Assert the output at the last state.Add exit arrows to cover all possible transitions.

Each state must have two exit arrows.

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

110 Sequence Detector: Moore

IN : 1 1 0 0 0 1 1 0 1 1 1 1 0OUT : 0 0 1 0 0 0 0 1 0 0 0 0 1

State Meaning

S0 No matching bits yetS1 1 (first bit) foundS2 1 (second bit) foundS3 0 (third bit) found, assert output

0

0

1

Reset

S1[0]

0

0 1

11

S2[0]

S0[0]

S3[1]

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

110 Sequence Detector: Moore

0

0

1

Reset

S1[0]

0

0 1

11

S2[0]

S0[0]

S3[1]

State Encoding

Symbolic Encoded

S0 00S1 01S2 10S3 11

Present State Input Next State Output

Q1 Q0 x Q+1 Q+

0 z

0 0 0 0 0 00 0 1 0 1

0 1 0 0 0 00 1 1 1 0

1 0 0 1 1 01 0 1 1 0

1 1 0 0 0 11 1 1 0 1

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

110 Sequence Detector: Moore

1

00

0

x

1

01 11 10

1

00

0

1

01 11 10

1

0

0

1

1

1

QQ1 0

xQQ1 0

Q0

D1

z

Q1

1 1

1

D0

D1 = Q1Q′0 +Q′

1Q0x

D0 = Q′1Q

′0x+Q1Q

′0x

′ +Q1Q0x

z = Q1Q0

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

110 Sequence Detector: Moore

D1 = Q1Q′0 +Q′

1Q0x

D0 = Q′1Q

′0x+Q1Q

′0x

′ +Q1Q0x

z = Q1Q0

Q

Clk

z

x

QD

Q

D

QQ

Q

DD

1

0

1

0

Reset

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

110 Sequence Detector: Mealy

IN : 1 1 0 0 0 1 1 0 1 1 1 1 0OUT : 0 0 1 0 0 0 0 1 0 0 0 0 1

S0

S1

S2

Reset

1/0

0/1

1/0

1/0

0/0

1/00/0

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

110 Sequence Detector: Mealy

S0

S1

S2

Reset

1/0

0/1

1/0

1/0

0/0

1/00/0 State Encoding

Symbolic Encoded

S0 00S1 01S2 10S3 11

Present State Input Next State Output

Q1 Q0 x Q+1 Q+

0 z

0 0 0 0 0 00 0 1 0 1 0

0 1 0 0 0 00 1 1 1 0 0

1 0 0 0 0 11 0 1 1 0 0

1 1 0 X X X1 1 1 X X X

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

110 Sequence Detector: Mealy

1

00

0

x

1

01 11 10

1

00

0

1

01 11 10

1

00

0

1

01 11 10

1

x

x

QQ1 0

x

x

x

x

xQQ1 0

xQQ1 0

D1

z

D0

D1 = Q1x+Q0x

D0 = Q′1Q

′0x

z = Q1x′

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

00-then-11 Detector

Detect 00 followed by any sequence ending with 11.11 can follow 00 immediately, or after any number of bits.Output 1 for exactly one clock cycleLet us use Gray state encoding.

S0

1Reset

S1 S2

00

1

S3

0

1

1

0

S4[1]

0

1

000Stateassignment

001 011 010 110

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

00-then-11 detector

Present State Input Next State Output

Q2 Q1 Q0 x Q+2 Q+

1 Q+0 y

0 0 0 0 0 0 1 01 0 0 0

0 0 1 0 0 1 1 01 0 0 0

0 1 0 0 0 1 1 01 1 1 0

0 1 1 0 0 1 1 01 0 1 0

1 0 0 X X X X X

1 0 1 X X X X X

1 1 0 0 0 0 1 11 0 0 0

1 1 1 X X X X X

Design Process Single-Mode Counters Multimode Counters Sequence Detectors Multi-Sequence Detectors

00-then-11 Detector

Q+2 = Q′

2Q1Q′0x

Q+1 = Q′

2Q1 +Q0x′

Q+0 = x′

y = Q2