Chapter 10

Adaptive

Delta Demodulator

10-1 Curriculum Objective

1. To understand the operat ion theory of adapt ive delta demodulation.

2. To understand the signal waveforms of ADM demodulation.

3. Design and implementation of ADM demodulator.

4. Measurement and adjustment of ADM demodulator.

10-2 Curriculum Theory

1. The Operation Theory of ADM Demodulation

In chapter 9, we utilized the structure of delta modulator and Δ(t) controlled circuit to

implement the ADM modulator and we also know that the modulated ADM signal is a kind of

TTL signal. Figure 10-1 is the block diagram of ADM demodulator. In figure 10-1, we can see

that the ADM demodulator is comprised by sampling, slope controller, level detect

algorithm, integrator and low-pass filter. The slope controller and the level detect algorithm

comprise a quantization level adjuster, which can control the gain of the integrator in the delta

demodulator. Since the gain of the integrator will affect the distortion of the recovered signal,

and the gain of

the integrator is controlled by the quantization level adjuster, therefore, in order to obtain the

recovered signal with low distortion, we need to design a good quantization level adjuster.

The main objective of the design of ADM is to reduce the slope overload effect.

On the other words, that means when the slope of the input signal is too large, then the ADM

will increase the quantization level (Δ), which can reduce the slope overload effect. Besides,

when the variation of the input signal is slow, the ADM will decrease the quantization level to

reduce the error. Therefore, ADM is an technique which utilize s the increment of the

dynamic range of quantization level to reduce the signal distortion.

Figure 10-1 Block diagram of ADM demodulator

2. The Implementation of ADM Demodulator

Figure 10-2 is the basic circuit of ADM demodulator. The modulated ADM signal is inputted

from the D-type flip-flop, which the D-type flip-flop is the sampler. After that the output

signal of the flip-flop will be

ADM

I/P Sampling Quantization Level

Adjuster

Integrator Audio

O/P

CLK

I/P

sent into the tunable amplifier and level adjuster. The objective is to change the gain of

the tunable amplifier according to the difference between the input signal x(t) and the

reference signal Xs(t). If the difference between the input signal and the reference signal

is very large, then the level adjuster will change the gain of the tunable amplifier so

that the value of Δ(t) will become large. On the other hand, if the difference between the

input signal and the reference signal is very small, then the level adjuster will reduce the

gain of the tunable amplifier so that the value of Δ(t) will become small. With this

advantage, when the frequency variat ion of the input signal is large, then we can

increase the value of Δ(t) to prevent the occurrence of slope overload. And when the

frequency variat ion of the input signal is small, then we can decrease the value of Δ(t)

to reduce the error. Therefore, finally, we can obtain the recovered signal, which is

similar to the original signal at the integrator.

Figure 10-2 Basic circuit diagram of CVSD demodulator.

Figure 10-3 Circuit diagram of adaptive delta demodulator.

Figure 10-3 is part of the circuit diagram of ADM demodulator. The main reason is

the circuit diagram in figure 10-3 is similar to the circuit diagram of delta demodulator

in chapter 8, therefore, please refer to chapter 8 for the operation theory of this circuit.

In this chapter, we are mainly discussed the auto controlled of Δ(t) value. Since the

ADM modulator is the modification of delta modulator, which is used to improve the

occurrence of slope overload. And then the slope-controlled circuit is related to the gain

of the integrator and the gain of the integrator is re lated to the analog switch. The reason

is the channels of the analog switch are related to the resistors R4 to R7 whether series

with resistor R8 or not. At the same time, the switching of channels of the analog

switch is controlled by the pin A and pin B.

Therefore, as similar to chapter 9, we will focus on the implementation of the controlled

circuit of the Δ(t) value by adding the circuit to pin A and. pin B.

Figure 10-4(a) is the controlled circuit of Δ(t) value. In figure 10 -4(a), UI is

the inverter. U5 and U6 comprise a synchronous counter, however, the CLK of the

flip-flop is positive edge trigger and the CLK of the counter is negative edge trigger.

Therefore, in order to synchronize the flip-flop and the counter, we need to add an

inverter. Connect the point A and point B in figure 10-4(a) to the point A and point B

of the analog switch in figure 10-3. Since by changing the values of point A and point B, we

can change the gain of the integrator, and then we can also change the magnitude of

the period between the output slope of the integrator and the output of the delta

modulator. Figure 10-4(b) is the output signal waveforms of each test points. Test point A

is the modulated ADM signal; test point B is the output signal waveform of Q of U5,

which will operate with test point A by "exclusion OR" (XOR), i.e. D = A +

(U5)Q .Asa result of the circuit in figure 10-4(a) utilize synchronous counter as the

pulse detector and latch, so, the results of test point C and test point F will be similar to

each others. Test point G is the "AND" between test point D and test point E. When

the test point G is zero, the counter will reset. At this moment, the output of the

counter is zero and refer to the integrator in figure 10-3, the gain will be

Av = R11

R4+R5+R6+R7+R8 (10-1)

When A:B = 01, the gain is

Av = R11

R5+R6+R7+R8(10-2)

When A:B = 10, the gain is

Av = R11

R6+R7+R8 (10-3)

When A:B = 11, the gain is

Av = R11

R7+R8 (10-4)

Figure 10-4(a) Circuit diagram of auto gain controller.

Figure 10-4(b) Output signal waveforms of each test point of the auto gain controller.

Figure 10-4 Circuit diagram and output signal waveforms of the auto gain controller.

From the above-mentioned equations, we know that when the value of the counter

become larger, the gain of the integrator also become larger. If the output value of the

counter is larger than 3 but not yet reset to zero, then the counter will load the outpu t

value into the counter, which means the increment will always maximum. The counter

will only reset until the pin CLR is "LOW". With this method, we can achieve the auto gain

control of the integrator. The different between the delta modulator and adaptive delta

modulator is that the gain of the integrator of the delta modulator is fixed. However, the

adaptive delta modulator will change the gain of the integrator according to the modulated

signal in present and past. In this chapter, the counter that we use is a 2-bits counter,

therefore, there are only 4 variations of the increment values. In order to obtain more

increment values, we just need to change the counter and the analog switch.

10-3 : Experiment Items

Experiment 1: Adaptive Delta Demodulator

1. To implement a adaptive delta modulator circuit as shown in figure 9 -3 or refer to

figure DCT9-1 on GOTT DCT-6000-05 module to produce the modulated delta signal.

At the audio signal input port (Audio I/P), input a 1 V amplitude and 500 Hz sine wave

frequency. Next at the CLK input port (CLK I/P), input a 5 V amplitude and 64 kHz

TTL signal.

2. To implement a adaptive delta demodulator circuit as shown in figure 10-3 or refer to

figure DCT 10-1 on GOTT DCT-6000-05 module.

3. Connect the modulated delta signal (ADM O/P) in figure DCT9-1 to the input

port (ADM I/P) of the adaptive delta demodulator in figure DCTI0-1. At the CLK

input port (CLK I/P) of the adapt ive delta demodulator, input a 5 V amplitude and 64

kHz TTL signal. Then by using oscilloscope, observe on the output signal waveforms of

sampling signal output port (TP1), unipolar-to-bipolar (TP2), the gain selection A

(TP3), the output port of slope controller (TP5), the input port of low-pass filter (TP6)

and the output port of audio signal (Audio O/P). Finally, record the measured results in

table 10-1.

4. According to the input signals in table 10-1, repeat step 3 and record the

measured results in table 10-1.

5. To implement a adaptive delta modulator circuit as shown in figure 9-3 or refer to

figure DCT9-1 on GOTT DCT-6000-05 module to produce the modulated delta signal. At

the audio signal input port (Audio I/P), input a 1 V amplitude and 500 Hz sine wave

frequency. Next at the CLK input port (CLK I/P), input a 5 V amplitude and 256 kHz TTL

signal.

6. Connect the modulated delta signal (ADM O/P) in figure DCT9-1 to the input

port (ADM I/P) of the adaptive delta demodulator in figure DCT10-1. At the CLK input

port (CLK I/P) of the adaptive delta demodulator, input a 5 V amplitude and 256 kHz

TTL signal. Then by using oscilloscope, observe on the output signal waveforms of TP1, TP2,

TP3, TP5, TP6 and Audio O/P. Finally, record the measured results in table 10-2.

7. According to the input signals in table 10-2, repeat step 6 and record the

measured results in table 10-2.

10-4 : Measured Results

Table 10-1 Measured results of ADM demodulator with 64 kHz CLK signal.

Input Signals of ADM

Modulator

Output Signal Waveforms

500 Hz

1 V

TP1 TP2

TP3 TP5

TP6

Audio O/P

Table 10-1 Measured results of ADM demodulator with 64 kHz CLK signal.

(continue)

Input Signals of ADM

Modulator

Output Signal Waveforms

1 kHz

1 V

TP1 TP2

TP3 TP5

TP6

Audio O/P

Table 10-2 Measured results of ADM demodulator with 256 kHz CLK signal.

Input Signals of ADM

Modulator

Output Signal Waveforms

500 Hz

1 V

TP1 TP2

TP3 TP5

TP6

Audio O/P

Table 10-2 Measured results of ADM demodulator with 256 kHz CLK signal.

(continue)

Input Signals of ADM

Modulator

Output Signal Waveforms

1 kHz

1 V

TP1 TP2

TP3 TP5

TP6

Audio O/P

10-5 : Problem Discussion

1. If the sampling frequency is being increased or decreased, explain the affect of the

demodulator at the output port.

2. Refer to figure 10-3, explain the functions of the integrator.

3. Refer to figure 10-4, explain how the circuit achieve auto gain control.