Chapter 10: 68HC11 Serial Peripheral Interface

H. Huang Transparency No.10-1

The 68HC11 Microcontroller

Chapter 10: 68HC11 Serial Peripheral Interface


Han-Way Huang

Minnesota State University, Mankato



Why SPI?

- The number of I/O port pins are limited on an 8-bit microcontroller.- It is desirable to implement more I/O functions on the same number of port pins.- Many I/O devices do not require high speed.- SPI allows more I/O functions to be supported on the 68HC11.

A Summary of the 68HC11 SPI System

- Two types of devices are involved in data transfer in the SPI format: master and slaves- Multiple SPI compliant devices can be interconnected- The master device initiates data transfer and also generates the clock signal required for data transfer synchronization- The 68HC11 SPI is often used for I/O port expansion, and interfacing with peripheral devices such as LED/LCD display drivers, phase-locked loop chips, A/D and D/A converters, serial EEPROMs, serial SRAMs, etc.



SPI Pins

- SS/PD5: slave select- SCK/PD4: serial clock- MOSI/PD3: master out slave in- MISO/PD2: slave out master in



SPIE: SPI interrupt enableSPE: SPI enableDWOM: port D wired-or mode selectMSTR: SPI master or slave selectCPOL: clock polarity. 1: SCK idle high, 0: SCK idle lowCPHA: SCK clock phase. Control the clock-data relationships

between the master and slave. CPHA and CPOL must be used together. See Figure 9.1.

SPR1 & SPR0: SPI clock rate select

SPI-Related Registers

1. The Serial Peripheral Control Register (SPCR)

SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0

7 6 5 4 3 2 1 0 SPCRlocated at$1028

0 0 0 0 0 1 u uValue after

reset

u = undefined

SPR1 SPR0 E divided by

0011

0101

24

1632



SS

SCK(CPOL = 0, CPHA = 0)

(CPOL = 0, CPHA = 1)



MISO/MOSI

MSB LSB

Internal strobe for data capture (all modes)

Figure 10.1 SPI data clock timing diagram (Redrawn with permission of Motorola)



Serial Peripheral Status Register (SPSR)

Port D Data Direction Register (DDRD)

SPIF WCOL 0 MODF 0 0 0 0

7 6 5 4 3 2 1 0 SPSRlocated at$1029

0 0 0 0 0 0 0 0Value after

reset

0 0 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

7 6 5 4 3 2 1 0 DDRDlocated at$1009

0 0 0 0 0 0 0 0Value after

reset

Controlled pin SS SCK MOSI MISO TxD RxD

0 = input1 = output



SPI Circuit Connection

1. Single master single slave

8-bit shift register 8-bit shift register

+5V

SS SS

Figure 10.2 SPI master-slave interconnection

Master Slave

SPI clockgenerator

MOSI MOSI

MISO MISO

SCK SCK



2. SPI Single master and multiple slaves circuit connection I

- The SPI master can selectively exchange data with any slave.- By disconnecting the MISO pin, the master can output data to one or multiple slaves at

the same time.

SS

+5V

MOSI SCK MISO SS

Shiftregister

MOSI SCK MISO SS

Shiftregister

MOSI SCK MISO

Shiftregister

SS

SPI Master(68HC11)

SCK

MOSI

MISO

PB0

PB1

PBk

.

.

.

.

.

.

. . .

Slave 0 Slave 1 Slave k

Shiftregister

Figure 10.3 Single-master and multiple-slave device connection (method 1)



3. SPI Single master and multiple slaves circuit connection II

- All slaves are connected into a large shift register chain.- The master cannot selectively exchange data with a single slave.

SS

+5V

MOSI SCK MISO SS

Shiftregister

MOSI SCK MISO SS

Shiftregister

MOSI SCK MISO

Shiftregister

SS

SPI Master(68HC11)

SCK

MOSI

MISO

. . .

Slave 0 Slave 1 Slave k

Figure 10.4 Single-master and multiple-slave device connection (method 2)

. . .



SPI Data Transfer

1. The procedure

- An SPI transfer is initiated by writing data to the shift register in the master SPI device.- Data is circuited 8 bit positions; thus data is exchange between the master and the slave.- The master SPI device sends out 8 pulses from the SCK pin to synchronize data transfer.- After 8 bits have been transferred, the SPIF flag of the SPSR register will be set to 1.

2. Error conditions

- write collision: a write is performed during an SPI data transfer. The write will be unsuccessful and the WCOL bit of the SPSR register will be set to 1.

- mode fault: the SS input of a master is asserted low. The SPI master that has a modefault will:

(1) generate an SPI interrupt if SPIE = 1(2) clear SPE flag to disable the SPI(3) clear the MSTR bit forcing itself into the slave mode(4) force the DDRD bits to zeros for the four SPI pins.



3. The program to transfer data from the master to a slave

regbas equ $1000 ; base address of the I/O register blockSPDR equ $2A ; offset of SPDR from regbasSPCR equ $28 ; offset of SPCR from regbasSPSR equ $29 ; offset of SPSR from regbasDDRD equ $09 ; offset of DDRD from regbasSPI_DIR equ $38 ; value to set SS, SCK and MOSI pins for output and MISO for inputSPI_INI equ $54 ; value to initialize the SPI which will enable SPI, disable SPI* ; interrupt, configure port D pins as normal CMOS pins, select* ; master mode, choose the falling edge of SCK to shift data, and* ; sets data rate to 1 Mbits/sec at 2 MHz E clock

ORG $00data RMB $10 ; a data buffer

.

.ldx #regbasldaa #SPI_DIRstaa DDRD,X ; set port D directionsldaa #SPI_INIstaa SPCR,X ; initialize the SPI operation parametersldaa datastaa SPDR,X ; start SPI transfer

wait ldab SPSR,X ; wait for data to be sent outbpl wait ; “..



3. The program to read data from a slave

ldx #regbasldaa #SPI_DIRstaa DDRD,Xldaa #SPI_INIstaa SPCR,Xstaa SPDR,X ; start an SPI transfer

here ldab SPSR,X ; wait until 8 bits have been shifted inbpl here ; “ldaa SPDR,X ; place the byte in A...



Simulating the SPI

If data is shifted on the falling edge of the clock signal:

Step 1: Set the clock to high.Step 2: Apply the data bit on the port pin that is connected to the serial data input pin of the

peripheral device.Step 3. Pull the clock to low.Step 4. Repeat steps 1 to 3 for as many times as needed.

If the rising edge is used to shift data, then

- set clock to low in step 1- set clock to high in step 3



Shift register HC589

Q H

9

Shiftregister

S A

A

BCD

E

FG

HLatch clock

Shift clock

Serial-shift/Parallel-loadOutput enable

Figure 10.5 HC589 block diagram and pin assignment

Data latch

14

1512

3

4

56

7

12

11

13

10

V CC = Pin 16GND = Pin 8



HC589 Operation

1. The parallel data inputs (A,…,H) will be loaded into the data latch on the rising edge of the latch clock.

2. When the serial shift/parallel load signal is low, the data in the data latch will be loadedinto the shift register. Otherwise, the shift register is enabled to shift.

3. When the shift register is enabled to shift, the serial data input SA will be shifted into the shift register and the data on stage H will be shifted out from pin QH.

4. The output enable signal (pin 10) must be low in order for data at stage H be driven outfrom pin QH.

Application of HC589

- to expand the number of parallel input ports of 8-bit microcontrollers.- convert parallel data into serial format



Interfacing the HC589 to the SPI

Method 1.

...

LC LC LCOE OE OE

Q H Q H Q HS A S A S A

A-H A-H A-H

SC SC SC

SS/PL SS/PL SS/PL

HC589 0 HC589 1 HC589 k

MISO

SCK

TxD

SS

68HC11

Figure 10.6 Serial connection of multiple HC589s to an SPI

SC: shift clockLC: latch clockSS/PL: serial shift/parallel load mode selectOE: output enable



Method I (continued)

procedure for data transfer:

Step 1. Program the DDRD register to configure SCK, TxD, and SS pins for output andthe MISO pin for input.

Step 2. Program the SPCR register to enable the SPI function and set up other parameters.Step 3. Set the LC pin to low and then pull it to high; this will load the external data into

the data latch in parallel.Step 4. Set the SS pin to low to select the parallel load mode, which will load the contents

of the data latch into the shift register.Step 5. Set the SS pin to high to select the serial shift mode.Step 6. Write a byte into the SPDR register to trigger eight SCK clock pulses to shift in

8 bits.Step 7. Repeat step 6 as many times as needed, and save the data in a buffer.



Example 10.1 Write a program to input 8 bytes from 8 external HC589s connected as shownin Figure 10.6 and store the data at locations $00-$07.Solution:Configure the SS, SCK, MOSI, and TxD pins for output and MISO and RxD pins for input --write the value %00111010 ($3A) into DDRD.

Write the value %01010000 ($50) into the SPCR register to:

1. disable SPI interrupt2. enable the SPI3. set port D pins for normal CMOS output pins (not open drain)4. use the rising edge of the SCK signal to shift data5. select a 1-Mbits/sec data rate

regbas equ $1000PORTD equ $08DDRD equ $09SPCR equ $28SPSR equ $29SPDR equ $2A SPCR_INI equ $50SPI_DIR equ $3A



org $C000ldx #regbasldaa #SPI_DIRstaa DDRD,X ; configure SPI pin directionsldaa #SPCR_INIstaa SPCR,X ; initialize SPI operation parameters

* The following two instructions load data into HC589s in parallelbclr PORTD,X $02 ; pull TxD (LC) to lowbset PORTD,X $02 ; pull TxD (LC) to high

bclr PORTD,X $20 ; pull SS pin to low to select parallel load mode and load ; the contents of the data latch into the shift register

bset PORTD,X $20 ; pull SS pin to high to select serial shift modeldab #8 ; loop count for transferring 8 bytesldy #$0000 ; set Y to point to the buffer

loop staa SPDR,X ; trigger SPI data transferbrclr SPSR,X $80 * ; wait until 8 bits have been shiftedldaa SPDR,X ; get one bytestaa 0,Y ; save the datadecb ; decrement loop countbne loopend



In C language,

#include <hc11.h>main ( ){

char buffer[8], i;DDRD = 0x3A; /* configure port D pins directions */SPCR = 0x50; /* configure SPI parameters */PORDT &= 0xFD; /* create a rising edge on the TxD pin */PORTD |= 0x02; /* to load data into data latch */PORTD &= 0xDF; /* transfer data from data latch to shift register */PORTD |= 0x20; /* select serial shift mode */for (i = 0; i < 8; i++) {

SPDR = 0x00; /* shift data in from the MISO pin */while (!(SPSR & 0x80)); /* wait for data to shift in */buffer [i] = SPDR;

}return 0;

}



Interfacing the HC589 to the SPI -- Method II

...

LC LC LC

OE OE OE

Q H Q H Q H S A

A-H A-H A-H

SC SC SC

SS/PL SS/PL SS/PL

HC589 0 HC589 1 HC589 kMISO

SCK

TxD

SS

68HC11

Figure 10.7 Serial connection of multiple HC589s to an SPI

PB0PB1

PBk

.

...

SC: shift clockLC: latch clockSS/PL: serial shift /parallel load mode selectOE: output enable



Procedure for data transfer (method II)

Step 1. Program the DDRD register to set the directions of the MISO, SCK, SS, and TxD pins.Step 2. Program the SPCR register to configure the SPI operation parameters.Step 3. Set the TxD pin to low and then pull it to high to load external data into the data latch

in parallel.Step 4. Set the SS pin to low to select the parallel load mode, which will load the contents of

the data latch into the shift register.Step 5. Pull the SS pin to high to select the serial shift mode.Step 6. Set the port B that controls the specified HC589 to low to enable the shift register to

output serial data. The remaining port B pins are set to high.Step 7. Write a byte into the SPDR register to trigger eight pulses from the SCK pin to shift

in the serial data. The external data is now in the SPDR register and ready for use.Step 8. Repeat steps 6 and 7 as many times as needed.



Shift Register HC595

Shiftregister

Q A

Q BQ C

Q D

Q E

Q FQ G

Q H

Latch

SQ H

15

13

1234567

912

10

11

A 14

Reset

LC

OE

SC

Figure 10.8 HC595 block diagram and pin assignment

VCC = Pin 16GND = Pin 8



HC595 Operation

- The shift register accepts serial data and provides a serial output. - The serial data input (A) is shifted into the shift register on the rising edge of the shift clock.- The data in the shift register will be loaded into the output latch on the rising edge of the

latch clock.- A low on the output enable pin allows data from the latch to be presented at the output

pins QA-QH. - The serial output SQH does not have tri-state capability.- Multiple HC595s can be cascaded to expand the number of parallel output ports for

the 68HC11.



Interfacing HC595 to the SPI -- Method I

MOSI A SQ H A SQ H A SQ H

SCK

SS

Reset

68HC11

SC SC

LC LC LC

SC

Reset Reset Reset

OE OE OE

8

Q A -Q H

8

Q A -Q H

8

Q A -Q H

Figure 10.9 Serial connection of multiple HC595s to the SPI

From reset circuit



Method I (continued)

Data transfer procedure

Step 1. Program the DDRD register to configure SPI pin directions.Step 2. Program the SPCR register to set up appropriate SPI operating parameters.Step 3. Write a byte into the SPDR register to trigger eight pulses from the SCK pin.Step 4. Repeat step 3 as many times as needed.Step 5. Set the SS pin to low and then pull it to high to transfer the byte in the shift

register into the output latch. After this step, the output latch contains validdata.

Example 9.2 Write a program to output three bytes to the first three HC595s in Figure 9.8.Solution:regbas equ $1000PORTD equ $08DDRD equ $09SPCR equ $28SPDR equ $2ASPSR equ $29



SPI_DIR equ $3A ; value to configure SPI pin directionsSPCR_IN equ $50 ; value to enables SPI, disables SPI interrupt, chooses rising * ; edge of SCK to shift data, selects normal port D pins, * ; and sets data rate to 1 Mbits/sec.K equ 3

org $00buffer fcb $11,$22,$33

org $C000ldx #regbasldaa #SPI_DIRstaa DDRD,X ; configure pins SS, MOSI, SCK, and TxD for outputldaa #SPCR_INstaa SPCR,X ; configure SPI operation parametersldab #K ; set up loop countldy #buffer ; set Y as a pointer to the buffer

ch_loop ldaa 0,Y ; send out one byte via SPI functionstaa SPDR,X ; “brclr SPSR,X $80 * ; wait until the byte is shifted outiny ; move the buffer pointerdecb ; decrement the loop countbne ch_loopbclr PORTD,X $20 ; create a rising edge on SS pin to load data into output bset PORTD,X $20 ; latchend



Interfacing the HC595 to the SPI -- Method II

MOSI A SQ H A SQ H A SQ H

SCK

Reset

68HC11

SC SC

LC LC LC

SC

Reset Reset Reset

OE OE OE

8

Q A -Q H

8

Q A -Q H

8

Q A -Q H

Figure 10.10 Parallel connection of multiple HC595s to the SPI

From reset circuit

.

.

.

PB0

PB1

PBk

HC595 0 HC595 1 HC595 k

...



Method II:

Data transfer procedure

Step 1. Program the DDRD register to set up SPI pin directions.Step 2. Program the SPCR register to enable the SPI subsystem, select the data rate, select

the rising edge of SCK signal for data shifting, select master mode, and disableinterrupt.

Step 3. Write a byte into SPDR to trigger SPI data transfer.Step 4. Set the PBi pin to low and then pull it to high to load the byte from the shift register

of the HC595 i into its output latch.



The Seven-Segment Display Driver Chip MC14489

24-1/2-stage shift register

BitGrabberDisplay Register

(24 Bits)

4 4 4 4 4

4 4 4 4 4

Nibble Mux &Decoder ROM

7 a to g h Dim/Bright

Anode Drivers(Current Sources)

D

C

BitGrabberConfiguration Register

(8bits)

Oscillator &Control Logic

Bank Switches(FETs)

POR

blank 55

9 13 15 16 17

bank1 bank2 bank3 bank4 bank5

7 6 5 4 2 1 20 19

a b c d e f g h

DataOut

18

8 R X

Pin 3 = V DDPin 14 = V SS

Data In 12

Clock 11

Enable 10

Figure 10.11 MC14489 multi-character LED driver (Redrawn with permissionof Motorola)

4

4



MC14489 Pins

Data In: A serial data input pin.Clock: The rising edge of this signal is used to shift data into the shift register. The

highest shift clock frequency is 4 MHz.Enable: External data can be entered when this signal is low. The data are loaded from the

shift register into the latches on the rising edge of this signal.a thru h: Seven-segment outputs for driving seven segments and decimal point LEDs.

Bank 1..5: Digit select pins. The MC14489 can drive up to five seven-segment displays, butonly one seven-segment display is lighted at any time. The display to be lighted is selected by these pins.

Rx: External current-setting resistor. The relationship between the segment current andRx is shown in Figure 10.12.



35

30

25

20

15

10

5400 800 1.2K 1.6K 2.0K 2.4K 2.8K 3.2K 3.6K 4.0K

Figure 10.12 a through h nominal current vs. R X (Redrawn withpermission of Motorola)

5 V supplyBit D23 = 1 (brighten LEDs)

With D23 = 0, i OH is cut by ~50%

i OH

pea

k cu

rren

t (m

A)

RX, external resistor ( )



The MC14489 Operation

- The configuration register controls the MC14489 operation.- Two operation modes: hex mode and special decode. The decode function is

shown in Table 10.1.- Displays can be made dimmer or brighter by clearing or setting the first bit of

the display data sent to the MC14489.

C7 C6 C5 C4 C3 C2 C1 C0

C7: when set to 0, no decode; when set to 1, special decode. (refer to C5-C4)C6: when set to 0, no decode; when set to 1, special decode. (refer to C3-C1)C5: bank 5 control. L= hex decode, H = depends on C7C4: bank 4 control. L= hex decode, H = depends on C7C3: bank 3 control. L= hex decode, H = depends on C6C2: bank 2 control. L= hex decode, H = depends on C6C1: bank 1 control. L= hex decode, H = depends on C6C0: L = low power mode (blanks the display), forced by power-on reset. H = normal mode

Figure 10.13 The MC14489 Configuration register

7 6 5 4 3 2 1 0

See Table 10.3



Tabl

e 10

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ripl

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Seg

men

t Dec

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Fun

ctio

n Ta

ble

(Red

raw

n w

ith

perm

issi

on o

f M

otor

ola)

Lam

p C

ondi

tion

s

No

Dec

ode

(inv

oked

via

bits

C1

to C

7)17-

segm

ent D

ispl

ayC

hara

cter

s

Hex

Dec

ode

(inv

oked

via

bits

C1

to C

5)

Spe

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Dec

ode

(Inv

oked

via

bits

C1

to C

7)

Ban

k N

ibbl

e V

alue

Hex

B

inar

yM

SB

LS

B

$00

0

0

0

$10

0

0

1

$20

0

1

0

$30

0

1

1

$40

1

0

0

$50

1

0

1

$60

1

1

0

$70

1

1

1

$81

0

0

0

$91

0

0

1

$A1

0

1

0

$B1

0

1

11

1

0

0$C $D

1 1

0

1

$E1

1

1

0

$F1

1

1

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dc

ba



Interfacing the MC14489 to the 68HC11 SPI

abcdefgh

8

8 8 8 8 8

Bank 5Bank 4Bank 3Bank 2Bank 1

+5V

Data In

Clock

Enable

MOSI

SCK

SS

68HC11

MC14489

3.6K R X

V DD

V SS

Figure 10.14 68HC11 driving five 7-segment displays using an MC14489



- One byte of configuration information and 3 bytes of display data must be sent to the MC14489 in Figure 10.14.

- The 4 most significant bits control the brightness and display of h segments asshown in Figure 10.15.

D23 D22 D21 D20

0 0 0 = all h outputs inactive

0 0 1 = activate h in bank 10 1 0 = activate h in bank 2

0 1 1 = activate h in bank 3

1 0 0 = activate h in bank 4

1 0 1 = activate h in bank 51 1 0 = activate h in both banks 1 and 2

1 1 1 = activate h in all banks

L = dim LEDs, H = brighten LEDs

Figure 10.15 Use of the most significant 4 bits of the display data



Example 10.3 Write a program to display 997.04 from bank 5 to bank 1 in Figure 10.14. Usethe normal brightness to display these five digits.Solution: The control byte to be written into the configuration register is as follows:bit 7: no decode, set to 0bit 6: no decode, set to 0bit 5: bank 5 hex decode, set to 0bit 4: bank 4 hex decode, set to 0bit 3: bank 3 hex decode, set to 0bit 2: bank 2 hex decode, set to 0bit 1: bank 1 hex decode, set to 0

The display data format is

40799

set the h segment of bank 3 (digit 7 in this case)

brighten LEDs

Figure 10.16 Display data for example 10.3

1 0 1 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 0 1 0 0



The Configuration of SPCR register:

bit 7 (SPIE): set to 0 to disable interruptbit 6 (SPE): set to 1 to enable SPI functionbit 5 (DWOM): set to 0 to choose normal port D pinsbit 4 (MSTR): set to 1 to select master modebit 3 & 2 (CPOL & CPHA): set to 00 to use rising edge to shift data outbit 1 & 0 (SPR1 & SPR0): set to 00 to choose 1 MHz shift rate

regbas equ $1000PORTD equ $08DDRD equ $09SPCR equ $28SPDR equ $2ASPSR equ $29SP_DIR equ $3A ; value to configure SPI pins directionsSPCR_IN equ $50 ; value to set up the specified SPI operation parameters



ORG $00disp_dat FCB $B9,$97,$04

ORG $C000LDX #regbasLDAA #SP_DIRSTAA DDRD,X ; configure SPI pin directionsLDAA #SPCR_INSTAA SPCR,X ; initialize the SPI parametersBCLR PORTD,X $20 ; enable data shifting to MC14489LDAA #$01STAA SPDR,X ; send out configuration data to MC14489BRCLR SPSR,X $80 * ; wait until configuration data has been shifted outBSET PORTD,X $20 ; latch data into configuration registerBCLR PORTD,X $20 ; enable SPI data transfer to MC14489LDY #disp_datLDAB #3

loop LDAA 0,YSTAA SPDR,X BRCLR SPSR,X $80 *INYDECBBNE loopBSET PORTD,X $20 ; load data into display data registerEND



A C Program for Sending Data to MC14489


int i;unsigned char disp_dat[3] = {0xB9, 0x97, 0x04};DDRD = 0x3A;SPCR = 0x50;PORTD &= 0xDF; /* enable SPI data transfer to MC14489 */SPDR = 0x01; /* send out configuration data */while (!(SPSR & 0x80)); /* wait until data have been shifted out */PORTD |= 0x20 /* load data into configuration register */PORTD &= 0xDF; /* enable SPI transfer to MC14489 */for (i = 0; i < 3; i++) {

SPDR = disp_dat [i];while (!(SPSR & 0x80));

}PORTD |= 0x20;

} /* load data into display data register */



Cascading MC14489s

- Connect the Data Out pin of one MC14489 to the Data In pin of the next MC14489.- To configure n MC14489s, we need to send out 3 × (n -1) + 1 bytes of data

to the MC14489s. Only n bytes are used to configure the MC14489s.- A circuit of cascading three MC14489s is illustrated in Figure 10.17.

68HC11Data

In Clock EnableDataOut

MC14489 # 1

DataIn Clock Enable

DataOut

MC14489 # 2

DataIn Clock Enable

DataOut

MC14489 # 3

MOSI

SCK

SS

bank 1tobank 5

a to hbank 1tobank 5

a to hbank 1tobank 5

a to h

Figure 10.17 Cascading three MC14489s



Example 10.8 Write a program to display the following information (temperature at14:20 of Aug. 2nd, 1999) on the 15 seven-segment displays driven by three MC14489s as shown in Figure 10.17:

30.5oC 14 20 08 02 99

Solution:

- Use the special decode of character F to represent the character for degree.- Represent all other characters using normal decode method.- The left-most five digits are displayed by the MC14489 #1.- The middle five digits are displayed by the MC14489 #2.- The right-most five digits are displayed by the MC14489 #3.

Three bytes of configuration data must be sent to three MC14489s:

1st byte 2ndbyte

3rd byte 4th byte 5th byte 6th byte 7th byte (last)

Time

Configurationregisterof device #3



Figure 10.18 Configuration information for three cascaded MC14489s

don't caredon't care don't caredon't care



Configurations of three MC14489s

MC14489 #1:

C7: set to 0 to select no decodeC6: set to 1 to select special decode (display degree character on bank 2)C5..C3: set to 0 to select hex decodeC2: set to 1 to select special decodeC1: set to 0 to select hex decodeC0: set to 1 to select normal mode

MC14489 #2 & #3:

C7 & C6: set to 0 to select no decodeC5..C1: set to 0 to select hex decodeC0: set to 1 to select normal mode

- The configuration data for the MC14489 #3 should be sent out first.- The complete configuration data is 01xxxx01xxxx45, where x strands for don’t

care and should be set to 0.



Display Data for MC14489 #1

1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 0

C552set the h segment of bank 4 digit 5

brighten LEDs

Figure 10.19 Display data for leftmost MC14489


1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

0021all h segments inactive

brighten LEDs

Figure 10.20 Display data for the middle MC14489

0


1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1

9208all h segments inactive

brighten LEDs

Figure 10.21 Display data for the rightmost MC14489

9



REGBAS EQU $1000SPSR EQU $29SPDR EQU $2ASPCR EQU $28PORTD EQU $08DDRD EQU $09

ORG $C000LDX #REGBASLDAA #$3ASTAA DDRD,X ; configure SPI pin directionsLDAA #$50STAA SPCR,X ; configure SPI parametersLDAB #7BCLR PORTD,X $20 ; enable SPI transfer to MC14489sLDY #conf_dat ; set Y to point to configuration data

loop1 LDAA 0,YSTAA SPDR,XBRCLR SPSR,X $80 * ; wait until a byte has been shifted outINYDECBBNE loop1BSET PORTD,X $20 ; load data into configuration registers



BCLR PORTD,X $20 ; enable SPI transfer to MC14489sLDY #disp_datLDAB #9

loop2 LDAA 0,YSTAA SPDR,XBRCLR SPSR,X $80 *INYDECBBNE loop2BSET PORTD,X $20 ; load data into display data register… ; do something else

conf_dat DB $01,$00,$00,$01,$00,$00,$45disp_dat DB $88,$02,$99,$81,$20,$00,$C2,$55,$FC



In C language


int i;unsigned char conf_dat [ ] = {0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x45};unsigned char disp_dat [ ] ={0x88, 0x02, 0x99, 0x81, 0x20, 0x00, 0xC2, 0x55, 0xFC};DDRD = 0x3A;SPCR = 0x50;PORTD &= 0xDF; /* enable SPI transfer to MC14489s */for (i = 0; i < 7; i++) {

SPDR = conf_dat[i];while (!(SPSR & 0x80));

}PORTD |= 0x20; /* load data into configuration registers */PORTD &= 0xDF; /* enable SPI transfer to MC14489s */for (i = 0; i < 9; i++) {

SPDR = disp_dat [i];while (!(SPSR 7 0x80));

}PORTD |= 0x20; /* load data into display data registers */return 0;

}



Liquid Crystal Displays (LCDs)

- LCDs are often multiplexed to save connection pins.- Motorola has LCD drivers that drives 1/4 multiplexing LCDs.- In a 1/4 multiplexing LCD, each character is represented by a multiple of four segments.- An LCD display that displays BCD digit consists of seven segments and an optional

decimal point.- An LCD segment is turned on and off by controlling the backplane and frontplane voltages.- Each BCD digit is controlled by two frontplane and four backplane signals.- There is no standard for backplane and frontplane connections on multiplexed LCD displays.

BP1 BP1

BP2

BP3

BP4

BP2

BP3

BP4

a

b

c

d

e

fg

h

a

b

c

d

e

fg

h

(b) Frontplane(a) Backplane

Figure 10.22 LCD backplane and frontplane connections

FP1 FP2FP1 FP1

BP1BP2BP3BP4

fged

abch

*Because there is no standard for backplaneand frontplane connections on multiplexeddisplays, this truth table can be used only forthe connection shown in Figure 10.22.

Table 10.2 LCD segment truth table *



The MC145000 and MC145001 LCD drivers

Bit 1

Bit 48

48-b

it S

hift

Reg

iste

r Bit 1

Bit 48

48-b

it L

atch

Fro

ntpl

ane

Dri

ve C

ircu

it

SystemClock Circuit

Back-planeDrive

Circuit

V/3 GeneratorCircuit

V DD /3

2V DD /3

BP1BP2BP3BP4

FP1FP2FP3FP4FP5FP6FP7FP8FP9FP10FP11FP12

Data Out

DataClock

DataIn*

OSC IN OSC OU

T

Frame-SyncOut

*Data-clock and data-in can be driven to voltagesgreater than V DD .

Figure 10.23 Block diagram of the MC145000 (master ) LCD driver (Redrawn with permission of Motorola)



48-b

it S

hift

Reg

iste

r

48-b

it L

atch

Fro

ntpl

ane

Dri

ve C

ircu

it

SystemClock Circuit

V/3 Generator

FP1FP2FP3FP4FP5FP6FP7FP8FP9FP10FP11

Data Out

DataClock

DataIn*

OSC IN Frame-SyncIn

*Data-clock and data-in can be driven to voltagesgreater than V DD .

Figure 10.24 Block diagram of the MC145001 (slave ) LCD driver (Redrawn with permission of Motorola)



Operation of the MC145000

- Display data bits are shifted in on the falling edge of the data clock.- Data in the shift register are loaded into the 48-bit latch at the beginning of each frame

period.- The frame period is the time during which all the LCD segments are set to the desired on

or off states. - The data in the shift register of the LCD driver is loaded into the latch that drives the

frontplane outputs when the frame-sync pulse is high.- New data should not be shifted in in this period to avoid flicker.- Backplane waveforms are invariant.- The frontplane and backplane waveforms, FPn and BPn, are generated using the system

clock and voltages from the V/3 generator circuit.- Examples on backplane and frontplane waveforms are given in Figure 10.26, 10.27.

Operation of the MC145001

- This unit consists of the same circuitry as the master unit, with two exceptions: it has nobackplane driver circuitry, and its shift register and latch hold 44 bits.



System clock(oscillator ÷ 256)

Frame-sync pulse

Figure 10.25 The relationship between the system clock and the frame-sync pulse



Systemclock

V DD

0 V

V DD

0 V

Frame-syncpulse

BP1

V DD

0 V

2/3V DD

1/3V DD

BP2

V DD

0 V

2/3V DD

1/3V DD

BP3

V DD

0 V

2/3V DD

1/3V DD

BP4

V DD

0 V

2/3V DD

1/3V DD

Figure 10.26 Backplane waveform



(a) Frontplane waveform of an on f segment and d, e, g to be off

(b) Voltage waveform of an on segment across segment f (BP1 - FP1)

(c) All segments OFF Frontplane waveform (FP2) for segments a, b,c, and h to be off

(d) OFF segment voltage waveform across segment b (BP2 - FP2)

V DD

2/3V DD

1/3V DD

0 V

V DD

2/3V DD

1/3V DD

0 V

-1/3V DD

-2/3V DD

- V DD

2/3V DD

1/3V DD

1/3V DD

0 V

-1/3V DD

Figure 10.27 Examples of frontplane waveforms and segment voltage waveforms



Clock Signal Issue

- OSCin is the input to the system clock circuit.- OSCout is the system clock output generated by the master unit.- The OSCout signal from the master unit is connected to the OSCin input of all slave units

to synchronize updating of display data.- The oscillator frequency can be obtained from an external oscillator or by connecting an

resistor between OSCin and OSCout.- The relationship between oscillator frequency and resistor value is shown in Figure 10.29.



1K 10K 100K 1M 10M

100K

1M

10M

Figure 10.29 Typical oscillator frequency vs. external resistance value

V DD = 3VV DD = 6V

Oscillator frequency (Hz)

Ext

erna

l res

isto

r va

lue

()



LCD display pattern

- The LCD controller multiplexes four bits to drive the same frontplane output pin.- The master unit also activates the corresponding backplane output to turn segments on

and off.- The bit locations (in the latch) that control the master unit LCD segments located at each

frontplane-backplane intersection are shown in Table 10.3.- The order for shifting the segment patterns into the LCD driver is a, b, c, d, e, f, g, and h.- The hexadecimal representation of BCD digits LCD display patterns are shown in

Table 10.3.

Frontplanes

FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12

BP1BP2BP3BP4

Bac

kpla

nes

4321

8765

1211109

16151413

20191817

24232221

28272625

32313029

36353433

40393837

44434241

48474645

Table 10.3 Bit locations for controlling the LCD segments



Digit a b c h f g e d

Segment Hexdecimalrepresentation

0123456789ABCDEF

1011010111100000

1111100111101100

1101111111101100

0000000000000000

1000111011111100

0011111011100010

1010001010111100

1011011010000100

$EB$60$C7$E5$6C$AD$2F$E0$EF$EC$EE$0A$6A$6B$04$00

Table 10.4a BCD digits display patterns (without decimal point)

Digit a b c h f g e d

Segment Hexdecimalrepresentation

0123456789ABCDEF

1011010111100000

1111100111101100

1101111111101100

1111111111111111

1000111011111100

0011111011100010

1010001010111100

1011011010000100

$FB$70$D7$F5$7C$BD$3F$F0$FF$FC$FE$1A$7A$7B$14$10

Table 10.4b BCD digits display patterns (with decimal point)



LCD driver system configuration- One master and one or multiple slave LCD drivers can be cascaded when more than six

digits are to be displayed (shown in Figure 10.30).- Data are shifted serially first into the master unit and then into the following slave units

on the falling edge of the common data clock.- At the beginning of each frame period, the master unit generates a frame-sync pulse to

synchronize to the master unit’s backplane drive circuit.- The master unit generates the backplane signals for all the LCD digits in the system.

MC145000Master LCD

Driver

MC145001Slave LCD

Driver

MC145001Slave LCD

Driver

LCD Array

Oscillator

Data Clock

OSC INOSC OUT

R ext(optional)

Serial Data In

4 Backplanes

Dataout

Dataout

Datain

Datain

Frame Sync.

System Clock

OSC INOSC IN

12 Frontplanes 11 Frontplanes 11 Frontplanes

Figure 10.30 Frontplane and backplane connections to a multiplexed-by-four seven-segment (plus decimal point) LCD (Redrawn with permission of Motorola)



An LCD from LXD -- part #69

60

1

31

30Figure 10.31 Block diagram of the eight-digit multiplexed LCD display from LXD inc.



- The backplane signal BP1 is assigned to pins 60 and 59.- The backplane signal BP2 is assigned to pins 32 and 31.- The backplane signal BP3 is assigned to pins 1 and 2.- The backplane signal BP4 is assigned to pins 29 and 30.- Ai, Bi, Ci, Di, Ei, Fi, Gi, and DP stand for the segments and decimal point of the ith digit.- A pin associated with some segment letter is a frontplane pin.- Up to 8 digits can be displayed using this LCD.

PADBP1BP2BP3BP4BP1BP2BP3BP4PAD

60BP1

----------

BP3--1

59BP1

----------

BP3--2

58--------

F8G8E8D83

57A8B8C8DPF8G8E8D84

56A8B8C8DP--------5

55A7B7C7DPF7G7E7D76

54A7B7C7DPF7G7E7D77

53----------------8

52A6B6C6DP--------9

51A6B6C6DPF6G6E6D610

50--------

F6G6E6D611

49A5B5C5DP--------12

48A5B5C5DP--------13

47--------F5G5E5D514

46--------

F5G5E5D515

45A4B4C4DP--------16

44A4B4C4DP--------17

43--------

F4G4E4D418

42--------

F4G4E4D419

39--------

F3G3E3D322

38--------F3G3E3D323

41A3B3C3DP--------20

40A3B3C3DP--------21



35----------------26



32--

BP2----------

BP429

31--

BP2----------

BP430

Figure 10.32 Pin assignment of the eight-digit multiplexed LCD from LXD Inc.



Using an MC145000 and an eight-digit LCD from LXD to display 6 digits

- The 1 M resistance sets the oscillator frequency to 24 KHz.- The system frequency is obtained by dividing the previous frequency by 256 and is

94 Hz.

OSC IN OSC OUTData in

Data clock

BP4BP3BP2BP1

FP12 FP11

FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1

52 10 49 14 45 18 41 22 37 24 34 2760

31

1

30

MOSI

SCK

68HC11

1.0 M (for 94 Hz system clock)*

* The oscillator frequency is 256 times the system clock frequency or 24 KHz

Figure 10.33 68HC11 SPI drives six-digit LCD display



Example 10.5 Write a program to display 123456 on the LCD in Figure 10.33.Solution:- Configure pins SS, MOSI, SCK, and Tx for output and the other port D pins for input.- Configure the SPI to operate with the following parameters:

1. SPI interrupt disabled2. SPI function enabled3. normal port D pins4. master mode5. shifting data using the falling edge of the SCK signal6. 1 Mbits/sec data rate

Write the value $54 into the SPCR register

- Send 48 0s to the LCD driver to clear the LCD digits.



regbas EQU $1000 ; base address of I/O register blockDDRD EQU $09 ; offset of DDRD from regbasSPCR EQU $28 ; offset of SPCR from regbasSPSR EQU $29 ; offset of SPSR from regbasSPDR EQU $2A ; offset of SPDR from regbasDD_INI EQU $3A ; value to set the DDRD registerSPCR_INI EQU $54 ; value to be written into the SPCR register

ORG $00digits FCB 1,2,3,4,5,6 ; digits to be displayedlp_cnt RMB 1 ; loop count

ORG $C000LDS #$3F ; set up stack pointer for EVB computerLDX #regbasLDAA #DD_INISTAA DDRD,X ; configure port D pin directionsLDAA #SPCR_INISTAA SPCR,X ; configure SPCR register

* The following 6 instructions send out 6 0’s to clear LCDsLDAB #6

loop CLRASTAA SPDR,XBRCLR SPSR,X $80 * ; wait for 8 bits to be shifted outDECBBNE loop



LDY #digits ; point Y to the start of the digit tableLDAB #6STAB lp_cnt ; initialize the loop count

loop1 LDAB 0,Y ; get the digit to be displayedPSHY ; save Y in the stackLDY #lcdndp ; place LCD pattern table address in YABY ; index into the LCD pattern tableLDAA 0,Y ; get the LCD pattern from the tableSTAA SPDR,X ; send out the digit patternBRCLR SPSR,X $80 * ; wait until the digit pattern has been shifted outPULY ; restore the value of Y from the stackINY ; move the digit pointerDEC lp_cnt ; decrement the loop countBNE loop1...

* The following lines contain the LCD display patterns of hexadecimal digitslcdndp FCB $EB,$60,$C7,$E5,$6C,$AD,$2F,$E0,$EF,$EC

FCB $EE,$0A,$6A,$6B,$04,$00END



In C Language,


int i;char digits [ ] = {1, 2, 3, 4, 5, 6};hex_pat [ ] = {0xEB, 0x60, 0xC7, 0xE5, 0x6C, 0xAd, 0x2F, 0xE0, 0xEF, 0xEC,

0xEE, 0x0A, 0x6A, 0x6B, 0x04, 0x00};DDRD = 0x3A; /* configure SPI pin directions */SPCR = 0x54; /* configure SPCR register */for (i = 0; i < 6; i++) { /* send out 0s to blank the screen */

SPDR = 0;while (!(SPSR & 0x80));

}for (i = 0; i < 6; i++) { /* send out digits 1..6 */

SPDR = hex_pat [digits [i]];while (!(SPSR & 0x80));

}return 0;

}



The MC68HC68T1 Real-Time Clock with Serial Interface

Features:

- Full clock features -- seconds, minutes, hours (AM/PM), day-of-week, date, month, year,auto leap year

- 32 bytes general-purpose RAM for saving critical data- power control functions -- sensing power transition, performing power up and power

down- burst mode for reading/writing successive addresses in clock/RAM- selectable crystal or 50/60 Hz line input frequency- clock registers utilize BCD data- watchdog circuit similar to COP- battery backup power supply input



68HC68T1 signals

CLK OUT: buffered clock output; 7 selectable frequencies.

CPUR: CPU reset.INT: interrupt. Activated when one of the

following occurs:1. power failure2. preset alarm time occurs.3. periodic interrupt

SCK: serial clock for data shifting. Either therising or falling edge can be used for datashifting.

MOSI: master in slave outMISO: master in slave outSS: slave selectPSE: power supply enablePOR: power on resetLINE: line sense.XTAL IN, XTAL OUT: crystal input/output

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CLK OUT

CPUR

INT

SCK

MOSI

MISO

SS

V SS

V DD

XTAL OUT

XTAL IN

V BATT

V SYS

LINE

POR

PSE

Figure 10.34 The MC68HC68T1



On-Chip RAM and Registers

- 32 bytes of on-chip RAM and 13 registers- to access these RAM and registers, the CPU first sends in an 8-bit address and then

performs the actual access- Each read/writable register and each RAM byte has two addresses: one for read and one

for write- The address map of these registers and RAM bytes are shown in Figure 10.35.- All timer counters and alarm registers are in BCD format (shown in Table 10.5).

Address Location

Read Write Function

Decimalrange

BCD datarange

BCD dataexample

$20$21$22

$23$24$25$26N/AN/AN/A

$A0$A1$A2

$A3$A4$A5$A6$A8$A9$AA

secondsminutes

hours (12-hour mode)

hours (24-hour mode)day of week (Sunday = 1)

date of monthmonth (January = 1)

yearseconds alarmminutes alarm

hours alarm (12-hour mode)

hours alarm (24-hour mode)

0-590-591-12

0-231-7

1-311-120-990-590-591-12

0-23

00-5900-59

81-92 (AM)A1-B2 (PM)

00-2301-0701-3101-1200-9900-5900-59

01-12 (AM)21-32 (PM)

00-23

214090

1003160687214010

10

Table 10.5 Clock/calendar and alarm data modes (Redrawn with permission of Motorola)



secondsminuteshoursday of the weekdate of the monthmonthyearnot usednot usednot usednot usednot usednot usednot usednot usednot usedstatus registerclock control registerinterrupt control register

$20$21$22$23$24$25$26$27$28$29$2A$2B$2C$2D$2E$2F$30$31$32

secondsminuteshoursday of the weekdate of the monthmonthyearnot usedseconds alarmminutes alarmhours alarmnot usednot usednot usednot usednot usednot usedclock control registerinterrupt control register

$A0$A1$A2$A3$A4$A5$A6$A7$A8$A9$AA$AB$AC$AD$AE$AF$B0$B1$B2

$32

$33

32 bytes general-purpose

RAM

read addresses only

Clock/Calendarread addresses only

Not used

32 bytes general-purpose

RAM

write addresses only

Clock/Calendarwrite addresses only

$00

through

$1F

$20

through

through

$7F

$80

through

$9F

$A0

through

$B2

Figure 10.35 MC68HC68T1 RAM and register address map (Redrawn withpermission of Motorola)



Clock Control Register

Start/stop: a 1 enables the counter stages of the clock circuitryLine/XTAL: a 1 selects 50/60 Hz Line input to update the timeXTAL Select: select crystal frequencies.

0 = 4.194304 MHz1 = 2.097152 MHz2 = 1.048576 MHz

3 = 32.768 MHz50 Hz/60 Hz: A 1 selects 50 Hz for line input. Otherwise, 60 Hz is selected.CLK OUT2-CLK OUT0: specify one of the seven frequencies to be used as the square wave

output at the CLK OUT pin.0 = Xtal1 = Xtal/22 = Xtal/43 = Xtal/84 = disable5 = 1 Hz6 = 2 Hz7 = 50/60 Hz for Line operation, 64 Hz for Xtal operation

Start Line

XtalStop

XtalSelct

1

XtalSelct

0

50 Hz

60 Hz

CLKOUT

2

CLKOUT

1

CLKOUT

0



Interrupt Control Register

Watch dog: When set to 1, the watchdog function is enabled.Power down: When set to 1, a power down operation is initiated.Power sense: When set to 1, this bit enables the Line input pin to sense a power failure.Alarm: When set to 1, the alarm function is enabled. When the alarm time is reached, the interrupt output is activatedPeriodic select: The frequency of the periodic output is selected by these four bits.

Watchdog

Powerdown Alarm

Powersense Periodic select

D7 D6 D5 D4 D3 D2 D1 D0



D3-D0value (hex)

Periodic interruptoutput frequency

Frequency timebase

Xtal Line

0123456

789ABCDEF

disable2048 Hz1024 Hz512 Hz256 Hz128 Hz64 Hz50 or 60 Hz32 Hz16 Hz8 Hz4 Hz2 Hz1 Hz1 cycle per minute1 cycle per hour1 cycle per day

xxxxxx

xxxxxxxxx

x

xxxxx

Table 10.7 Periodic interrupt output frequencies (at INT pin)



Status Register

Watchdog. Set to 1 when a CPU failure is detected.First time up. Set to 1 by a power on reset.Interrupt true. Set to 1 when one of the three interrupts is valid.Power sense INT. Set to 1 when the power sense circuit generates an interruptAlarm INT. Set to 1 when the contents of the seconds, minutes, and hours time

time counters and alarm latches are equal.Clock INT. Set to 1 on a periodic interrupt.

0 Watchdog

0Firsttimeup

Inter-rupttrue

PowersenseINT

AlarmINT

ClockINT

D7 D6 D5 D4 D3 D2 D1 D0



Interfacing the 68HC68T1 to the 68HC11

- The corresponding pins of the 68HC11 and 68HC68T1 are connected together.

- A battery is added to the 68HC68T1 sothat important information can be keptwhen the line power is interrupted.

- An alarm transducer is added and willbe ringing at 4 KHz to remind the userthat the preset alarm time has reached.

- Only the timer function is used.- A 32.67 KHz crystal oscillator is used to

generate the clock signal to be used by the 68HC68T1.

- Data transfer to/from the 68HC68T1 canoccur one byte at a time or in multi-byte burst mode.

- Each read or write cycle causes clock/calendar register or RAM addressto automatically increment by 1.

SCK

MOSI

MISO

SS

IRQ

SCK

MOSI

MISO

SS5 V

3.3 K

INT

68HC68T1

Alarmtransducer

CX-1V32.760KHz

22 pF

22 M

150 K

CLK OUT

XTAL IN

XTAL OUT

V DDR charg

e

3.6 V3 NiCd

Cells 0.1 F

68HC11

V BATT

5 V

Figure 10.37 Circuit connections between a 68HC11 and a 68HC68T1 for theclock function

64



Constant definition for the programming of 68HC68T1

regbas equ $1000SPDR equ $2ASPCR equ $28SPSR equ $29DDRD equ $09PORTD equ $08ram_addr equ $80 ; starting address to write the RAMsecond_r equ $20 ; read address for secondsminute_r equ $21 ; read address for minuteshour_r equ $22 ; read address for hoursday_wk_r equ $23 ; read address for day of weekdate_m_r equ $24 ; read address for date of monthmonth_r equ $25 ; read address for monthyear_r equ $26 ; read address for yearstat_reg equ $30 ; read address for status registerclk_ctlr equ $31 ; read address for clock control registerint_ctlr equ $32 ; read address for interrupt control registersecond_w equ $A0 ; write address for secondsminute_w equ $A1 ; write address for minuteshour_w equ $A2 ; write address for hoursday_wk_w equ $A3 ; write address for day of week



date_m_w equ $A4 ; write address for date of monthmonth_w equ $A5 ; write address for monthyear_w equ $A6 ; write address for years_alarm equ $A8 ; write address for seconds alarmm_alarm equ $A9 ; write address for minutes alarmh_year equ $AA ; write address for hours alarmclk_ctlw equ $B1 ; write address for clock control registerint_ctlw equ $B2 ; write address for interrupt control register



The initialization of the SPI function

- Configure pins SS, CLK, MOSI, TxD for output and MISO and RxD for input. Writethe value %00111010 into the DDRD register.

- Choose the following SPI operating parameters:

1. disable SPI interrupt2. enable SPI function3. port D normal CMOS pins4. master mode5. rising edge of CLK for shifting data6. 1 Mbits/sec data shifting rate

Write the value $50 into the SPCR register.

The instruction sequence to initialization the SPI system:

ldx #regbasldaa #$3Astaa DDRD,Xldaa #$50staa SPCR,X



Data transfer to and from the 68HC68T1- Set the SS signal to high during the data transfer process.- Send the time of day information (7 bytes) and alarm information (3 bytes) in two separate

burst mode transfer because these two blocks of information are not in contiguous addresses.- Reserve 10 bytes in SRAM of the 68HC11 to hold time-of-day and alarm information.

* The following instruction sequence sends the time-of-day information to the 68HC68T1org $00

clk_mgt rmb 10 ; block of memory to store time-of-day and alarm informationorg $C000ldx #regbasbset PORTD,X $20 ; enable data transfer to the 68HC68T1ldaa #second_wstaa SPDR,X ; send the write address of seconds to the 68HC68T1brclr SPSR,X $80 * ; wait until the byte is shifted outldab #7 ; use accumulator B as the loop countldy #clk_mgt ; Y points to the base address of time-of-day information

LP1 ldaa 0,Ystaa SPDR,X ; send out one byte information to the 68HC68T1brclr SPSR,X $80 * ; wait until the byte is shifted outinydecbbne LP1bclr PORTD,X $20 ; disable SPI transfer to the 68HC68T1



* The following instruction sequence sends out the alarm information to the 68HC68T1bset PORTD,X $20 ; enable SPI transfer to the 68HC68T1ldaa #s_alarmstaa SPDR,X ; send out seconds alarm addressbrclr SPSR,X $80 * ; wait until the address has been shifted outldab #3 ; use accumulator B as the loop countldy #clk_mgt+7 ; Y points to the alarm information block

LP2 ldaa 0,Ystaa SPDR,X ; send out one byte of alarm informationbrclr SPSR,X $80 * ; wait until the byte is shifted outiny ; move to the next bytedecb ; decrement the loop countbne LP2bclr PORTD,X $20 ; disable SPI transfer to the 68HC68T1

* The following instruction sequence reads the status register of the 68HC68T1bset PORTD,X $20 ; enable data transfer from the 68HC68T1ldaa #stat_regstaa SPDR,X ; send out the address of the status registerbrclr SPSR,X $80 * ; wait until the address byte is shifted outstaa SPDR,X ; start an SPI transfer to read the status registerbrclr SPSR,X $80 * ; wait until the status register is shifted inldaa SPDR,X ; place the status register in accumulator Abclr PORTD,X $20 ; disable SPI transfer to the 68HC68T1



Clock/Calendar portion

- consists of a long string of counters that are toggled by a 1-Hz input that can be derivedfrom one of the three sources:

1. an external crystal oscillator applied between pins XTAL IN and XTAL OUT2. an external frequency source applied to XTAL IN3. a 50- or 60-Hz source connected to the LINE input

- an AM/PM indicator is available; once set, it toggles at 12:00 AM and 12:00 PM.



Alarm operation

- the alarm latches consist of seconds, minutes, and hours registers.- when the contents of alarm latches equal the values of the seconds, minutes, and hours

time counters, an interrupt is generated.- the CLK OUT can be used to drive an alarm transducer.- the procedure for using the alarm function is as follows:

1. disable CLK OUT when the alarm time has not been reached.2. enable the alarm interrupt.3. when the alarm time is reached, the alarm interrupt-service routine enables a pulse

output from the CLK OUT pin for some specific amount of time.

- the alarm interrupt should be enabled and its procedure is:

1. enable the periodic interrupt of the 68HC68T12. set up the alarm time and then set up the alarm counter. The alarm counter is used

to keep track of the amount of time that the alarm transducer has been turned on.3. stay in a wait loop while checking if the alarm counter has been decremented to 0.

If yes, turn off the alarm and reinitialize the alarm counter.



Alarm interrupt service routine

1. checks the cause of the interrupt by reading the status register2. returns if the interrupt is periodic and the alarm is not turned on.3. turns on the alarm transducer if the interrupt is caused by the alarm function.4. decrement the alarm count by 1 and then returns if the interrupt is caused by periodic

interrupt and the alarm transducer is on.

The interrupt control register should be set up as follows for this application:

- disable watchdog interrupt (clear bit 7)- disable power down (clear bit 6)- disable power sense (clear bit 5)- enable alarm interrupt (set bit 4 to 1)- set the periodic interrupt frequency to be 1 Hz (set bits 3-0 to 1100)

The value %00011100 should be written into the interrupt control register.



The clock control and interrupt control registers can be initialized by using the burst mode:

ldx #regbasbset PORTD,X $20 ; enable data transfer to the 68HC68T1ldaa #clk_ctlwstaa SPDR,X ; send the write address of the clock control registerbrclr SPSR,X $80 * ; wait until the address is shifted outldaa #$B4 ; disable CLK OUT when alarm time has not reachedstaa SPDR,X ; send out the clock control byte

first_bt brclr SPSR,X $80 first_bt ; wait until the clock control byte is shifted outldaa #$1Cstaa SPDR,X ; send out the interrupt control byte

sec_bt brclr SPSR,X $80 sec_bt ; wait until the interrupt control byte is shifted outbclr PORTD,X $20 ; disable data transfer to the 68HC68T1

A flag is needed to indicate whether the alarm transducer has been turned on. The alarmcounter and the alarm flag can be set up as follows:

threemin equ 180 ; let the alarm transducer be turned on for three minutesalarmcnt rmb 1 ; memory location to store the alarm countalarmflg rmb 1 ; memory location used as alarm flagset_alct ldaa #threemin

staa alarmcnt ; initialize alarm count to 180clr alarmflg ; clear the alarm flag



Clock interrupt service routineclk_ISR ldx #regbas

bset PORTD,X $20 ; enable SPI transfer to the 68HC68T1ldaa #stat_regstaa SPDR,Xbrclr SPSR,X $80 * ; wait until the address has been shifted outstaa SPDR,X ; trigger an SPI transfer to read the status registerbrclr SPSR,X $80 * ; wait until the status register has been shifted inbclr PORTD,X $20 ; disable SPI transferbset PORTD,X $20 ; re-enable SPI transfer so that new address can be sent outldaa SPDR,X ; place the status register in Aanda #$02 ; check the alarm interrupt bitbeq periodic ; if interrupt is periodic go and check if the alarm flag is setldaa #clk_ctlw ; send out the write address of the clock control registerstaa SPDR,X ; “brclr SPSR,X $80 * ; wait until the address has been shifted outldaa #%10110011 ; send a new control byte to the clock control register to turnstaa SPDR,X ; on CLK OUTbrclr SPSR,X $80 * ; wait until the new control byte is shifted outldaa #1staa alarmflg ; set the alarm flagbra exit ; prepare to return from interrupt



periodic ldaa alarmflg ; check the alarm flagbeq exit ; return if the alarm is not turned ondec alarmcnt ; decrement the alarm count if the alarm has been turned onbne exit ; if alarm is not zero then return

* disable CLK OUT, reinitialize the alarm count and clear the alarm flag when alarm count * has been decremented to 0

ldaa #threeminstaa alarmcntclr alarmflg ; clear the alarm flag

* To disable CLK OUT, write the value %10110100 into the clock control registerldaa #clk_ctlwstaa SPDR,X ; send the write address to the 68HC68T1brclr SPSR,X $80 * ; wait until the address has been shifted outldaa #$B4staa SPDR,X ; send out the new clock control bytebrclr SPSR,X $80 * ; wait until the new clock control byte has been shifted out

exit bclr PORTD,X $20 ; disable SPI transfer to the 68HC68T1rti



Example 10.6 For the circuit in Figure 10.37, write a C function to send the current time-of-day and alarm time information to the 68HC68T1. This function must also enable the 68HC68T1 to generate periodic and alarm interrupt to the 68HC11.Solution:

#define second_w 0xA0 /* seconds write address */#define s_alarm 0xA8 /* write address for seconds alarm */#define ccr_wad /* clock-control register write address */

init_68HC68T1 (char spi_dir, char spr_ctrl, char t_of_d [ ], char alarm, char ccon [ ]){

int i;DDRD = spi_dir; /* set up SPI pin diriections */SPCR = spr_ctrl; /* initialize SPI parameters */PORTD |= 0x20; /* enable SPI transfer to the 68HC68T1 */SPDR = second_w; /* send the write address for seconds */while (!(SPSR & 0x80)); /* wait until the byte is shifted out */for (i = 0; i < 7; i+) {

SPDR = t_of_d [i]; /* send the current time to 68HC68T1 */while (!(SPSR & 0x80));

}



PORTD &= 0xDF; /* disable SPI transfer so that new address can be sent */PORTD |= 0x20; /* enable SPI transfer to the 68HC68T1 */SPDR = s_alarm; /* send the second alarm address to the 68HC68T1 */while (!(SPSR & 0x80));for (i = 0; i < 3; i++) {

SPDR = alarm [i]; /* send new alarm time to the 68HC68T1 */while (!(SPSR & 0x80));

}PORTD &= 0xDF;PORTD |= 0x20; /* enable SPI transfer to the 68HC68T1 */SPDR = ccr_wad; /* send write address of clock control register */while (!(SPSR & 0x80));for (i = 0; i < 2; i++) { /* send out clock and interrupt control info. */

SPDR = ccon[i];while (!(SPSR 0x80));

}PORTD &= 0xDF;

}



Example 10.7 Write a main program and an interrupt service routine for the 68HC68T1.The main program sets up the IRQ interrupt vector, calls the function in Example 10.6 toinitialize the 68HC68T1, sets up alarm count, clears alarm flag, and enable the interrupt.The IRQ interrupt service routine will perform the operations described earlier. This programis to be run on the EVB, the EVBU, or the CMD-11A8 demo board.Solution:

#include <hc11.h>#define stat_reg 0x30 /* read address of the status register */unsigned char alarm_cnt, alarm_flg;unsigned char t_of_d [7], alarm [3], ccon [2];void IRQ_ISR ( );main ( ){

alarm_cnt = 180;alarm_flg = 0;./* read the current time-of-day and alarm time here */.ccon[0] = 0xB4; /* clock control byte */ccon[1] = 0x1C; /* interrupt control byte */init_68HC68T1 (0x3A, 0x50, t_of_d [ ], alarm [ ], ccon [ ]);



*(unsigned char *)0xee = 0x7E; /* set up IRQ interrupt jump vector */*(void (**)())0xef = IRQ_ISR;INTR_ON ( );./* do something else */.return 0;

}#pragma interrupt_handler IRQ_ISR ( );void IRQ_ISR ( ){/* read the status register to identify the cause of interrupt */

PORTD |= 0x20; /* enable SPI transfer to the 68HC68T1 */SPDR = stat_reg; /* send out status register read address */while (!(SPSR & 0X80));SPDR = 0x00; /* read the status register */while (!(SPSR & 0x80));PORTD &= 0xDF; /* disable SPI transfer */if (SPDR & 0x20) { /* interrupt is caused by alarm time */

PORTD |= 0x20; /* enable SPI transfer to the 68HC68T1 */SPDR = ccr_wad; /* send out the clock-control register write address */while (!(SPSR & 0x80));SPDR = 0xB3; /* turn on alarm device */



while (!(SPSR &0x80));alarm_flg = 1; /* set this flag to indicate that alarm is turned on */PORTD &= 0xDF; /* disable SPI transfer to 68HC68T1 */return;

}if (!alarm_flg)

return; /* interrupt is caused by periodic interrupt and alarm is not on */-- alarm_cnt;if (alarm_cnt)

return;else {

alarm_cnt = 180;alarm_flg = 0;PORTD |= 0x20;SPDR = clk_ctlw; /* send clock-control register write address */while (!(SPSR & 0X80));SPDR = 0xB4; /* turn off alarm */while (!(SPSR & 0x80));PORTD &= 0xDF;return;

}}



Other functions of the 68HC68T1 chip

1. Power sensing: - the voltage level on the LINE input pin is check- as long as the voltage is either higher or lower than a certain threshold around VDD,

a power failure is indicated.- the 68HC68T1 may interrupt the CPU on a power failure for the CPU to take

appropriate actions

2. Power-down:- power down is initiated by the processor - signals PSE, CLK OUT, and CPUR output will be placed low during a power-down- procedure of power down is as follows:

a. set the power sense operation (set bit 5 of the interrupt control register)b. when interrupt occurs, the processor reads the status register to determine the interrupt

source.c. if a power failure is sensed, the processor does the necessary housekeeping to prepare

for shutdown.d. the CPU reads the status register again after several milliseconds to determine the

validity of the power failure.e. the CPU sets power down and disable all interrupts when the power failure is verified.f. when the power returns and Vsys rises above Vbatt + 0.7V, power up is initiated. The

CPU reset is released and serial communication is established.



3. Power-up

- Power-up is started when the signal POR goes high- If the Vsys input also goes high, then 68HC68T1 initiates the power-up operation by placing

PSE, CLK OUT, and CPUR to high so that the CPU can start to boot.

4. Watchdog function

- when enabled, the SS pin must be toggled at regular intervals without a serial transfer.- if the SS pin is not toggled, the 68HC68T1 supplies a CPU reset pulse at the CPUR pin

and the watchdog bit in the status register is set to 1.- the watchdog service time and CPU reset period (CPUR low) is listed in Table 9.8.

Service time (ms)Reset time (ms)

50 Hz

maximumminimum

--20

1040

60 Hz

maximumminimum

XTAL

maximumminimum

--16.7

8.333.3

--15.6

7.831.3

Table 10.8 Watchdog service and reset time

Documents

Chapter 10: 68HC11 Serial Peripheral Interface