Chapter 1

Introduction to Digital VLSI Systems Design

Evolution of VLSI Systems

Category Date Density (gates)

Single transistor 1959 1

device

Logic gate 1960 1

Small Scale Integration (SSI) 1964 Up

to 10

Medium Scale Integration (MSI) 1967 10

- 100

Large Scale Integration (LSI) 1972

100 - 1000

Very Large Scale Integration (VLSI) 1978

1000 – 10000

Ultra Large Scale Integration (ULSI) 1989

10000 & above

SLI/SOC Late 90s > 10 Million

Applications of VLSI Systems

• Digital cameras

• Digital camcorders

• Digital camera interface

• Digital cinema

• Digital Display

• Digital TV and Digital cable TV

• Digitizer for analog NTSC/PAL/SECAM

cameras

• Display interface

• Mobile Phone

• FAX machine

• PDA

• Scanner

• Anti-lock brakes

• Automatic transmission

• Cruise control

• Global positioning system for automobiles

• Electro cardiograph

• Life-support systems

• MRI/CT scan

• LCD projector

• Low cost computer

• Mobile phone personal computers

• Scan pen and PC notes taker

• Automated baggage clearance system in

airports

• Avionic systems

• Flight simulator

• Instrument landing system

• Ship controls

• Driverless shuttle

• Cruise controls

• Traffic Controller

• Washing machine

• Petrol/Diesel dispenser

• Demodulator for satellite communication

• Encryption/decryption

• Network card

• Network switches/routers

• Quadrature amplitude modulator (QAM) and

demodulator

• Wireless LAN/WAN

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Digital System Design using FPGAs

1. Formulate the detailed product specification.

2. Develop the detailed hardware architecture.

3. Code the architecture in a hardware design

language such as Verilog or VHDL.

4. Compile and simulate the design and, verify

the functionality.

5. Synthesize to map on to a target FPGA device

and optimize the logic.

6. Run the Place and Route tool for creating bit

stream of the design application.

7. Program the bit stream generated in step 6 in a

serial EPROM.

8. Design and fabricate the printed circuit board

to accommodate the FPGA, the serial EPROM

and other components required for the end

application.

9. Solder the components and test the populated

FPGA board using the development system,

logic analyzer, pattern generator, etc.

10. Download the application bit stream from the

development system or the on-board serial

EPROM and verify the system functionality.

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Virtex FPGAs

Densities from 50K to 1M gates

System performance up to 200 MHz

66-MHz PCI Compliant I/Os

Built-in clock-management circuitry

Four dedicated delay-locked loops (DLLs) for

advanced clock control

Four primary low-skew global clock

distribution nets, plus 24 secondary local clock

nets

Hierarchical memory system

LUTs configurable as

16-bit RAM

32-bit RAM

16-bit dual-ported RAM or 16-bit Shift

Register

Configurable synchronous dual-ported 4K-bit

RAMs

Fast interfaces to external high-performance

RAMs

Flexible architecture that balances speed and

density

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input functions

Abundant registers with clock enable and, dual

synchronous/asynchronous set and reset

Internal Tri-state bussing

IEEE 1149.1 boundary-scan logic

Die-temperature sensor diode

Supported by FPGA Development Systems

Wide selection of PC and workstation

platforms

SRAM based in-system configuration

Unlimited re-programmability

Four programming modes

0.22 μm 5-layer metal process

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Virtex FPGA Architecture

Virtex Field Programmable Gate Arrays

(Courtesy of Xilinx Inc.)

Virtex FPGA Architecture (Courtesy of

Xilinx Inc.)

• Dedicated block memories of 4096 bits each

• Clock DLLs for clock-distribution delay

compensation and clock domain control

• Tri-state buffers (BUFTs) associated with each

CLB

_____________________________________________________________

Configurable Logic Block

Two-Slice Virtex CLB (Courtesy of Xilinx Inc.)

Detailed View of Virtex Slice (Courtesy of Xilinx Inc.)

Virtex Block Select RAM Bits

(Courtesy of Xilinx Inc.)

Input/Output Block

Virtex Input/Output Block (IOB)

(Courtesy of Xilinx Inc.)

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Summary of Spartan-3 FPGA Attributes

(Courtesy of Xilinx Inc.)

Notes:

1. Logic Cell = 4-input Look-Up Table (LUT)

plus a ‘D’ flip-flop. “Equivalent Logic Cells”

equals “Total CLBs” x 8 Logic Cells/CLB x

1.125 effectiveness.

2. These devices are available in Xilinx

Automotive versions as described in DS314:

Spartan-3 Automotive XA FPGA Family.

3. These devices are available in lower static power versions as described in DS313: Spartan-3L Low Power FPGA Family.

Number of RAM Blocks by Device

(Courtesy of Xilinx Inc.)

Features

• Low-cost, high-performance logic solution for

high-volume, consumer-oriented applications

- Densities up to 74,880 logic cells (5 million

gates)

• Select IO signaling

- Up to 784 I/O pins

- 622 Mb/s data transfer rate per I/O

- 18 single-ended signal standards

- 8 differential I/O standards

- Signal swing ranging from 1.14V to 3.45V

- Double Data Rate (DDR) support

- DDR, SDRAM support up to 333 Mbps

• Logic resources

- Abundant logic cells with shift register

capability

- Wide, fast multiplexers

- Fast look-ahead carry logic

- Dedicated 18 x 18 multipliers

- JTAG logic compatible with IEEE 1149.1/1532

• Select RAM hierarchical memory

- Up to 1,872 Kbits of total block RAM

- Up to 520 Kbits of total distributed RAM

• Digital Clock Manager (up to four DCMs)

- Clock skew elimination

- Frequency synthesis

- High resolution phase shifting

• Eight global clock lines and abundant routing

• Fully supported by Xilinx ISE development

system

- Synthesis, mapping, placement and routing

• Low-power Spartan-3L Family and Automotive

Spartan-3 XA Family variants

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Spartan-3 FPGA Architectural Overview

Configuration

Spartan-3 Family Architecture

(Courtesy of Xilinx Inc.)

Arrangement of Slices within the CLB

(Courtesy of Xilinx Inc.)

Simplified diagram of the Left Hand Side

SLICEM

(Courtesy of Xilinx Inc.)

Notes:

1. Options to invert signal polarity as well as other

options that enable lines for various functions are

not shown.

2. The index i can be 6, 7 or 8 depending on the

slice. In this position, the upper right-hand slice

has an F8MUX, and the upper left-hand slice has

an F7MUX. The lower right-hand and left-hand

slice has an F6MUX.

Simplified IOB Diagram (Courtesy of Xilinx Inc.)

Configurable Logic Blocks Overview

Arrangement of Slices within the CLB

(Courtesy of Xilinx Inc.)

Diagram of SLICEM (Courtesy of Xilinx Inc.)

Diagram of SLICEL (Courtesy of Xilinx Inc.)

Logic Resources in a CLB

Slices LUTs Flip -

Flops MULT_ANDs Arithmetic & Carry-

Chains

DistributedRAM(1)

4 8 8 8 2 64 bits

Virtex-4 Logic Resources Available in all

CLBs (Courtesy of Xilinx Inc.)

Block RAMs

Xilinx FPGA Product Selector (Continued)

(Courtesy of Xilinx Inc.)

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FLEX 10K Series EPLDs

The industry’s first embedded programmable

logic device (PLD) family, providing System-on-

a-Programmable-Chip (SOPC) integration

– Embedded array for implementing mega-functions, such as efficient memory and specialized logic functions

– Logic array for general logic functions

High density

– 10,000 to 250,000 typical gates

– Up to 40,960 RAM bits; 2,048 bits per embedded array block (EAB), all of which can be used without reducing logic capacity

System-level features

– Multi-volt I/O interface support

– 5 V tolerant input pins

– Low power consumption (< 0.5 mA typical in standby mode)

– FLEX 10K and FLEX 10KA devices support PCI bus

– FLEX 10KA devices include pull-up clamping diode, selectable on a pin-by-pin basis for 3.3 V PCI compliance

– Select FLEX 10KA devices support 5 V PCI buses

– Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 without consuming any device logic

– Devices are fabricated on advanced processes and operate with a 3.3 V or 5 V supply voltage

– In-circuit re-configurability via external configuration device, intelligent controller, or JTAG port

– Clock Lock and Clock Boost options for reduced clock delay/skew and clock multiplication

Flexible interconnect

– Fast track

Interconnect continuous routing structure for fast,

predictable interconnect delays

– Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators

– Dedicated cascade chain that implements high-speed, high-fan-in logic functions

– Tri-state emulation that implements internal tri-state buses

– Up to six global clock signals

– Individual tri-state output enable control for each pin

– Open-drain option on each I/O pin

– Programmable output slew-rate control to reduce switching noise

– FLEX 10KA devices support hot-socketing

Peripheral register for fast setup and clock-to-

output delay

– Available in a variety of packages with 84 to 600 pins

– Pin-compatibility with other FLEX 10K devices in the same package

Software design support and automatic place-

and-route provided by development systems for

Windows-based PCs, Sun SPARC station and HP

9000 Series 700/800 workstations

Additional design entry and simulation support

provided by EDIF, library of parameterized

modules (LPM), Design ware components,

Verilog HDL, VHDL, and other interfaces to

popular EDA tools from manufacturers such as

Cadence, Exemplar Logic, Mentor Graphics,

OrCAD, Synopsys, Synplicity, VeriBest, and

Viewlogic

FLEX 10K Device Features (Continued)

(Courtesy of Altera Corp.)

FLEX 10K Device Features

(Courtesy of Altera Corp.)

Functional Description

FLEX 10K Device Block Diagram

(Courtesy of Altera Corp.)

Embedded Array Block-Logic Array Block

Note:

FPF10K10, FPF10K10A, FPF10K20, FPF10K30,

FPF10K30A, FPF10K40, FPF10K50 and FPF10K50V

devices have 22 EAB local interconnect channels;

EPF10K70, FPF10K100, FPF10K100A, FPF10K130V,

and FPF10K250A devices have 26.

FLEX 10K Embedded Array Block

(Courtesy of Altera Corp.)

FLEX 10K LAB (Courtesy of Altera Corp.)

Notes:

1. FPF10K10, FPF10K10A, FPF10K20, FPF10K30,

FPF10K30A, FPF10K40, FPF10K50 and

FPF10K50V devices have 22 inputs to the LAB local

interconnect channel from the row; EPF10K70,

FPF10K100, FPF10K100A, FPF10K130V, and

FPF10K250A devices have 26.

2. FPF10K10, FPF10K10A, FPF10K20, FPF10K30,

FPF10K30A, FPF10K40, FPF10K50 and

FPF10K50V devices have 30 LAB local interconnect

channels; EPF10K70, FPF10K100, FPF10K100A,

FPF10K130V, and FPF10K250A devices have 34

LABs.

Logic Element

FLEX 10K Logic Element (Courtesy of

Altera Corp.)