Chapter 1 Introduction to CMOS Circuit Design

Chapter 1 Chapter 1 ppIntroduction to CMOS Circuit Introduction to CMOS Circuit

DesignDesign

Jin-Fu LiAdvanced Reliable Systems (ARES) Lab.

Department of Electrical EngineeringN l C l UNational Central University

Jhongli, Taiwan

OutlineIntroductionMOS Transistor SwitchesMOS Transistor SwitchesCMOS LogicCi i d R iCircuit and System Representation

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

Introduction

AA

C

B

C=AxB


C=AxB

Switch: MOSFETMOSFETs are basic electronic devices used to direct and control logic signals in IC designto direct and control logic signals in IC design

MOSFET: Metal-Oxide-Semiconductor Field-Effect TransistorN-type MOS (NMOS) and P-type MOS (PMOS) Voltage-controlled switchesg

A MOSFET has four terminals: gate, source, drain and substrate (body)drain, and substrate (body)Complementary MOS (CMOS)

Usin t t p s f MOSFETs t t l i Using two types of MOSFETs to create logic networksNMOS & PMOS


NMOS & PMOS

Silicon Lattice and Dopant AtomsPure silicon consists of a 3D lattice of atoms

Silicon is a Group IV element and it forms covalent pbonds with four adjacent atomsIt is a poor conductor

N-type (P-type) semiconductorBy introducing small amounts of Group V-As (Group By ntroduc ng small amounts of Group V As (Group III-B) into the silicon lattice

Si SiSi

Si SiSi +

Si SiSi

As SiSi

--

Si SiSi

B SiSi

+

Si SiSi Si SiSi Si SiSi

L tti f L tti f N t L tti f P t


Lattice of pure Silicon

Lattice of N-type Semiconductor

Lattice of P-type Semiconductor

P-N JunctionsA junction between p-type and n-type semiconductor forms a diode.semiconductor forms a diode.Current flows only in one direction

p-type n-typep yp yp

anode cathodeanode cathode


NMOS TransistorFour terminals: gate, source, drain, bodyGate–oxide–body stack looks like a capacitorGate oxide body stack looks like a capacitor

Gate and body are conductorsSiO2 (oxide) is a very good insulator2 ( ) y gCalled metal–oxide–semiconductor (MOS) capacitorEven though gate is no longer made of metal

GateSource DrainPolysilicon

SiO2

n+

p bulk Si

n+


NMOS OperationsBody is commonly tied to ground (0 V)When the gate is at a low voltage:When the gate is at a low voltage:

P-type body is at low voltageSource body and drain body diodes are OFFSource-body and drain-body diodes are OFFNo current flows, transistor is OFF


SiO2

0n+

p bulk Si

n+D

0

S


NMOS Operations (Cont.)When the gate is at a high voltage:

Positive charge on gate of MOS capacitorPositive charge on gate of MOS capacitorNegative charge attracted to bodyInverts a channel under gate to n-typeInverts a channel under gate to n typeNow current can flow through n-type silicon from source through channel to drain, transistor is ONsource through channel to dra n, trans stor s ON


SiO2

Polysilicon

n+

p bulk Si

n+D

1

S


p bu S

PMOS OperationsSimilar, but doping and voltages reversed

Body tied to high voltage (VDD)Body tied to high voltage (VDD)Gate low: transistor ONGate high: transistor OFFGate high: transistor OFFBubble indicates inverted behavior

SiO


SiO2

n bulk Si

p+ p+


Threshold VoltageEvery MOS transistor has a characterizing parameter called the threshold voltage VTparameter called the threshold voltage VT

The specific value of VT is established during the manufacturing process the manufacturing process Threshold voltage of an NMOS and a PMOS

V

VADrainV

VA

NMOS PMOS

Source+ V

VA=1Mn On

VDD

VA

VGS

MnGate+

VA=1Mp Off

VDD

VDD-|VTp|VA

VGSp

MpGate

+

-

VDD

VA=0 Mn Off

VTn

0

VGSn

Source-

VA=0 Mp On0Drain


Logic translationGate-source voltage Logic translationGate-source voltage

MOS Transistor is Like a Tap…


Source: Prof. Banerjee, ECE, UCSB

MOS SwitchesNMOS symbol and characteristics

Vth5v

0v5v

0v5v-Vth

th

PMOS symbol and characteristicsy0v

0v5v

Vth

Vth

5v0v Vth


CMOS SwitchA complementary CMOS switch

Transmission gateTransmission gate

-s -s

Ca b a b a b

-s

Symbols

s s s

0v5v

0v

5v0v

0v

Characteristics5v


CMOS Logic-InverterThe NOT or INVERT function is often considered the simplest Boolean operationp p

F(x)=NOT(x)=x’ Vdd

Vin Vout Vin Vout

Vdd Vdd Vdd

0

Vdd Vdd Vdd

1 1 Vdd/2 Indeterminate0 1 1 0 Vdd/2 Indeterminatelogic level


Combinational LogicSerial structure

S1=0S2 0

S1=0S2 1

S1=1S2 0

S1=1S2 1a

S1

S2=0 S2=1 S2=0 S2=1aS1

0

0 1

a!=b a!=b

S2S2

0

1

a!=b a!=b

a!=b a=b

S1=0S2=0

S1=0S2=1

S1=1S2=0

S1=1S2=1

b

a S1

S1

S2 0 S2 1 S2 0 S2 1a S1

0

0 1

a=b a!=b

S2

S21 a!=b a!=b


b

Combinational LogicParallel structure

S1=0S2=0

S1=0S2=1

S1=1S2=0

S1=1S2=1a S1

0 1

S1 S2 S20

1

a!=b a=b

a=b a=b

S1=0S2=0

S1=0S2=1

S1=1S2=0

S1=1S2=1

b

a S1

S1 S2

S2 0 S2 1 S2 0 S2 1

S20

0 1

a=b a=b

b

1 a=b a!=b


b

NAND Gate

Output AA

Output A

0

10

1 1B B

1

0 1 1

1 0

AB

OutputB


NOR Gate

A

B

Output

A

0

10

1 0B

1

0 1 0

0 0

AB

OutputB


Compound Gate))()(( CDABF +=

A BA B

C DAB

FF

C D B

CD

A

B

C

DB D


Structured Logic DesignCMOS logic gates are intrinsically inverting

The output always produces a NOT operation The output always produces a NOT operation acting on the input variables

For example the inverter shown below For example, the inverter shown below illustrates this property

VDD1

f=0a=1

0


Structured Logic DesignThe inverting nature of CMOS logic circuits allows us to construct logic circuits for AOI allows us to construct logic circuits for AOI and OAI expressions using a structured approachapproachAOI logic function

Implements the operations in the order AND then Implements the operations in the order AND then OR then NOTE g dcbadcbag )( +=E.g.,

OAI logic functionImplements the operations in the order OR then

dcbadcbag ..),,,( +

Implements the operations in the order OR then AND then NOTE g )()()( dcbadcbag +⋅+=


E.g., )()(),,,( dcbadcbag ++=

Structured Logic DesignBehaviors of nMOS and pMOS groups

Parallel-connected nMOS Parallel connected nMOS OR-NOT operations

Parallel-connected pMOSpAND-NOT operations

Series-connected nMOSAND-NOT operations

Series-connected pMOS OR-NOT operations

Consequently, wired groups of nMOS and pMOS are logical duals of another


Dual PropertyIf an NMOS group yields a function of the form

)(b

then an identically wired PMOS array gives the

)( cbag +⋅=

then an identically wired PMOS array gives the dual function

h h AND d OR i h b

)( cbaG ⋅+=

where the AND and OR operations have been interchanged

h f NM PM This is an interesting property of NMOS-PMOS logic that can be exploited in some CMOS designs


An Example of Structured Design)( dcbaX +⋅+=

VDD

cb

d

a

X

Group 1 Group 2

Group 3

ab

dc


An Example of XOR GateBoolean equation of the two input XOR gate

this is not in AOI formbababa ⋅+⋅=⊕ , this is not in AOI formBut, , this is in AOI form Therefore

bababa +=⊕bababa ⋅+⋅=⊕

bbbb ⊕⊕ )(Therefore, babababa ⋅+⋅=⊕=⊕ )(

VDDb

VDDba

b

b

a

a

b a

b• •••

a aba ⊕

a aba ⊕• •••

b b b b

XOR Gate XNOR Gate


XOR Gate XNOR Gate

Multiplexer

1110

AB

AB

Y10

100100

BCD

Y

S S

-SS

A

S1 S0

AY

S YB

CB

-S

C

D

S1 -S1 S0 -S0


S

Static CMOS SummaryIn static circuits at every point in time (except when switching), the output is connected to g), peither Vdd or Gnd through a low resistance path

Fan-in of n (or n inputs) requires 2n (n N-type and n P-type) devices

Non-ratioed logic: gates operate independent of PMO NMO iPMOS or NMOS sizesNo path ever exists between Vdd and Gnd: low

static powerFully-restored logic (NMOS passes “0” only and PMOS passes “1” onlyGates must be inverting


Latches

D -Q

CLKQ

Q -QD D

CLK

Q

-Q Q

Q Q


Flip Flop

QMaster Slave

QD-Q

CLK

D D QQ-Q-Q

CLKCLK


Circuit and System RepresentationsBehavioral representation

Functional high levelFunctional, high levelFor documentation, simulation, verification

Structural representationStructural representationSystem level – CPU, RAM, I/OFunctional level ALU Multiplier AdderFunctional level – ALU, Multiplier, AdderGate level – AND, OR, XORCi it l l T sist s R L CCircuit level – Transistors, R, L, CFor design & simulation

Ph i l iPhysical representationFor fabrication


Behavior RepresentationA one-bit full adder (Verilog)

module fadder(sum,cout,a,b,ci);output sum, cout;i b iinput a, b, ci;reg sum, cout;

a b

always @(a or b or ci) beginsum = a^b^ci;

ci coutfadder

sum = a^b^ci;cout = (a&b)|(b&ci)|(ci&a);

end

sum

endendmodule


Structure RepresentationA four-bit full adder (Verilog)

module adder4(s,c4,a,b,ci); a b( )output[3:0] sum;output c4;input[3:0] a b;

a[0] b[0] a[1] b[1] a[2] b[2] a[3] b[3]input[3:0] a, b;input ci;reg[3:0] s;

ci

s[0]

a0 a3a1 a2

s[1] s[2] s3]

co[0] co[1] co[2]

reg c4;wire[2:0] co;

fadder a0(s[0] co[0] a[0] b[0] ci);

s[0] s[1] s[2] s3]

s adder4fadder a0(s[0],co[0],a[0],b[0],ci);fadder a1(s[1],co[1],a[1],b[1],co[0]);fadder a2(s[2],co[2],a[2],b[2],co[1]);

adde

fadder a3(s[3],c4,a[3],b[3],co[2]);endmodule


Physical RepresentationLayout of a 4-bit NAND gate

in1 in2 in3 in4

Vdd Vdd

in1 in2 in3 in4

in1Out

in2Out

in3

in4

in1 in2 in3 in4

Gnd


in1 in2 in3 in4

Design Flow for a VLSI Chip

S ifi tiSpecification

Function

Behavioral Design

Structural Design

Function

Function

Physical Design

FunctionTimingPower

Physical Design


Documents

Chapter 1 Introduction to CMOS Circuit Design