Chapter 01 Computer Organization and Design, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design) 5th Edition

8/17/2019 Chapter 01 Computer Organization and Design, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design) 5th Edition

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COMPUTER ORGANIZATION AND DThe Hardware/Software Interface

5thEdition

Chap er 1

Computer Abstractions

and Technology


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Chapter 1 — Computer Abstractions and Technology — 2

The Computer Revolution

Progress in computer technology Underpinned by Moore’s aw

Ma!es no"el applications feasible

#omputers in automobiles #ell phones

Human genome pro$ect

%orld %ide %eb Search Engines

#omputers are per"asi"e

&'('Introduc

tio n


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Classes of Computers

Personal computers )eneral purpose* "ariety of software Sub$ect to cost/performance tradeoff

Ser"er computers +etwor! based High capacity* performance* reliability

,ange from small ser"ers to building si-ed


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Classes of Computers

Supercomputers High.end scientific and engineering

calculations Highest capability but represent a small

fraction of the o"erall computer mar!et

Embedded computers

Hidden as components of systems Stringent power/performance/cost constraints



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The ostC !ra


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The ostC !ra

Chapter 1 — Computer Abstractions and Technology — "

Personal Mobile e"ice 0PM1 2attery operated #onnects to the Internet Hundreds of dollars Smart phones* tablets* electronic glasses

#loud computing %arehouse Scale #omputers 0%S#1

Software as a Ser"ice 0SaaS1 Portion of software run on a PM and a

portion run in the #loud 3ma-on and )oogle


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$hat %ou $ill &earn

How programs are translated into themachine language 3nd how the hardware e4ecutes them

The hardware/software interface %hat determines program performance

3nd how it can be impro"ed

How hardware designers impro"eperformance

%hat is parallel processing


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(nderstanding erformance

3lgorithm etermines number of operations e4ecuted

Programming language* compiler* architecture etermine number of machine instructions e4ecuted

per operation Processor and memory system

etermine how fast instructions are e4ecuted

I/5 system 0including 5S1 etermines how fast I/5 operations are e4ecuted


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!ight )reat *deas

esign for Moore’s Law

Use abstraction to simplify design

Ma!e the common case fast

Performance via parallelism

Performance via pipelining

Performance via prediction

Hierarchy of memories

Dependability via redundancy

Chapter 1 — Computer Abstractions and Technology — +

&'(6Eig

ht)reatIdeas

in#om

puter3rchitec

t

ure


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Chapter 1 — Computer Abstractions and Technology — 1,

-elo. %our rogram

3pplication software %ritten in high.le"el language

System software #ompiler7 translates H code to

machine code 5perating System7 ser"ice code

Handling input/output

Managing memory and storage

Scheduling tas!s 8 sharing resources Hardware

Processor* memory* I/5 controllers

&'(92e

low:

ourProg

ram


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&evels of rogram Code

High.le"el language e"el of abstraction closer

to problem domain Pro"ides for producti"ity

and portability

3ssembly language Te4tual representation of

instructions

Hardware representation 2inary digits 0bits1 Encoded instructions and

data


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Components of a Computer

Same components for

all !inds of computer es!top* ser"er*

embedded

Input/output includes User.interface de"ices

isplay* !eyboard* mouse

Storage de"ices

Hard dis!* #/;* flash +etwor! adapters


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Touchscreen

PostP# de"ice

Supersedes !eyboard

and mouse

,esisti"e and

#apaciti"e types Most tablets* smart

phones use capaciti"e

#apaciti"e allows

multiple touchessimultaneously


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Through the &oo/ing )lass

# screen7 picture elements 0pi4els1 Mirrors content of frame buffer memory


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0pening the -o

#apaciti"e multitouch # screen

9(> ;* 6? %att.hour battery

#omputer board


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Chapter 1 — Computer Abstractions and Technology — 1"

*nside the rocessor C(

atapath7 performs operations on data #ontrol7 se@uences datapath* memory* (((

#ache memory

Small fast S,3M memory for immediateaccess to data


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Chapter 1 — Computer Abstractions and Technology — 1#

*nside the rocessor

3pple 3?


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Chapter 1 — Computer Abstractions and Technology — 1'

Abstractions

3bstraction helps us deal with comple4ity Hide lower.le"el detail

Instruction set architecture 0IS31 The hardware/software interface

3pplication binary interface

The IS3 plus system software interface Implementation

The details underlying and interface

The BIG Pic ure


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Chapter 1 — Computer Abstractions and Technology — 1+

A afe lace for ata

;olatile main memory oses instructions and data when power off

+on."olatile secondary memory Magnetic dis!


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6et.or/s

#ommunication* resource sharing*nonlocal access

ocal area networ! 03+17 Ethernet

%ide area networ! 0%3+17 the Internet %ireless networ!7 %i


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Technology Trends

Electronics

technologycontinues to e"ol"e Increased capacity

and performance

,educed cost

:ear Technology ,elati"e performance/cost

'A?' ;acuum tube '

'AB? Transistor 9?'AC? Integrated circuit 0I#1 ADD

'AA? ;ery large scale I# 0;SI1 6*=DD*DDD

6D'9 Ultra large scale I# 6?D*DDD*DDD*DDD

,3M capacity

&'(?Te

chnologiesfor

2uilding

Processorsa

n

dMem

ory


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emiconductor Technology

Silicon7 semiconductor 3dd materials to transform properties7

#onductors

Insulators Switch



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7anufacturing *Cs

:ield7 proportion of wor!ing dies per wafer


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*ntel Core i# $afer

9DDmm wafer* 6>D chips* 96nm technology

Each chip is 6D(C 4 'D(? mm


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*ntegrated Circuit Cost

+onlinear relation to area and defect rate

%afer cost and area are fi4ed efect rate determined by manufacturing process

ie area determined by architecture and circuit design

6area/611ieareaper 0efects0'

':ield

areaiearea%afer wafer per ies

:ieldwafer per ies wafer per #ostdieper #ost

×+=

≈

×=

&


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efining erformance

%hich airplane has the best performance

&'(BPe

rformance


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Response Time and Throughput

,esponse time How long it ta!es to do a tas!

Throughput Total wor! done per unit time

e(g(* tas!s/transactions/F per hour How are response time and throughput affected

by ,eplacing the processor with a faster "ersion

3dding more processors

%e’ll focus on response time for nowF


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Relative erformance

efine Performance G '/E4ecution Time is n time faster than :J

n== :

:

timeE4ecutiontimeE4ecution

ePerformancePerformanc

E4ample7 time ta!en to run a program 'Ds on 3* '?s on 2

E4ecution Time2 / E4ecution Time 3G '?s / 'Ds G '(?

So 3 is '(? times faster than 2


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7easuring !ecution Time

Elapsed time Total response time* including all aspects Processing* I/5* 5S o"erhead* idle time

etermines system performance

#PU time Time spent processing a gi"en $ob

iscounts I/5 time* other $obs’ shares

#omprises user #PU time and system #PUtime ifferent programs are affected differently by

#PU and system performance


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C( Cloc/ing

5peration of digital hardware go"erned by a

constant.rate cloc!

#loc! 0cycles1

ata transfer and computation

Update state

#loc! period

#loc! period7 duration of a cloc! cycle e(g(* 6?Dps G D(6?ns G 6?DK'D L'6s

#loc! fre@uency 0rate17 cycles per second e(g(* =(D)H- G =DDDMH- G =(DK'DAH-


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C( Time

Performance impro"ed by ,educing number of cloc! cycles

Increasing cloc! rate

Hardware designer must often trade off cloc!rate against cycle count

,ate#loc!

#ycles#loc!#PU

Time#ycle#loc!#ycles#loc!#PUTime#PU

=

×=


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C( Time !ample

#omputer 37 6)H- cloc!* 'Ds #PU time

esigning #omputer 2 3im for Bs #PU time

#an do faster cloc!* but causes '(6 K cloc! cycles

How fast must #omputer 2 cloc! be

=)H-Bs

'D6=

Bs

'D6D'(6,ate#loc!

'D6D6)H-'Ds

,ate#loc!Time#PU#ycles#loc!

Bs

#ycles#loc!'(6

Time#PU

#ycles#loc!,ate#loc!

AA

2

A

3 3 3

3

2

22

=×

=××

=

×=×=

×=

×==


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*nstruction Count and C*

Instruction #ount for a program etermined by program* IS3 and compiler

3"erage cycles per instruction etermined by #PU hardware

If different instructions ha"e different #PI 3"erage #PI affected by instruction mi4

,ate#loc!

#PI#ountnInstructio

Time#ycle#loc!#PI#ountnInstructioTime#PUnInstructioper #ycles#ountnInstructio#ycles#loc!

×=

××=×=


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C* !ample

#omputer 37 #ycle Time G 6?Dps* #PI G 6(D #omputer 27 #ycle Time G ?DDps* #PI G '(6 Same IS3 %hich is faster* and by how much

'(6?DDpsI

BDDpsI

3Time#PU

2Time#PU

BDDpsI?DDps'(6I

2Time#ycle

2#PI#ountnInstructio

2Time#PU

?DDpsI6?Dps6(DI

3Time#ycle 3#PI#ountnInstructio 3Time#PU

=×

×=

×=××=

××=

×=××=

××=

3 is fasterF

Fby this much


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C* in 7ore etail

If different instruction classes ta!e different

numbers of cycles

∑=

×=n

'i

ii 1#ountnInstructio0#PI#ycles#loc!

%eighted a"erage #PI

∑=

×==

n

'i

i

i #ountnInstructio

#ountnInstructio

#PI#ountnInstructio

#ycles#loc!

#PI

,elati"e fre@uency


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C* !ample

3lternati"e compiled code se@uences usinginstructions in classes 3* 2* #

#lass 3 2 #

#PI for class ' 6 9

I# in se@uence ' 6 ' 6I# in se@uence 6 = ' '

Se@uence '7 I# G ?

#loc! #yclesG 6K' 'K6 6K9

G 'D

3"g( #PI G 'D/? G 6(D

Se@uence 67 I# G B

#loc! #yclesG =K' 'K6 'K9

G A

3"g( #PI G A/B G '(?


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erformance ummary

Performance depends on 3lgorithm7 affects I#* possibly #PI

Programming language7 affects I#* #PI

#ompiler7 affects I#* #PI

Instruction set architecture7 affects I#* #PI* Tc

The BIG Pic ure

cycle#loc!

Seconds

nInstructio

cycles#loc!

Program

nsInstructioTime#PU ××=

&'


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o.er Trends

In #M5S I# technology

(CTh

ePow

er%all


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Reducing o.er

Suppose a new #PU has >?O of capaciti"e load of old #PU

'?O "oltage and '?O fre@uency reduction

D(?6D(>???10;D(>?#PP =

old

6

oldold

old

6

oldold

old

new ==×× ×××××=

The power wall

%e can’t reduce "oltage further %e can’t remo"e more heat

How else can we impro"e performance

&'


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(niprocessor erformance(>TheSea

# hange7TheS

witchto

Multipro

cesso

rs

#onstrained by power* instruction.le"el parallelism*

memory latency


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7ultiprocessors

Multicore microprocessors More than one processor per chip

,e@uires e4plicitly parallel programming

#ompare with instruction le"el parallelism Hardware e4ecutes multiple instructions at once Hidden from the programmer

Hard to do Programming for performance oad balancing

5ptimi-ing communication and synchroni-ation


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!C C( -enchmar/

Programs used to measure performance Supposedly typical of actual wor!load

Standard Performance E"aluation #orp 0SPE#1 e"elops benchmar!s for #PU* I/5* %eb* F

SPE# #PU6DDB Elapsed time to e4ecute a selection of programs

+egligible I/5* so focuses on #PU performance +ormali-e relati"e to reference machine Summari-e as geometric mean of performance ratios

#I+T6DDB 0integer1 and #


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C*6T2,," for *ntel Core i# +2,

!C - h /


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!C o.er -enchmar/

Power consumption of ser"er at different

wor!load le"els Performance7 ss$ops/sec

Power7 %atts 0Qoules/sec1

= ∑∑

==

'D

Di

i

'D

Di

i power ss$ops%attper ss$ops5"erall


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!Cpo.er8ss92,,' for :eon :5"5,

itf ll A d hl< &

&'(


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itfall; Amdahl


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=allacy; &o. o.er at *dle

oo! bac! at iC power benchmar! 3t 'DDO load7 6?>%

3t ?DO load7 'CD% 0BBO1

3t 'DO load7 '6'% 0=CO1

)oogle data center Mostly operates at 'DO L ?DO load

3t 'DDO load less than 'O of the time

#onsider designing processors to ma!e

power proportional to load


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itfall; 7* as a erformance 7etric

MIPS7 Millions of Instructions Per Second oesn’t account for

ifferences in IS3s between computers

ifferences in comple4ity between instructions

BB

B

'D#PI

rate#loc!

'Drate#loc!

#PIcountnInstructio

countnInstructio

'DtimeE4ecution

countnInstructioMIPS

×

=

××

=

×=

#PI "aries between programs on a gi"en #PU

C l di R /

&'(


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Concluding Remar/s

#ost/performance is impro"ing ue to underlying technology de"elopment

Hierarchical layers of abstraction In both hardware and software

Instruction set architecture The hardware/software interface

E4ecution time7 the best performance

measure Power is a limiting factor

Use parallelism to impro"e performance

A#oncludin

g,emar!s

Documents

Chapter 01 Computer Organization and Design, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design) 5th Edition