chap5

The 8051 Microcontroller and Embedded Systems

CHAPTER 5

8051 ADDRESSING MODES

OBJECTIVES

List the five addressing modes of the 8051 microcontroller Contrast and compare the addressing modes Code 8051 Assemblv language instructions using each

addressing mode Access RAM using various addressing modes List the SFR (special function registers) addresses Discuss how to access the SFR Manipulate the stack using direct addressing mode Code 8051 instructions to manipulate a look-up table Access RAM, I/O, and ports using bit addresses Discuss how to access the extra 128 bytes of RAM space in

the 8052

Addressing Modes

The various addressing modes of a microprocessor are determined when it is designed, and therefore cannot be changed by the programmer.

The 8051 provides a total of five distinct addressing modes.

– (1) immediate – (2) register – (3) direct– (4) register indirect – (5) indexed

Immediate addressing mode

The operand comes immediately after the op-code.

The immediate data must be preceded by the pound sign, "#".

Register addressing mode

Register addressing mode involves the use of registers to hold the data to be manipulated.

SECTION 5.2: ACCESSING MEMORY USING VARIOUS ADDRESSING MODES

Direct addressing mode There are 128 bytes of RAM in the 8051. The RAM has been assigned addresses 00 to

7FH. – 1. RAM locations 00 - 1 FH are assigned to the register

banks and stack.– 2. RAM locations 20 - 2FH are set aside as bit-

addressable space to save single bit data. – 3. RAM locations 30 - 7FH are available as a place to

save byte-sized data.

Direct addressing mode

It is most often used to access RAM locations 30 - 7FH.

This is due to the fact that register bank locations are accessed by the register names of R0 - R7.

There is no such name for other RAM locations so must use direct addressing.

Direct addressing mode

In the direct addressing mode, the data is in a RAM memory location whose address is known, and this address is given as a part of the instruction.

Special Function Registers

In the 8051, registers A, B, PSW, and DPTR are part of the group of registers commonly referred to as SFR.

The SFR can be accessed by their names or by their addresses.

For example, register A has address E0H and register B has been designated the address F0H.

SFR

SECTION 5.2: ACCESSING MEMORY USING VARIOUS ADDRESSING MODES

SFR registers and their addresses

Table 5–1 8051 Special Function Register (SFR) Addresses

Stack and direct addressing mode

Another major use of direct addressing mode is the stack.

In the 8051 family, only direct addressing mode is allowed for pushing onto the stack.

An instruction such as "PUSH A" is invalid. Pushing the accumulator onto the stack must be coded as "PUSH 0E0H.

Direct addressing mode must be used for the POP instruction as well.

"POP 04" will pop the top of the stack into R4 of bank 0.

Register indirect addressing mode

A register is used as a pointer to the data. If the data is inside the CPU, only registers R0

and R 1 are used for this purpose. R2 - R7 cannot be used to hold the address of an

operand located in RAM when using indirect addressing mode.

When RO and R 1 are used as pointers they must be preceded by the @ sign.

Register indirect addressing mode

Advantage of register indirect addressing mode

One of the advantages of register indirect addressing mode is that it makes accessing data dynamic rather than static as in the case of direct addressing mode.

Looping is not possible in direct addressing mode.

This is the main difference between the direct and register indirect addressing modes.

Advantage of register indirect addressing mode

Limitation of register indirect addressing mode in the 8051

R0 and R 1 are the only registers that can be used for pointers in register indirect addressing mode.

Since R0 and R l are 8 bits wide, their use is limited to accessing any information in the internal RAM (scratch pad memory of 30H - 7FH, or SFR).

To access data stored in external RAM or in the code space of on-chip ROM, we need a 16-bit pointer, the DPTR.

Indexed addressing mode and on-chip ROM access

Indexed addressing mode is widely used in accessing data elements of look-up table entries located in the program ROM space of the 8051.

The instruction used for this purpose is :MOVC A, @ A+DPTR

The 16-bit register DPTR and register A are used to form the address of the data element stored in on-chip ROM.

Because the data elements are stored in the program (code) space ROM of the 8051, the instruction MOVC is used instead of MOV. The "C" means code.

In this instruction the contents of A are added to the 16-bit register DPTR to form the 16 bit address of the needed data.

Indexed addressing mode and MOVX instruction

The 8051 has another 64K bytes of memory space set aside exclusively for data storage.

This data memory space is referred to as external memory and it is accessed by the MOVX instruction.

The 8051 has a total of 128K bytes of memory space since 64K bytes of code added to 64K bytes of data space gives us 128K bytes.

One major difference between the code space and data space is that, unlike code space, the data space cannot be shared between code and data.

SECTION 5.3: BIT ADDRESSES FOR I/O AND RAM

Many microprocessors such as the 386 or Pentium allow programs to access registers and I/0 ports in byte size only.

If you need to check a single bit of an I/0 port, you must read the entire byte first and then manipulate the whole byte with some logic instructions to get hold of the desired single bit.

This is not the case with the 8051. One of the most important features of the 8051 is the ability to

access the registers, RAM, and I/0 ports in bits instead of bytes.

This is a very unique and powerful feature for a microprocessor made in the early 1980s.


Bit-addressable RAM

Figure 5–1 16 Bytes of Internal RAM. Note: They are both bit- and byte-accessible.


Bit-addressable RAM

Table 5–2 Single-Bit Instructions


I/O port bit addresses

Figure 5–2 SFR RAM Address (Byte and Bit)


Bit memory map

Table 5–3 Bit Addresses for All Ports


Registers bit-addressability

Figure 5–3 Bits of the PSW Register

Types Of Instructions

1. Data transfer instructions.

2. Arithmetic instructions.

3. Logical instructions.

4. Logical instructions with bits.

5. Branch instructions.

PUNJAB EDUSAT SOCIETY

Data Transfer Instructions

These instructions move the content of one register to another one.

Data can be transferred to stack with the help of PUSH and POP instructions.



MNEMONIC DESCRIPTION BYTES

MOV A,Rn (A) (Rn) 1

MOV A,Rx (A) (Rx) 2

MOV A,@Ri (A) (Ri) 1



MOV A,#X (A) Data 2

MOV Rn,A (Rn) (A) 1

MOV Rn, Rx (Rn) (Rx) 2



MOV Rn, #X (Rn) Data 2

MOV Rx, A (Rx) (A) 2

MOV Rx, Rn (Rx) (Rn) 2



MOV Rx, Ry (RX) (Ry) 3

MOV Rx, @ Ri (Rx) (Ri) 2

MOV Rx, # X (Rx) Data 3



MOV @ Ri, A (Ri) (A) 1

MOV @ Ri, Rx (Ri) (Rx) 2

MOV @ Ri, #X (Ri) Data 2



MOV DPTR, #X (DPTR) Data 3

MOVC A @ (A) (A+DPTR) 1 A+DPTR

MOVC A@ (A) (A+PC) 1

A+PC



MOVX A,@ Ri A (Ri) 1

MOVX A, @ (A) (DPTR) 1

MOVX @Ri, A (Ri) (A) 1

DPTR



MOVX @ (DPTR) (A) 1

PUSH Rx Push directly 2 addressed Rx register on stack

POP Rx (A) (Rx) 2

DPTR, A



XCH A, Rn (A) (Rn) 1

XCH A, Rx (A) (Rx) 2

XCH A, @Ri (A) (Ri) 1



XCHD Exchange 4 lower 1 bits in accumulator with indirectly addressed register


Arithmetic Instructions

These instructions perform several basic operations. After execution, the result is stored in the first operand.

8 bit addition, subtraction, multiplication, increment-decrement instructions can be performed.



MNEMONICS DESCRIPTION BYTE

ADD A, Rn A = A + Rn 1

ADD A, Rx A = A + Rx 2

AAD A, @ Ri A = A+ Ri 1



ADD A, # X A = A + Byte 2

ADDC A, Rn A = A + Rn + C 1

ADDC A , Rx A = A + Rx + C 2



ADDC A, @ Ri A = A + Ri + C 1

ADDC A, # X A = A + Byte + C 2

SUBB A, Rn A = A – Rn – 1 1



SUBB A, Rx A = A – Rx – 1 2

SUBB A, @ Ri A = A – Ri – 1 1

SUBB A, # X A = A – Byte – 1 2



INC A A = A + 1 1

INC Rn Rn = Rn + 1 1

INC Rx Rx = Rx + 1 2



INC @ Ri Ri = Ri + 1 1

DEC A A = A – 1 1

DEC Rn Rn = Rn – 1 1



DEC Rx Rx = Rx – 1 2

DEC @ Ri Ri = Ri – 1 1

INC DPTR DPTR = DPTR + 1 1



MUL AB B:A = A * B 1

DIV AB A = [A/B] 1

DA A Decimal adjustment of 1 accumulator according to BCD code


Logical Instructions

These instructions perform logical operations between two register contents on bit by bit basis.

After execution, the result is stored in the first operand.



MNEMONIC DESCRIPTION BYTE

ANL A, Rn (A) (A) ^ (Rn) 1

ANL A, Rx (A) (A) ^ (Rx) 2

ANL A,@ Ri (A) (A) ^ (Ri) 1



ANL A, # X (A) (8 bit data) ^ (A) 2

ANL Rx, A (Rx) (A) ^ (Rx) 2

ANL Rx,# X (Rx) (8 bit data) ^ (Rx) 3



ORL A, Rn (A) (A) + (Rn) 1

ORL A, Rx (A) (A) + (Rx) 2

ORL A, @ Ri (A) (A) + (Ri) 2



ORL Rx, A (Rx) (A) + (Rx) 2

ORL Rx,# X (Rx) (8 bit data) + (Rx) 2

XORL A, Rn Logical exclusive 1 OR operation between the contents of accumulator and R register.



XORL A, Rx Logical exclusive OR 2

operation between the contents of the accumulator and directly addressed register Rx.

XORL A,@ Ri Logical exclusive OR 1 operation between the contents of the accumulator and directly addressed register.



XORL A, # X Logical exclusive OR 2 operation between the contents of accumulator and the given 8 bit data.

XORL Rx, A Logical exclusive OR 2 operation between the contents of the accumulator and directly addressed register Rx.



XORL Rx, # X Logical exclusive OR 3 operation between the contents of the directly addressed register Rx and the given 8 bit data.

CLR A (A) 0 1

CPL A (A) (/A) 1



SWAP A (A3-0) (A7-4) 1

RL A (An + 1) (An) 1

(A0) (A7) RLC (An + 1) (An) 1

(A0) ( C )

( C ) (A7)



RR A (An) (An + 1) 1

(A7) (A0)

RRC A (An) (An + 1) 1

(A7) ( C )

( C ) (A0)


Logical Instructions On Bits

Similar to logical instructions, these instructions also perform logical operations.

The difference is that these operations are performed on single bits.




CLR C ( C = 0 ) 1

CLR bit clear directly addressed bit 2

SETB C ( C = 1 ) 1



SETB bit Set directly 2 addressed bit

CPL C (1 = 0, 0 = 1) 1

CPL bit Complement directly 2 addressed bit



ANL C, bit Logical AND operation 2 between Carry bit and directly addressed bit.

ANL C,/bit Logical AND operation 2 between Carry bit and inverted directly addressed bit.



ORL C, bit Logical OR operation 2 between Carry bit and directly addressed bit.

ORL C,/bit Logical OR operation 2 between Carry bit and inverted directly addressed bit.



MOV C, bit Move directly addressed 2 bit to carry bit.

MOV bit, C Move Carry bit to directly 2 addressed bit.


Program Flow Control Instructions

In this group, instructions are related to the flow of the program, these are used to control the operation like, JUMP and CALL instructions.

Some instructions are used to introduce delay in the program, to the halt program.




ACALL adr11 (PC) (PC) + 2 2

(SP) (SP) + 1

((SP)) (PC7 – 0)

(SP) (SP) + 1

((SP)) (PC15-8)



LCALL adr16 (PC) (PC) + 3 3

(SP) (SP) + 1

((SP)) (PC7-0)

(SP) (SP) + 1

((SP)) (PC15-8)

(PC) addr15-0



RET (PC15-8) ((SP)) 1

(SP) (SP) – 1

(PC7-0) ((SP))

(SP) (SP) - 1



RET1 (PC15-8) ((SP)) 1

(SP) (SP) – 1

(PC7-0) ((SP))

(SP) (SP) – 1

AJMP addr11 (PC) (PC) + 2 1

(PC10-0) page address



LJMP addr16 (PC) addr15-0 3

SJMP rel short jump from 2

(from -128 to +127 locations in

relation to first next instruction)



JC rel (PC) (PC) + 2 2

IF ( C ) = 1

THEN (PC) (PC) + rel

JNC rel (PC) (PC) + 2 2

IF ( C) = 0




JB bit, rel Jump if addressed 3

bit is set. Short jump.

JBC bit, rel Jump if addressed 3

bit is set and clear it.

Short jump.



JMP @A + DPTR (PC) (A) + (DPTR) 1

JZ rel (PC) (PC) + 2 2

IF (A) = 0




JNZ rel (PC) (PC) + 2 2

IF (A) = 0


CJNE A, Rx, rel Compare the contents 3

of acc. And directly addressed register Rx. Jump if they are different. Short jump.



CJNE A, #X, rel (PC) (PC) + 3 3

IF ( A) < > data

THEN (PC) (PC) + relative

offset

IF (A) < data

THEN ( C ) 1

ELSE ( C ) 0



CJNE @ RI, # x, rel (PC) (PC) + 3 3

IF (Rn) <> data


offset

IF (Rn) < data

THEN ( C ) 1

ELSE ( C ) 0



CJNE @ Ri, # X, rel (PC) (PC) + 3 3

IF ((Ri)) <> data


offset

IF ((Ri)) < data

THEN ( C ) 1

ELSE ( C ) 0



DJNZ Rn , rel (PC) (PC) + 2 2

(Rn) (Rn) - 1

IF (Rn) > 0 or (Rn) < 0




DJNZ Rx, rel (PC) (PC) + 2 3

(Rx) (Rn) – 1

IF (Rx) > 0 or (Rx) < 0


NOP No operation 1


Summary

Instruction set. Addressing modes. Data transfer instruction. Arithmetic instruction. Logical instruction. Logical operation on bits.


Using BIT directive

The BIT directive is a widely used directive to assign the bit-addressable I/0 and RAM locations.

The BIT directive allows a program to assign the I/0 or RAM bit at the beginning of the program, making it easier to modify them.

Using EQU directive

We can also use the EQU directive to assign addresses.

Next …

Lecture Problems Textbook Chapter 5– Answer as many questions as you can and

submit via MeL before the end of the lecture.–

Proteus Exercise Textbook Chapter 5– Do as much of the Proteus exercise as you can

and submit via MeL before the end of the lecture.

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