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Figure 41 Application of commutative law of addition.

Thomas L. Floyd

Digital Fundamentals, 9e

Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

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Figure 42 Application of commutative law of multiplication.

Thomas L. Floyd




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Figure 43 Application of associative law of addition. Open file F04-03 to verify.

Thomas L. FloydDigital Fundamentals, 9e



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Figure 44 Application of associative law of multiplication. Open file F04-04 to verify.




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Figure 45 Application of distributive law. Open file F04-05 to verify.




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Figure 46




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Figure 47




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Figure 48




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Figure 49


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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458


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Figure 410


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Figure 411


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Figure 412


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Figure 413


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Figure 414


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Figure 415 Gate equivalencies and the corresponding truth tables that illustrate DeMorgans theorems. Notice the equality of the two

output columnsin each table. This shows that the equivalent gates perform the same logic function.


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Figure 416 A logic circuit showing the development of the Boolean expression for the output.


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Figure 417 Gate circuits for Example 48. Open file F04-17 to verify equivalency.


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Figure 418 Implementation of the SOP expressionAB +BCD +AC.


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Figure 419 This NAND/NAND implementation is equivalent to the AND/OR in Figure 418.


Copyright 2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458


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Figure 420 Implementation of the POS expression (A +B)(B + C+D)(A + C).





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Figure 421 A 3-variable Karnaugh map showing product terms.





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Figure 422 A 4-variable Karnaugh map.





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Figure 423 Adjacent cells on a Karnaugh map are those that differ by only one variable. Arrows point between adjacent cells.





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Figure 424 Example of mapping a standard SOP expression.





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Figure 425





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Figure 426





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Figure 427





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Figure 428





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Figure 429





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Figure 430





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Figure 431





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Figure 433





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Figure 435 Example of mapping directly from a truth table to a Karnaugh map.





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Figure 436 Example of the use of dont care conditions to simplify an expression.





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Figure 437 Example of mapping a standard POS expression.



Upper Saddle River, New Jersey 07458All rights reserved.

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Figure 440




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Figure 441




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Figure 442 A 5-variable Karnaugh map.




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Figure 443 Illustration of groupings of 1s in adjacent cells of a 5-variable map.




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Figure 444




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Figure 445 A VHDL program for a 2-input AND gate.




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Figure 446




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Figure 447 Seven-segment display format showing arrangement of segments.




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Figure 448 Display of decimal digits with a 7-segment device.




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Figure 449 Arrangements of 7-segment LED displays.

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Figure 450 Block diagram of 7-segment logic and display.

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Fi 4 51 K h i i i i f h l i i

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Figure 451 Karnaugh map minimization of the segment-a logic expression.

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Fi 4 52 Th i i l i i l i f f h 7 di l

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Figure 452 The minimum logic implementation for segment a of the 7-segment display.

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Fi 4 53

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Figure 453

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Figure 454

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Figure 455

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Figure 456

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Figure 457

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Figure 458

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Figure 458

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Figure 459

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Figure 459

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Figure 460

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Figure 4 60

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Figure 461

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Figure 4 61

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Figure 4 62

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Figure 464

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g

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Figure 465

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g

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