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Figure 31 Standard logic symbols for the inverter (ANSI/IEEE Std. 91-1984).

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Digital Fundamentals, 9e

Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

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Figure 32 Inverter operation with a pulse input. Open file F03-02 to verify inverter operation.

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Figure 33 Timing diagram for the case in Figure 32.

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Figure 34




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Figure 35




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Figure 36 The inverter complements an input variable.




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Figure 37 Example of a 1s complement circuit using inverters.




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Figure 38 Standard logic symbols for the AND gate showing two inputs (ANSI/IEEE Std. 91-1984).




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Figure 39 All possible logic levels for a 2-input AND gate. Open file F03-09 to verify AND gate operation.


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2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458


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Figure 310 Example of AND gate operation with a timing diagram showing input and output relationships.


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Figure 311


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Figure 312


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Figure 313


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Figure 314 Boolean expressions for AND gates with two, three, and four inputs.


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Figure 315 An AND gate performing an enable/inhibit function for a frequency counter.


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Figure 316 A simple seat belt alarm circuit using an AND gate.


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Figure 317 Standard logic symbols for the OR gate showing two inputs (ANSI/IEEE Std. 91-1984).


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Figure 318 All possible logic levels for a 2-input OR gate. Open file F03-18 to verify OR gate operation.


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Figure 319 Example of OR gate operation with a timing diagram showing input and output time relationships.


Copyright 2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458


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Figure 320





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Figure 321





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Figure 322





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Figure 323 Boolean expressions for OR gates with two, three, and four inputs.





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Figure 324 A simplified intrusion detection system using an OR gate.





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Figure 325 Standard NAND gate logic symbols (ANSI/IEEE Std. 91-1984).





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Figure 326 Operation of a 2-input NAND gate. Open file F03-26 to verify NAND gate operation.





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Figure 327





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Figure 328





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Figure 329 Standard symbols representing the two equivalent operations of a NAND gate.





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Figure 331





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Figure 332





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Figure 333 Standard NOR gate logic symbols (ANSI/IEEE Std. 91-1984).





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Figure 334 Operation of a 2-input NOR gate. Open file F03-34 to verify NOR gate operation.





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Figure 335





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Figure 336





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Figure 337 Standard symbols representing the two equivalent operations of a NOR gate.



Upper Saddle River, New Jersey 07458All rights reserved.

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Figure 338




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Figure 339




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Figure 340




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Figure 341 Standard logic symbols for the exclusive-OR gate.




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Figure 342 All possible logic levels for an exclusive-OR gate. Open file F03-42 to verify XOR gate operation.




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Figure 343




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Figure 344 Standard logic symbols for the exclusive-NOR gate.




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Figure 345 All possible logic levels for an exclusive-NOR gate. Open file F03-45 to verify XNOR gate operation.




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Figure 346 Example of exclusive-OR gate operation with pulse waveform inputs.




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Figure 347




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Figure 348 An XOR gate used to add two bits.




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Figure 349 Basic concept of a programmable AND array.

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Figure 350

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Fi 3 51 Th bl f li k

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Figure 351 The programmable fuse link.

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Fi 3 53 A i l AND ith EPROM t h l O l t i th i h f i li it

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Figure 353 A simple AND array with EPROM technology. Only one gate in the array is shown for simplicity.

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Fi 3 54 B i t f AND ith SRAM t h l

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Figure 354 Basic concept of an AND array with SRAM technology.

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Figure 3 55 Setup for programming a PLD in a programming fixture (programmer)

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Figure 355 Setup for programming a PLD in a programming fixture (programmer).

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Figure 3 56 Programming setup for reprogrammable logic devices

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Figure 356 Programming setup for reprogrammable logic devices.

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Figure 3 57 Examples of design entry of an AND gate

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Figure 357 Examples of design entry of an AND gate.

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Figure 358 Simplified illustration of in-system programming via a JTAG interface

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Figure 358 Simplified illustration of in-system programming via a JTAG interface.

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Figure 359 Simplified block diagram of a PLD with an embedded processor and memory

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Figure 359 Simplified block diagram of a PLD with an embedded processor and memory.

Thomas L. Floyd




Figure 360 Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin numbers and basic dimensions

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Figure 3 60 Typical dual in line (DIP) and small outline (SOIC) packages showing pin numbers and basic dimensions.

Thomas L. Floyd




Figure 361 Pin configuration diagrams for some common fixed-function IC gate configurations.

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Figure 3 61 Pin configuration diagrams for some common fixed function IC gate configurations.

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Figure 362 Logic symbols for hex inverter (04 suffix) and quad 2-input NAND (00 suffix). The symbol applies to the same device in

CMOS TTL i

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any CMOS orTTL series.

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Figure 363

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g

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Figure 364 The LS TTL NAND gate output fans out to a maximum of 20 LS TTL gate inputs.

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g g p g p

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Figure 365 The partial data sheet for a 74LS00.

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g p

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Figure 366 The partial data sheet for a 74HC00A.

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g p

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Figure 367 The effect of an open input on a NAND gate.

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Figure 368 Troubleshooting a NAND gate for an open input.

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Figure 369 Troubleshooting a NOR gate for an open output.

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Figure 371

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Figure 372

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Figure 381

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Figure 388

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Figure 399

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