CHAP2_VLSITechImpl

7/29/2019 CHAP2_VLSITechImpl

1/55

VLSITechnology

Implementa3onTrioAdiono

www.paume.itb.ac.id/~tadiono/el-4040/


2/55

DesignParameters

ByWhichDesignSuccessisMeasured: PerformanceSpecs-func3on,3ming,speed,power SizeofDie-manufacturingcost TimetoDesign-engineeringcostandschedule EaseofTestGenera3on&Testability-engineeringcost,

manufacturing,cost,schedule

Manufacturability-resilienttocircuit/processvariability

8/20/12 EL-4040 Perancangan Sistem VLSI 2


3/55

Implementa3onChoices

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches



4/55

DesignandTechnologyStyles

CustomDesignMostlymanualdesign,longdesigncycleHighperformance,highvolumeMicroprocessors,analog,leafcells,IP

SemiCustom:StandardCell

Pre-designedcells,CAD,shortdesigncycleMediumperformance,ASIC

FPGA/PLDPre-fabricated,fastautomateddesign,lowcostPrototyping,reconfigurablecompu3ng



5/55

ChipSizeforDifferentTechnology

Gate Array

Standard Cell

Full Custom

Chip Area Ratios:3:2:1



6/55

PerformancevsDesignTIme



7/55

FullCustom

CustomDesignisusedwhenperformanceordesigndensityistheprimaryimportance.

CustomDesign:laborintensivehighcostandlong!metomarket

Onlyjus3fiedeconomicallyunderthefollowingcondi3ons:Thecustomblockcanbereusedmany3mes(for

example,asalibrarycell)

Thecostcanbeamor3zedoveralargevolume.(forexample,memories)

Costisnottheprimedesigncriterion,asitisinsupercomputersorhypersupercomputers.



8/55

CustomCircuitDesign

CustomdesigninIntelPen3um4,onlythemostperformance-cri3calmodulessuchasthePLLandtheclockbuffer.

Customdesignisusedindesigninglibrarycell.Intel 4004

Courtesy Intel



9/55

CustomDesignEnvironment

LayoutEditors Electrical-RuleCheckers(ERC) Design-RuleChecker(DRC) Verifica3onTool Simula3onTool Extrac3onToolModelingTool



10/55

Example:CustomDesign

Basicbuildingblock:SRAMCell Holdsonebitofinforma3on,likealatch Mustbereadandwri]en

12-transistor(12T)SRAMcell Useasimplelatchconnectedtobitline 46x75unitcell

bit

write

write_b

read

read_b

Schematic Layout8/20/12 EL-4040 Perancangan Sistem VLSI 10


11/55

DesignRuleChecker(DRC)

Poly_not_fet to all_diff minimum

spacing = 0.14 um.



12/55

StandardCell

ReusingalimitedlibraryofcellsStandardizedesignentrylevelatthelogicgate Standardiza3onisachievedatthelogicorfunc3onlevel

Specificdesignsforeachgatecandevelopedandstoredinasowaredatabaseorcelllibrary.

(Behavioral,Structural,andPhysicalDomaindescrip3onspercell)

Layoutisusuallyautoma3callyplacedandroutedusingCADsoware

Predominantfull-customdesignstyle Adesigniscapturedasaschema3c



13/55

StandardCell

Advantage:CellsonlyneedtobedesignedandverifiedonceCanbereusedmany3mes

Disadvantage:Reducethepossibilityoffine-tuningthedesignReducetheintegra3ondensityand/orperformance.



14/55

StandardCell

Librarycontainsawideselec3onoflogicgates:

SSIlogic:e.g.nand,nor,xor,inverters,buffers,latches,registers

+Eachgatecanhavemul3pleimplementa3onstoprovideproperdrivefordifferentfan-outs,e.g.standardsize,2x,4x

MSIlogic:e.g.decoders,encoders,adders,comparatorsDatapath:e.g.ALUs,adders,registerfiles,shiersMemories:e.g.RAM,ROM Systemlevelblocks:e.g.mul3pliers,microcontrollers

Multiplier Adder



15/55

StandardCell

Routing channelrequirements are

reduced by presence

of more interconnect

layers

Layoutisautoma2callygenerated

restric2ononlayoutop2onsCellsare

-Placedinrowsthatisseparatedby

rou2ngchannels.

-Allcellsinthelibraryhavetohave

iden2calheights.



16/55

StandardCells

UniformcellheightUniformwellheight

M1VDDandGNDrails M2AccesstoI/Os Well/substratetaps Exploitsregularity



17/55

SynthesizedStandardCell

SynthesizeHDLintogate-levelnetlist Place&Routeusingstandardcelllibrary Asubstan3alfrac3onofareadevotedtosignalrou3ng. Thegoalofplacementandrou3ngtoolsistominimizedinterconnectoverhead. Byfeed-throughcells Byaddingmoreinterconnectlayer



18/55

StandardCell

SSI/LSI blocks: layout style is rows of constant hight blocksseparated by rows of routing.

SSI/LSI standard cell concept is extended to higher levelfunctions, often available as parameterized modules.



19/55

StandardCell



20/55

StandardCell

Layoutstrategy: Supplylinearedistributehorizontallyandsharedbetweencellsinthesamerow Inputsignalsarewiredver3callyusingpolysilicon Input/outputterminalsarelocatedthroughoutthecellbody

Thesuccessofthestandardcellapproachanbea]ributedto:

Theincreasedqualityoftheautoma3ccellplacementandrou3ngtools

Theadventofsophis3catedlogic-synthesistools:usingmul3levelofabstrac3ons



21/55

StandardCellExample

[Brodersen92]



22/55

StandardCell

Cell-structurehidden under

interconnect layers



23/55

StandardCell-Example

3-input NAND cell

(from ST Microelectronics):C = Load capacitanceT = input rise/fall time



24/55

Automa3cCellGenera3on

Courtesy Acadabra

Initial transistor

geometries

Placed

transistors

Routed

cell

Compacted

cell

Finished

cell



25/55

MacroModules

25632 (or 8192 bit) SRAMGenerated by hard-macro module generator



26/55

SoMacroModules



27/55

IntellectualProperty

A Protocol Processor for Wireless



28/55

SemicustomDesignFlow

HDL

Logic Synthesis

Floorplanning

Placement

Routing

Tape-out

Circuit Extraction

Pre-LayoutSimulation

Post-LayoutSimulation

Structural

Physical

BehavioralDesign Capture

DesignIt

eration



29/55

TheDesignClosureProblem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)

h h h l


30/55

Integra3ngSynthesiswithPhysicalDesign

Physical Synthesis

RTL (Timing) Constraints

Place-and-RouteOptimization

Artwork

Netlist withPlace-and-Route Info

MacromodulesFixed netlists


G t A


31/55

Gate Array" Gate Array: A gate array is where the logic network can be

programmed into the device near the end of its manufacture,

during the metallization phase. " Advantages: Fast time-to-market, low Non-Recurring

Engineering (NRE) charges, lower cost." Disadvantages: Poor silicon utilization, limited mixed-signal

capability, poor per-formance relative to the cell-basedapproach." Alt. Designations: Sea-of-gates, embedded array,

embedded in an array (considered by In-Stat/MDR as astandard cell)."


( )


32/55

ProgrammableLogicArray(PLA)

x0 x1 x2

ANDplane

x0x1

x2

Product terms

ORplane

f0 f1


l


33/55

Two-LevelLogic

Inverting format (NOR-

NOR) more effective

Every logic function can beexpressed in sum-of-products

format (AND-OR)

minterm


PLA L t E l i3 l it


34/55

PLALayoutExploi3ngularity

f0

f1

x0

x0

x1

x1x2

x2

Pull-up devices Pull-up devices

VDD GNDAnd-Plane Or-Plane


B hi S N Lif i PLA


35/55

BreathingSomeNewLifeinPLAs

RiverPLAs

Acascadeofmulple-output PLAs. AdjacentPLAsareconnectedviariverroung.

PRE-CHARGE

PRE-

CHARGE

PRE-CHARGE

PRE-CHARGE

BUFFER

BUFFER

BUFFER

BUFFER

PRE-CHARGE

PRE-CHARGE

BUFFER

BUFFER

PRE-CHARGE

PRE-

CHARGE

BUFFER

BUFFER

No placement and routing needed. Output buffers and the input buffers

of the next stage are shared.

Courtesy B. Brayton8/20/12 EL-4040 Perancangan Sistem VLSI 35

elay


36/55

ExperimentalResults

LayoutofC2670

Network of PLAs,

4 layers OTC

River PLA,

2 layers no additional routing

Standard cell,

2 layers channel routing

Standard cell,

3 layers OTC

0.2

0.6

1

1.4

0 2 4 6 area

de

SC NPLA RPLA

Area:RPLAs (2 layers) 1.23SCs (3 layers) - 1.00,

NPLAs (4 layers) 1.31

DelayRPLAs 1.04SCs 1.00NPLAs 1.09

Synthesis time: for RPLA , synthesis time equals design time;SCs and NPLAs still need P&R.

Also: RPLAs are regular and predictable


L t Bi di I l t 3


37/55

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Late-BindingImplementa3on


G t A S f t


38/55

GateArraySea-of-gates

rows of

cells

routing

channel

uncommitted

VDD

GND

polysilicon

metal

possible

contact

In1 In2 In3 In4

Out

Uncommited

Cell

CommittedCell

(4-input NOR)


Sea of gate Primi3 e Cells


39/55

Sea-of-gatePrimi3veCells

N M O S

P M O S

O x id e - i s o l a t io n

P M O S

N M O S

N M O S

Using oxide-isolation Using gate-isolation


Sea of gates


40/55

Sea-of-gates

Random Logic

MemorySubsystem

LSI Logic LEA300K(0.6 m CMOS)

Courtesy LSI Logic


The return of gate arrays?


41/55

Thereturnofgatearrays?

The image cannot be displayed. Yourcomputer may not have enoughmemory to open the image, or theimage may have been corrupted.Restart your computer, and then openthe file again. If the red x still appears,you may have to delete the image andthen insert it again.

The image cannot be displayed. Yourcomputer may not have enoughmemory to open the image, or theimage may have been corrupted.Restart your computer, and then openthe file again. If the red x stillappears, you may have to delete theimage and then insert it again.

metal-5 metal-6

Via-programmable cross-point

programmable via

Via programmable gate array

(VPGA)

[Pileggi02] Exploits regularity of interconnect


User Programmable Logic


42/55

User-Programmable Logic" User-Programmable Logic: User-Programmable Logic (UPL) is

comprised of three unique product families; Simple Programmable Logic

Devices (SPLDs), Complex Programmable Logic Devices (CPLDs), andField-Programmable Gate Arrays (FPGAs), with FPGAs being the mostcommonly used UPL. Memory programming architectures mostcommonly used in these products are static RAM, EEPROM, flashmemory and anti-fuse. Density measurements of user-programmablelogic products vary with the product, with the most common for FPGAs

being system gates, and for CPLDs, Look Up Tables (LUTs). Dependingupon whom one talks to, a system gate can range anywhere from 8-12ASIC gates."

Advantages: Very low, if any, non-recurring engineering charges, veryrapid time-to- market, and depending on particular product andarchitecture, can be of very low cost, with the emphasis on can. Unless

it is a fused or ant-fused architecture, UPL can be reconfigured in thefield."

Disadvantages: Poor silicon utilization, considerably lower performancecompared to an equivalent cell-based design, extremely limited analogcapability."


Prewired Arrays


43/55

PrewiredArrays

Classifica3onofprewiredarrays(orfield-programmable

devices): BasedonProgrammingTechnique

Fuse-based(program-once)Non-vola3leEPROMbased RAMbased

ProgrammableLogicStyle Array-Based Look-upTable

ProgrammableInterconnectStyle Channel-rou3ngMeshnetworks


RAM based FPGA


44/55

RAM-basedFPGA

Xilinx XC4000exCourtesy Xilinx8/20/12 EL-4040 Perancangan Sistem VLSI 44

A Low Energy FPGA (UC Bey)


45/55

ALow-EnergyFPGA(UCBey)

qArray Size: 8x8 (2 x 4LUT)

q Power Supply: 1.5V &0.8V

q Configuration: Mapped asRAM

q Toggle Frequency:125MHz

qArea: 3mm x 3mm


Larger Granularity FPGAs


46/55

LargerGranularityFPGAs

q 1-mm 2-metalCMOS tech

q 1.2 x 1.2 mm2q

600k transistors

q 208-pin PGAq fclock = 50 MHz

q Pav = 3.6 W @ 5Vq Basic Module: Datapath

PADDI-2 (UC Berkeley)


Structured ASIC


47/55

Structured ASIC" Structured ASIC: A MOS cell-based design, which includes

the capability to be repro-grammed, as well as having its logic

reconfigured, by one of several approaches, includingembedded gate array, FPGA and fuse."

Advantages: Rapid time-to-market, lower non-recurring NREcharges than those associated with the cell-based approach,excellent mixed-signal capability, multi-applicationalpossibilities."

Disadvantages: As a customer, you have to be involvedearly in the device design cycle, so costs will be higher thanthose associated with the gate array, for example."


Structured ASICs


48/55

StructuredASICs

StructuredASICsareanewbreedofcustomdevicethatapproachtheperformanceoftoday'sStandardCellASICwhiledrama3callysimplifyingthedesigncomplexity.StructuredASICsofferdesignersasetofdeviceswithspecific,customizablemetallayersalongwithpredefinedmetallayers,whichcancontaintheunderlyingpa]ernof

logiccells,memory,andI/O.


Design at a Crossroad


49/55

DesignataCrossroad

System-on-a-Chip

RAM

500 k Gates FPGA

+ 1 Gbit DRAM

Preprocessing

Multi-

Spectral

Imager

Csystem

+2 Gbit

DRAMRecog-

nition

A

nalog

64 SIMD Processor

Array + SRAM

Image Conditioning100 GOPS

q Embedded applicationswhere cost,performance,

and energy are the real

issues!

q DSP and control intensiveq Mixed-modeq Combines programmable

and application-specificmodules

q Software plays crucial role


T i3 t A t 3 d R l St t


50/55

Transi3ontoAutoma3onandRegularStructures

Intel 4004 (71) Intel 8080

Intel 8085

Intel 8286 Intel 8486Courtesy Intel


Architecture Re-Use


51/55

ArchitectureRe-Use

SiliconSystemPlaorm Flexiblearchitectureforhardwareandsoware Specific(programmable)components Networkarchitecture Sowaremodules RulesandguidelinesfordesignofHWandSW

HasbeensuccessfulinPCs Dominanceofafewplayerswhospecifyandcontrolarchitecture

Applica3on-domainspecific(differenceinconstraints) Speed(computepower) Dissipa3on Costs Real/non-real3medata


Berkeley Pleiades Processor


52/55

BerkeleyPleiadesProcessor

0.25um 6-level metal CMOS !5.2mm x 6.7mm!1.2 Million transistors!40 MHz at 1V!2 extra supplies: 0.4V, 1.5V!1.5~2 mW power dissipation!

Interface

Reconfigurable

Data-path

FPGA

ARM8 Core


Heterogeneous Programmable Plaorms


53/55

HeterogeneousProgrammablePlaorms

Xilinx Vertex-II Pro

Courtesy Xilinx High-speed I/O

Embedded PowerPc

Embedded memories

Hardwired multipliers

FPGA Fabric


Regularity


54/55

Regularity

DESIGNTHECHIPHIERARCHYINTOIDENTICALORSIMILARMODULESEXTENDEDUSEOFREGULARITYSIMPLIFIESTHEDESIGNPROCESS

REGULARITYCANEXISTATALLLEVELSOFDESIGNHIERARCHY

CircuitLevel:uniformtransistorsizesratherthanmanuallyop3mizingeachdevice

LogicLevel:iden3calgatestructuresratherthancustomizeeverygate

ArchitectureLevel:constructarchitecuresthatuseanumberofiden3calProcessorstructures


Linear Array


55/55

LinearArray

LinearArray:Theanalogworldsanswertothegatearray.Aseriesoftransistors,resistorsandcapacitors,whichare

interconnectedduringthemetalliza3onprocess,toformvarious

analogfunc3ons.Someofthesedeviceswillcontainlimitedlogic

(ormixed-signal)capability,usuallylimitedtoonlyafewthousand

gates.Whilethistechnologysegmenthassurvivedandgrownover

theyears,itisprimarilylimitedtoanalog-onlydesigns.Thistechnologyisavailablefromonlyafewsuppliers,mostofwhich

aresecond-3erplayers.However,itisimportanttonotethata

widevarietyofembeddableandconfigurableanalogcoresare

availablefromawidesupplierbase,includingbothIDMsandIP

providers.

Documents

CHAP2_VLSITechImpl