Computer-System Operation

Chapter 2 Computer System Structure

Computer-System Structure A general-purpose computer system consists of a CPU and a number of device controllers that are connected through a common bus that provides access to the shared memory.

Computer System Operation

Each device controller is in charge of a particular device type (disk drive, video displays etc).

I/O devices and the CPU can execute concurrently. Each device controller has a local buffer.

CPU moves data from/to main memory to/from local buffers

I/O is from the device to local buffer of controller.

Device controller informs CPU that it has finished its operation by causing an interrupt.

Steps in starting an I/O device and getting interrupt

Device and Device Controller

Device Controller Software Relationship

Device Controller Interface

External Interrupts

An external interrupt is a temporal suspension of a process caused by an event external to that process and performed in such a way that the process can be resumed.

I/O

Timer

Hardware failure

Interrupt Handler

A program that determines nature of the interrupt and performs whatever actions are needed

Control is transferred to this program

Generally part of the operating systemInstruction Cycle with Interrupts

CPU checks for interrupts after each instruction.

If no interrupts, then fetch next instruction of current program.

If an interrupt is pending, then suspend execution of the current program. The processor sends an acknowledgement signal to the device that issued the interrupt so that the device can remove its interrupt signal. Interrupt architecture saves the address of the interrupted instruction (and values of other registers). Interrupt transfers control to the interrupt service routine (Interrupt Handler), generally through the interrupt vector, which contains the addresses of all the service routines. Separate segments of code determine what action should be taken for each type of interrupt

Dealing with Multiple Interrupts

Two approaches can be used to deal with multiple interrupts.

1. Disable interrupt while processor is executing an interrupt (i.e. process the interrupts sequentially).

Interrupts remain pending until the processor enables interrupts. After interrupt handler routine completes, the processor checks for additional interrupts.

2. Assign priorities to interrupts. Higher priority interrupts cause lower-priority interrupts to wait. Causes a lower-priority interrupt handler to be interrupted. Example: when input arrives from communication line, it needs to be absorbed quickly to make room for more input.

Traps A trap is a software-generated interrupt caused by an error, for example: arithmetic overflow/underflow

division by zero

execute illegal instruction

reference outside users memory space

Interrupt Driven I/O To start an I/O operation, the CPU loads the appropriate registers within the device controller.

The device controller examines the contents of these registers and determines what action to take and then performs the action. Device controller informs CPU that it has finished its operation by causing an external interrupt.

A disk block read example:

For disk reads, the controller reads the block (one or more sectors) from the derive serially, bit by bit, until the entire block is in the controller internal buffer. It then performs a checksum to verify that no read errors have occurred. The controller sends an interrupt. When the OS starts running, it can read the disk block from the controllers buffer a byte or a word at a time by executing a loop, with each iteration reading one byte or word from the controller device register and storing it in the main memory.

Interrupt Time Line for a Single Process Doing Output

I/O Structure/Methods Once an I/O starts, two courses of actions are possible.

Synchronous I/O After I/O starts, control returns to user program only upon I/O completion. Wait instruction idles the CPU until the next interrupt

Wait loop (contention for memory access).

At most one I/O request is outstanding at a time, no simultaneous I/O processing.

Asynchronous I/O After I/O starts, control returns to user program without waiting for I/O completion. System call is required request to the operating system to allow user to wait for I/O completion.

A Device-status table contains entry for each I/O device indicating its type, address, and state.

Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt. Operating system maintains a wait queue a list of waiting request for each device. When an I/O is complete, an I/O device sends an interrupt. The operating system first determines which I/O device sent the interrupt and then uses the I/O device table to determine the status of the device. If there are additional requests waiting for this device, the operating system starts processing the next request. Finally the control is returned from the I/O interrupt. If a process was waiting for this request to complete, the control can be given back to it.

Two I/O Methods

Device Status Table

Direct Memory Access (DMA) Structure

Recall that with interrupt driven I/O, the CPU can request data from an I/O controller one byte/word at a time which wastes the CPU time. DMA is a scheme which allows block of data transfer from the device to the memory without the intervention of the CPU. After setting up buffers, pointers, and counters for the I/O device by the CPU, the device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention.

Only one interrupt is generated per block, rather than the one interrupt per byte. The OS can only use DMA if the hardware has a DMA controller. The basic operation of the CPU is as follows:

A user program (or OS) requests data transfer

The OS finds a buffer from a pool of buffers (a buffer is 128 to 4096 bytes long depending on the device type).

A device driver sets the DMA controller registers to use the appropriate source and destination addresses and transfer length.

A command to I/O controller is also issued telling it to read data from the disk to its internal buffer and verify the checksum. When the Valid data is in the controllers buffer, DMA can begin. The DMA controller initiates the transfer by issuing a read request over the bus to the disk controller.

The disk controller writes the data to the memory and sends an acknowledgement to the DMA.

The DMA increases the memory address to use and decrements the byte count. If the byte count is still greater than 0, the process is repeated.

When the whole block is transferred, the DMA controller interrupts the CPU to let it know that the transfer is complete.

If both the DMA controller and the CPU want to access the memory at the same time, the CPU is made to wait this is called cycle stealing. Note that the processor is only involved at the beginning and end of the transfer

Storage Structure

Main memory only large storage media that the CPU can access directly. Secondary storage extension of main memory that provides large nonvolatile storage capacity.

Magnetic disks rigid metal or glass platters covered with magnetic recording material

Disk surface is logically divided into tracks, which are subdivided into sectors.

The disk controller determines the logical interaction between the device and the computer.

Storage Hierarchy

Storage systems organized in hierarchy. Speed

Cost

Volatility

Storage-Device HierarchyCaching

Use of high-speed memory to hold recently-accessed data. Requires a cache management policy.

Caching introduces another level in storage hierarchy. This requires data that is simultaneously stored in more than one level to be consistent.

Dual-Mode Operation Sharing system resources requires operating system to ensure that an incorrect program cannot cause other programs to execute incorrectly. Provide hardware support to differentiate between at least two modes of operations.

1. User mode execution done on behalf of a user.

2. Monitor mode (also kernel mode or system mode) execution done on behalf of operating system.

Must ensure that a user program could never gain control of the computer in monitor mode and privileged Instructions can be executed only in monitor mode.

Solution: Mode bit (in Status Register).

Mode bit was added to computer hardware (in Status Register) to indicate the current mode: monitor/system (0) or user (1).

When an interrupt occurs, trap hardware switches to monitor mode, at the correct service routine in the monitor address space - safe!

I/O Protection

All I/O devices need to be protected from wrongdoing by the users.

All I/O instructions are privileged instructions. Thus user cannot issue I/O instructions directly. We must ensure that a user program could never gain control of the computer in monitor mode (i.e., a user program that, as part of its execution, stores a new address in the interrupt vector).

Given the I/O instructions are privileged, how does the user program perform I/O?

Solution: System Calls (from user programs).

System call the method used by a process to request action by the operating system:

Usually takes the form of a trap to a specific location in the interrupt vector. Control passes through the interrupt vector to a service routine in the OS, and the mode bit is set to system mode.

The system verifies that the parameters are correct and legal and executes the request.

Returns control to the instruction following the system call.

Use of A System Call to Perform I/O

Memory Protection

Must provide memory protection at least for the interrupt vector and the interrupt service routines.

In general, OS should be protected from user programs and user programs from each other as well.

In order to have memory protection, add two registers that determine the range of legal addresses a program may access:

Base register holds the smallest legal physical memory address.

Limit register contains the size of the range

Memory outside the defined range is protected. This protection is accomplished by the CPU by comparing every address generated in the user mode with the registers. Any attempt to access monitor memory of other users memory results in a trap to the monitor, which treats the trap as a fatal error.

The base and limit registers can only be loaded by the operating system, which uses a privileged instruction.

Hardware Address ProtectionCPU Protection

A user program must be prevented from getting stuck in an infinite loop and never returning control to the OS. To accomplish this, a timer is used.

A Timer interrupts computer after specified period to ensure operating system maintains control. Timer is decremented every clock tick.

When timer reaches the value 0, an interrupt occurs.

Timer commonly used to implement time sharing.

Time also used to compute the current time.

Load-timer is a privileged instruction.set user mode

user

monitor

Interrupt/fault

Trap instruction is used to switch to monitor mode

PAGE 2.1Prepared by Dr. Amjad Mahmood

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