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© 2012 ANSYS, Inc. August 31, 2012 1 Apache Design, a subsidiary of ANSYS Apache Design, a subsidiary of ANSYS
Challenges for Power, Signal, and Reliability Verification on 3D-IC/Silicon Interposer Designs
Norman Chang, VP and Sr. Product Strategist
© 2012 ANSYS, Inc. August 31, 2012 2 Apache Design, a subsidiary of ANSYS
• 3D-IC/Silicon Interposer Trend
• Multi-die Power Integrity Need
• Stacked Die Reliability Concerns
• Wide-I/O Signal Integrity Issues
• Summary
Outline
© 2012 ANSYS, Inc. August 31, 2012 3 Apache Design, a subsidiary of ANSYS
• 3D-IC & Silicon Interposer competitive advantages
• Higher performance, lower power, and reduced form factor
• Optimal cost structure, reducing porting/design cost
• Better time-to-market through easier and faster integration
3D-IC/Silicon Interposer Trend
Silicon Substrate
DRAM
Logic
Flash RF Passives
CIS Analog MEMS Silicon Interposer
Integration
MPU Flash
Analog
Logic
CIS RF
DRAM
3D-IC with TSV
PCB Integration
© 2012 ANSYS, Inc. August 31, 2012 4 Apache Design, a subsidiary of ANSYS
• Small form factor with economical packaging
– Driven by continuous demand of smaller/faster/higher design integration at a cheaper cost
– Enhanced system performance (higher bandwidth and lower power) via high density interconnect
• High-performance wide-I/O connections to RAMs
– Shorten interconnection from chip-to-chip via SiI
– Low driver/receiver power: Interposer C << package C
• Good fit to silicon process technology
– TSV independent of technology nodes, decoupled from platform technology
– Lower cost organic substrate
Why Silicon Interposer?
© 2012 ANSYS, Inc. August 31, 2012 5 Apache Design, a subsidiary of ANSYS
• Multi-die logic partition for floor plan and P&R
• Test methodology
• TSV-aware DRC/LVS
• TSV extraction
• Power integrity
– Early/sign-off analysis
• Reliability integrity
– Power/thermal/stress/EM/ESD
• Signal integrity
– Wide-I/O jitter analysis
Challenges of Silicon Interposer Design
© 2012 ANSYS, Inc. August 31, 2012 6 Apache Design, a subsidiary of ANSYS
• 3D-IC/Silicon Interposer Trend
• Multi-die Power Integrity Need
• Stacked Die Reliability Concerns
• Wide-I/O Signal Integrity Issues
• Summary
Outline
© 2012 ANSYS, Inc. August 31, 2012 7 Apache Design, a subsidiary of ANSYS
• Shared P/G network for Silicon Interposer designs calls for multi-die power integrity analysis
• Simultaneous switching activity on multi-die impacts IR/DvD on individual die
Stacked Die Power Integrity Analysis
Memory
Substrate
Logic
Substrate
Si Interposer Substrate
Package
TSV
front_side
ubump
back_side
ubump
feedthru net
( chip IOs)
P/G
Backside metal RDL routing
Signal
© 2012 ANSYS, Inc. August 31, 2012 8 Apache Design, a subsidiary of ANSYS
• Input multi-die design and corresponding process data (can be of different technologies), all at once
• Impact from shared P/G nets and decap in interposer die can be factored into memory and logic die
Concurrent Multi-die Voltage Drop Analysis
RedHawk Concurrent Analysis
Logic Die
LEF/DEF, N65 iRCX
Memory Die
LEF/DEF, N40 iRCX
Silicon Interposer
LEF/DEF, N65 iRCX Package Netlist
Memory Die Logic Die
Silicon Interposer
DvD Map of 3-die concurrent analysis
Memory Die Logic Die
Silicon Interposer
DvD Map of 3-die concurrent analysis
© 2012 ANSYS, Inc. August 31, 2012 9 Apache Design, a subsidiary of ANSYS
• Most suitable when one die is external without the complete design database
• Chip Power Model (CPM™) is a die model with R/L/C network and current profile, generated by RedHawk™ or Totem™
• Enables simple hand-off and fast turn-around-time
CPM-based Multi-die IR/DvD Analysis
RedHawk
Logic Die LEF/DEF, N65 iRCX
Silicon Interposer
LEF/DEF, N65 iRCX
Package Netlist
Memory Die Logic Die
Silicon Interposer
DvD Map of 3 - die concurrent analysis
Logic Die
Silicon Interposer
CPM
Memory Die LEF/DEF, N40 iRCX
RedHawk
/Totem
© 2012 ANSYS, Inc. August 31, 2012 10 Apache Design, a subsidiary of ANSYS
• Connected in a face2back manner
• “Top die” connects to “package” through “bottom die”
• Bottom die PDN contains TSVs that connect its M1 to back-side metal, which connects to top die using “copper pillars”
• RLCK model of package used
3D-IC Test Case Layout
© 2012 ANSYS, Inc. August 31, 2012 11 Apache Design, a subsidiary of ANSYS
CO
NC
UR
REN
T M
OD
EL B
ASE
D
Layout view of both
die in concurrent
mode
3D-IC Test Case Description
Model of top die
hooked to bottom
die layout
© 2012 ANSYS, Inc. August 31, 2012 12 Apache Design, a subsidiary of ANSYS
Case A Case B
Power Top Die 1.00 1.00
Power Bottom Die 0.33 0.33
Voltage Drop Top Die 10.94 11.91
Votage Drop Bottom Die 4.67 3.7
GND bounce Top Die 5.03 6.57
GND bounce Bottom Die 2.31 1.00
Voltage drops on two die in two cases: Case A: top half of the top die is active
Case B: left half of the top die is active
Bottom Die is affected by operation of the Top Die!
Top Die Demand Variation Transient Analysis
Ref: Singh et al, “Design and optimization of a power delivery network for 3D stacked die designs”, DesignCon 2011.
© 2012 ANSYS, Inc. August 31, 2012 13 Apache Design, a subsidiary of ANSYS
• 3D-IC/Silicon Interposer Trend
• Multi-die Power Integrity Need
• Stacked Die Reliability Concerns
• Wide-I/O Signal Integrity Issues
• Summary
Outline
© 2012 ANSYS, Inc. August 31, 2012 14 Apache Design, a subsidiary of ANSYS
• Strong power-thermal interaction, especially on leakage power
• Thermal distribution more complicated due to multi-die interaction
• Thermal-induced stress more severe due to different process technologies
• Temperature-dependent EM limit changes significantly at 28nm or below technologies
• ESD is worse or similar on HBM/CDM models
Multi-die Reliability Concerns
© 2012 ANSYS, Inc. August 31, 2012 15 Apache Design, a subsidiary of ANSYS
• Power-Thermal Iterations
Power-Thermal (PT) Loop
Iteration
Power-Thermal Loop
82.4
97.0
106.8
113.4
117.9 118.8
83.9
96.0
103.5108.6
112.0 112.3
60
70
80
90
100
110
120
130
0 1 2 3 4 5 6 7
Iteration
70
80
90
100
110
120
130
140
Temperature
Power
(oC) (W)
Note: Total power and maximum temperature on chip
Through Co-analysis:
• Power/Thermal Convergence
• Thermal Run-away
© 2012 ANSYS, Inc. August 31, 2012 16 Apache Design, a subsidiary of ANSYS
Power-Thermal Convergence Using Sentinel-TI
External Heat Sink
MoldingDie
Die Attach
Ambient
Temperature
Still Air
or
Air Speed
Mask
HS Attach
Substrate
PCB
Wire
Solder
Updated
Temperature
CTM from RedHawk/Totem
Look-up power map from
temperature map
Updated
Power
© 2012 ANSYS, Inc. August 31, 2012 17 Apache Design, a subsidiary of ANSYS
Test Case with Silicon Interposer
Stacked Silicon Technology
(courtesy of Xilinx paper) TSMC Ref 12 Test Case
© 2012 ANSYS, Inc. August 31, 2012 18 Apache Design, a subsidiary of ANSYS
Thermal Analysis of 2.5D Silicon Interposer Design
Memory die’s thermal map is affected by Logic die of higher power (0.12W from logic vs. 0.005W from memory)
Memory Die Logic Die
Power Density
Temperature
bump, ubump,
and TSV
© 2012 ANSYS, Inc. August 31, 2012 19 Apache Design, a subsidiary of ANSYS
Example of Power Density Map and Layer Thermal Responses with CTM-based Flow
Self-heating
Power Density
© 2012 ANSYS, Inc. August 31, 2012 20 Apache Design, a subsidiary of ANSYS
3D-IC Thermal Analysis Flow: CTM-based Power-Thermal Co-analysis
CTM: Chip Thermal Model
Temp-dependent power database
RedHawk Icepak
Package Design
(mcm, sip)
Thermal
Profile
Thermal
Co-analysis
Thermal/Stress
Analysis
IC DESIGN
IC Power
Integrity Analysis
CTM
Generation CTM
P
T
Power update
R Extraction
EM limit update Thermal
Profile
Memory
Substrate
SoC
Substrate
Si InterposerSubstrate
Package
TSV
front_side
ubump
back_side
ubump
feedthru net
( chip IOs) inter
net
Backside metalRDL routing
JA/JB/JC
Delphi
Power Map
System
Thermal
Tools
Sentinel-TI
© 2012 ANSYS, Inc. August 31, 2012 21 Apache Design, a subsidiary of ANSYS
• Where does deformation/stress come from?
– Differential thermal expansion due to on-chip temperature increase
– Silicon chips have very low thermal expansion coefficients and are pushed and pulled by surrounding components
Deformation/Stress in Packages
2.6 ppm/C
12.4 ppm/C
12.7 ppm/C
17.4 ppm/C
Expansion
movements
ppm = mm/mm x 106
Board
Substrate
Mold Die
ppm= mm/mm x10-6
© 2012 ANSYS, Inc. August 31, 2012 22 Apache Design, a subsidiary of ANSYS
• Higher stress on logic die due to higher power dissipation and temperature
• Resulting in more severe thermal to relative relative Silicon Interposer
Multi-die Stress Analysis
Tmax= 58.70 C Tmax= 55.95 C
© 2012 ANSYS, Inc. August 31, 2012 23 Apache Design, a subsidiary of ANSYS
Thermal Impact on Electromigration
© 2012 ANSYS, Inc. August 31, 2012 24 Apache Design, a subsidiary of ANSYS
Thermal Aware Power and Signal EM
Traditional Analysis
constant “high” T Thermal-aware Analysis
based on “actual” T Signal EM Thermal-aware results
Power EM Maps
Thermal-aware EM analysis avoids false violations and over-design
© 2012 ANSYS, Inc. August 31, 2012 25 Apache Design, a subsidiary of ANSYS
3D-IC – HBM (better due to TSV slows down
the discharging rate but can be worse on the condition below)
– CDM (slightly worse due to more charges)
2.5D Silicon Interposer – HBM (similar due to common TSV path) – CDM (worse due to larger package)
ESD Comparison between 3D-IC / Silicon Interposer Design and Single Die Package
Bottom Die Top Die
VSS
si
g
Powe
r
Clam
p1
VDD
Power
Clamp
2
TSV
TSV
VDD
VSS
3D-IC HBM
Vt1 > Vclamp + I_hbm * R_hbm_path
Vclamp
+
_
Vt1
+ D1 D3 D2 D4
© 2012 ANSYS, Inc. August 31, 2012 26 Apache Design, a subsidiary of ANSYS
• 3D-IC/Silicon Interposer Trend
• Multi-die Power Integrity Need
• Stacked Die Reliability Concerns
• Wide-I/O Signal Integrity Issues
• Summary
Outline
© 2012 ANSYS, Inc. August 31, 2012 27 Apache Design, a subsidiary of ANSYS
• Chips face down, Interposer face up
• Interposer connects:
– To chip μbumps
– Among μbumps and TSVs via front-side wiring
– To package via TSVs + C4 solder balls on back-side
– Parallel bus channel (1K-8K bits)
Wide-I/O Example: SoC + RAM on Interposer
SoC RAM
Package
Interposer
rails via TSV signals via TSV
SoC RAM
ubumps
C4s
RAM interface internal to
Interposer
usually separate power domains
© 2012 ANSYS, Inc. August 31, 2012 28 Apache Design, a subsidiary of ANSYS
• SoC drivers and receivers + core noise
• Interposer rails, signals nets, passives
• IBIS or other RAM model
• Stimulus
Modeling Wide-I/O Jitter Through Interposer S
timul
us
Interposer rail
parasitics
SoC SSO + core
model
Interposer
signal
parasitics
RAM IBIS or
other load and
termination
Package /
PCB
+
– +
–
A
A
V
A
A
© 2012 ANSYS, Inc. August 31, 2012 29 Apache Design, a subsidiary of ANSYS
Jitter on SiI Parallel Wide-I/O Bus Example
m_data2[12]: most
affected by x-talk
m_q6[6]: slowest
All switch 010
victim:
m_data2[3]
aggressor:
m_data2[4]
© 2012 ANSYS, Inc. August 31, 2012 30 Apache Design, a subsidiary of ANSYS
• Increasing number of shared P/G ports require analysis of the entire 3D-IC (multi-die, package) for accurate power integrity
• Concurrent simulation method or CPM-based analysis method is possible due to availability of design data
• Reliability issues, including power/thermal/stress/EM/ESD are getting more serious for 3D-IC or Silicon Interposer designs
• Wide-I/O with Silicon Interposer will likely become a major platform for high performance logic<->memory designs, and channel jitter analysis is much needed
Summary