Ch.8 Flip-Flops and Related Devices

Ch.8 Flip-Flops and Related Devices

Latch Edge-Triggered and Master-Slave Flip-

Flops Flip-Flop Operating Characteristics Flip-Flop Applications One-Shots and the 555 Timer Troubleshooting Programmable Logic: Registered

Operation Latches and Flip-Flops Using VHDL

2

Information Security Lab.

Introduction

fn m

Y=f(X)

XX: the finite set of input symbols

Y: the finite set of output symbols

f: a Boolean function for the output

Digital Logic (1) Combinational Logic Circuit, (2) Sequential Logic Circuit

Combinational Logic Circuit

3


Sequential Logic Circuit

Latches, Flip-flopsRAM, etc.

4


X : the finite set of input symbolsY : the finite set of output symbolsS : the finite set of status symbols, S 2K

f : a Boolean functions(logic diagram) for output Yg : a Boolean functions for next state S+

f gn m

Y=f(X,S)X

StatusS

S+=g(X,S)Storage Device

K

Finite State Machine

5


6


1.Bistable Multivibrator: latches and flip-flops Has two stable states

2.Monostable Multivibrator: one-shot Has one stable state

3.Astable Multivibrator: clock Has no stable state

Latch / flip-flop

Q : ‘1’ or ‘0’

Q’

One-shot

Q

Q’ Clock

Multivibrators

7


Latches

•The S-R (Set-Reset) Latch– A type of bistable multivibrator– Store one bit

Figure 8-1 Two versions of SET-RESET (S-R) latches. Open file F08-01 and verify the operation of both latches.

( 걸쇄 , 빗장 )

8


QQ’=1

Normally HIGH input

9


InputS’ R’

OutputQ Q’

Comments

0 0 1 1 Not allowed

0 1 1 0 Set

1 0 0 1 Reset

1 1 Q Q’ No change

10


Figure A-13 The 74xx279 quad S’-R’ latch.

11


Application Example : Latches

•The Latch as a Contact-Bounce Eliminator

S’: 1 1 1 1 • • • 1 0 1 0 0 • • •

R’: 0 1 0 1 • • • 1 1 1 1 1 • • •

No change

12


The Gated S-R Latch

•Requires an enable input(EN) (G is also used to designate an enable input)

Figure 8-7 A gated S-R latch.

0

1

1

13


14


The Gated D Latch

15


Figure A-14 The 74xx75 quad gated D latches.

16


Edge-Triggered Flip-Flops

• Edge-triggered flip-flop changes state either at the positive edge(or rising edge) or at the negative edge(falling edge) of clock pulse and is sensitive to its inputs only at this transition of clock

Figure 8-11 Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered).

+ T-flip-flop

17


The Edge-Triggered S-R Flip-flop

18


InputS R

OutputQ Q’

Comments


0 1 1 0 Set

1 0 0 1 Reset

1 1 ? ? Not allowed

19


•A method of Edge-Triggering

20


21


The Edge-Triggered D Flip-flop

Figure 8-18 A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter/ truth table

InputD Clk

OutputQ Q’

Comments

0 0 1 Reset

1 1 0 Set

22


The Edge-Triggered J-K Flip-flop

Figure 8-20 A simplified logic diagram for a positive edge-triggered J-K flip-flop.

Figure 8-21 Transitions illustrating the toggle operation when J=1 and K=1.

toggle

23


InputJ K Clk

OutputQ Q’

Comments


0 1 0 1 Reset

1 0 1 0 Set

1 1 Q’ Q Toggle

Ex 8-7)

24


State Equation of J-K Flip-flop

InputJ K Q(t)

OutputQ(t+1)

Comments

0 0 0 0 No change

0 0 1 1 No change

0 1 0 0 Reset

0 1 1 0 Reset

1 0 0 1 Set

1 0 1 1 Set

1 1 0 1 Toggle

1 1 1 0 Toggle

JKQ(t) 00 01 11 10

0 1 1

1 1 1

State Equation Q(t+1) = JQ(t)’ + K’Q(t)

25


Ex 8-6)

26


The Edge-Triggered T Flip-flop

T

InputT Clk

OutputQ Q’

Comments

0 Q Q’ No change

1 Q’ Q Toggle

Clk

T

Q

27


Asynchronous Preset and Clear Inputs

•An active preset input makes the Q output high(set)

•An active clear input makes the Q output low(reset)

Figure 8-24 Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.

28


Ex 8-8)

29


toggle

Ex 8-9) For a negative edge-triggered flip-flop, determine the Q output waveform

30


Figure A-14 The 74xx75 quad gated D latches.

31


Figure A-15 Logic symbols for the 74xx74 dual positive edge-triggered D flip-flops.

32


Figure A-16 Logic symbols for the 74xx112 dual negative edge-triggered J-K flip-flops.

33


Master-Slave Flip-Flops

•The pulse-Triggered Master-Slave J-K Flip-flop

Figure 8-28 Basic logic diagram for a master-slave J-K flip-flop.

master slave

34


ToggleQ’ Q1 1 Set1 01 0

Reset 0 10 1 No changeQ Q’0 0

CommentsOutputQ Q’

InputJ K Clk

Ex 8-9) For a active LOW clock master-slave J-K flip-flop, determine the Q output waveform

35


Flip-Flop Operating Characteristics

•Propagation Delay times1.tPLH as measured from the triggering edge of

clock pulse to the LOW-to-HIGH transition of the output

2.tPHL as measured from the triggering edge of clock pulse to the HIGH-to-LOW transition of the output

Figure 8--31 Propagation delays, clock to output.

36


3. tPLH as measured from the triggering edge of the preset input to the LOW-to-HIGH transition of the output

4. tPHL as measured from the triggering edge of the clear input to the HIGH-to-LOW transition of the output

Figure 8-32 Propagation delays, preset input to output and clear input to output.

37


Set-up Time/ Hold Time

Figure 8--33 Set-up time (ts). The logic level must be present on the D input for a time equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry.Figure 8-34 Hold time (th). The logic level must remain on the D input for a time equal to or greater than th after the triggering edge of the clock pulse for reliable data entry.

38


Maximum Clock Frequency

•The maximum clock frequency(fMAX): the highest rate at which a flip-flop can be reliably triggered

– is determined by propagation delay times, se-up, and hold times

•Pulse Widths(tW)– is determined by se-up, and hold times

•Power DissipationP = VCC X ICC

Ex) power requirement: 5V X 5mA = 25mW/flip-flop 10 flip-flops require 25 X 10 =250 (mW) and 50 mA

39


ParameterCMOS TTL

74HC74A 74AHC74 74LS74A 74F74tPHL(Clk to Q) 17 ns 4.6 ns 40 ns 6.8 ns

tPLH(Clk to Q) 17 ns 4.6 ns 25 ns 8.0 ns

tPHL(Clr’ to Q) 18 ns 4.8 ns 40 ns 9.0 ns

tPLH(Pre’ to Q) 18 ns 4.8 ns 25 ns 6.1 ns

ts(set-up time) 14 ns 5.0 ns 20 ns 2.0 ns

th(hold time) 3.0 ns 0.5 ns 5 ns 1.0 ns

tW(Clk HIGH) 10 ns 5.0 ns 25 ns 4.0 ns

tW(Clk LOW) 10 ns 5.0 ns 25 ns 5.0 ns

tW(Clr’/Pre’) 10 ns 5.0 ns 25 ns 4.0 ns

fmax 35 MHz 170 MHz 25 MHz 100 MHz

Power, quiescent

0.012 mW 1.1 mW

Power, 50% duty

44 mW 88 mW

Comparison of operating parameters for four IC families of flip=flops of the same type at 25°C

40


Flip-Flop Applications

Application Examples1.Parallel Data Storage(register stores a word)

0

1

1

0Figure 8-35 Example of flip-flops used in a basic register for parallel data storage.

41


2. Frequency Division( 주파수 분주 )

Figure 8-36 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.

Figure 8-37 Example of two J-K flip-flops used to divide the clock frequency by 4. QA is one-half and QB is one-fourth the frequency of CLK.

42


Ex 8-11) Develop the fout waveform when fin is 8 kHz.

fin/4fin/8

fin/2

Sol)8KHz

4KHz

2KHz

1KHz

43


3. Counting(asynchronous: same as frequency division)

Figure 8-40 Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.

44


Ex 8-12) Determine the output waveforms for each output of flip-flops

Sol)

45


One-Shots(monostable multivibrator)

•A one-shot produces a single pulse each time it is triggered.

Figure 8-43 A simple one-shot circuit.

Figure 8-44 Basic one-shot logic symbols. CX and RX stand for external components.

td RC(time constant)

46


Figure 8-45 Nonretriggerable one-shot action.

Figure 8-46 Retriggerable one-shot action.

47


Application Example

Figure 8-47 A sequential timing circuit using three one-shots.

48


Figure A-17 Logic symbols for the 74121 nonretriggerable one-shot.

49


Figure A-18 Three ways to set the pulse width of a 74121.

50


Figure A-20 Logic symbol for the 74xx122 retriggerable one-shot.

51


The 555 Timer(astable multivibrator)

Figure 8-48 Internal functional diagram of a 555 timer (pin numbers are in parenthesis).

Monostable(one-shot) Operation

tW=1.1R1C1

Figure 8-49 The 555 timer connected as a one-shot.

52


Figure 8-50 One-shot operation of the 555 timer.

53


Astable Operation

Figure 8-51 The 555 timer connected as an astable multivibrator (oscillator).

Figure 8-52 Operation of the 555 timer in the astable mode.

54


f= 1.44/((R1+2R2)C1)

R2>R1, tH = 0.7(R2 + R1)C1 , tL = 0.7R2C1

T = tH + tL = 0.7(R1 + 2R2)C1

Duty cycle = tH/T = tH/(tH+tL) = (R1+R2)/(R1+2R2)100%

Figure 8-53 Frequency of oscillation as a function of C1 and R1 + 2R2. The sloped lines are values of R1 + 2R2.

tH tH

tL tLtLtL

55


Ex 8-14) Determine the frequency and duty cycle

Sol) f= 1.44/((R1+2R2)C1) = 1.44/((2.2k+2x4.7k)0.022F)= 5.64 kHzDuty cycle= (R1+R2)/(R1+2R2)100%=(2.2k + 4.7k)/(2.2k +2X4.7k)100% =

59.5%

56


Troubleshooting

•Glitch problem in two-phase clock generator

Figure 8-56 Two-phase clock generator with ideal waveforms.

57


Figure 8-57 Logic analyzer displays for the circuit in Figure 8-56.

58


Figure 8-58 Two-phase clock generator using negative edge-triggered flip-flop to eliminate glitches.

59


Programmable Logic: Registered Operation

•The Registered Logic in a Programmable Logic Device

Figure 8-59 Generic CPLD/FPGA registered logic.

60


Figure 8-60 Combinational(a) and registered(b) output configurations.

61


Latches and flip-flops using VHDL

• The S-R latch can be either high or low inputs• Q and QNOT are both inputs and outputs,

VHDL has a bi-directional mode inout which is used in the port statement

port( S, R: in std_logic; Q, Qnot: inout std_logic);

62


S-R latch in VHDL

library ieee;use ieee.std_logic-1164.all;entity SRlatch is port( S, R: in std_logic; Q, Qnot: inout std_logic);end entity Srlatch;architecture Latch_Operation of SRlatch isbegin process(S,R) is begin Q <= Qnot nor S; Qnot <= Q nor R; end process;end architecture Latch_Operation;

63


S-R latch to S-R Flip-flop

•The S-R flip-flop may use a clock pulse•The clock pulse needs to be an edge trigger

event•Using the VHDL statement wait until rising_edge(clock) will cause the program to be driven by the clock

64


library ieee;use ieee.std_logic-1164.all;entity SRFlipFlop is port(S, R, Clock: in std_logic; Q, QNot: inout std_logic);end entity SRFlipFlop;architecture FlipFlopBehavior of SRFlipFlop isbegin process(S,R,Clock) is begin

wait until rising_edge(Clock);if S=‘1’ and R=‘0’ then Q<=‘1’;elsif S=‘0’ and R=‘1’ then Q<=‘0’;else Q<=Q;

end ifQNot<= not Q;

end process;end architecture FlipFlopBehavior;

VHDL for Rising edge-triggered, active high input S-R Flip-flop

65


Figure 8-64 S-R flip-flop simulation waveform.

66


VHDL for Rising edge-triggered, active high input D Flip-flop

library ieee;use ieee.std_logic-1164.all;entity DFlipFlop is port(D, Clock: in std_logic; Q, QNot: inout std_logic);end entity SRFlipFlop;

architecture FlipFlopBehavior of DFlipFlop isbegin process(D, Clock) is begin

wait until rising_edge(Clock);if D=‘1’ then Q<=‘1’;else Q<=Q;

end ifQNot<= not Q;

end process;end architecture FlipFlopBehavior;

67


Re-usable packages(Programs)

•Make S-R latch a package and use it many times

•Using a VHDL package allows the use of the S-R latch in the construction of other logic devices–Refer the VHDL code on the next page(p.68)

Ex 8-18) Write the VHDL code to implement an active-LOW input J’-K’ flip-flop with positive edge-triggering using the previously defined package, SRPackage.J’ Q

F/F

K’ Q’

68


library ieee;use ieee.std_logic-1164.all;

package SRPackage isprocedure ActiveLowSRlatch(SNot, RNot: in std_logic;

Q, QNot: inout std_logic);end SRPackage;

package body SRPackage isprocedure ActiveLowSRlatch(SNot, RNot: in std_logic;

Q, QNot: inout std_logic) isbegin

if SNot=‘1’ and RNot=‘0’ then Q:=‘0’; QNot:=‘1’;elsif SNot=‘0’ and RNot=‘1’ then Q:=‘1’; QNot:=‘0’;elsif SNot=‘0’ and RNot=‘0’ then Q:=QNot; QNot:=

not Q;end if -- not included “11: no changed” condition

end ActiveLowSRlatch;end SRPackage;

Toggle replaces invalid S’-R’

condition

69


library ieee;use ieee.std_logic-1164.all;use work.SRPackage.all;

entity ActiveLowJK isport(JNot, Knot, Clock: in std_logic; X, Y: inout std_logic);

end entity ActiveLowJK;

architecture JKBehavior of ActiveLowJK isbegin

process(JNot, KNot)variable V1, V2: std_logic;begin

wait until rising_edge(Clock);FF1: ActiveLowSRlatch(SNot=>JNot, RNot=>Knot, Q=>V1,

QNot=>V2);X<= V1;Y<= V2;

end process;end JKBehavior;

V1

V2

J’ S’ Q X

F/F

K’ R’ Q’ Y

Sol) the VHDL code for active-LOW input J’-K’ flip-flop with positive edge-triggering using the previously defined package, SRPackage in Ex 8-18.

Procedure call

70


Figure 8-67 J’-K’ flip-flop simulated waveforms. Outputs X and Y are initialized to valid states after the first clock pulse.

71


J-K Flip-Flop Components

• In example 8-18, a modified S-R latch package was used to define the J-K flip-flop

• The J-K flip-flop will be made into a component for used in a frequency dividercomponent JKFlipFlop is

port( J,K,Clock: in std_logic; Q: inout std_logic);end component JKFlipFlop;

VHDL keyword buffer•Similar to in out and inout used in a port

statement•buffer is unidirectionalport(clock: in std_logic; Qa, Qb, Fout: buffer

std_logic);

72


Ex 8-19) Write a VHDL description of the frequency divider in figure below using previously defined component JKFlipFlop and develop the fout waveform

buffer

73


Sol) library ieee;use ieee.std_logic-1164.all;

entity FreqDivider isport(clock: in std_logic; Qa, Qb, fout: buffer std_logic);

end entity FreqDivider;

architecture FreqDivBehavior of FreqDivider iscomponent JKFlipFlop is

port(J, K, Clock: in std_logic; Q: inout std_logic);

end component JKFlipFlop;signal I: std_logicbegin

I<=‘1’;FFA: JKFlipFlop port map(J=>I, K=>I, Clock=>clock,

Q=>Qa);FFB: JKFlipFlop port map(J=>I, K=>I, Clock=>Qa, Q=>Qb);

FFC: JKFlipFlop port map(J=>I, K=>I, Clock=>Qb, Q=> fout);end architecture FreqDivBehavior;

A unique user defined label is assigned to each component

installation

74


Relation of VHDL software to HW Implementation

• Use working code to make more complex code• Complex operations can often be better

described using the behavioral approach• The VHDL complier will decide how to

implement the code• This allows the code to be usable on other

programmable devices

VHDL Approach Model and its Abstraction

1.Structural model2.Dataflow model3.Behavioral model

Abstraction level : HIGH

75


Digital System Application

Traffic Light Controller System•Requirements for the Timing Circuits

76


•Frequency divider(divide by 210)–25.175/(210)MHz = 25175/1024 KHz=24.585 KHz

77


library ieee;use ieee.std_logic-1164.all;

entity FrequencyDivider isport(clock: in std_logic; fout: buffer std_logic);

end entity FrequencyDivider;

architecture FreqDivBehavior of FrequencyDivider is

signal Qa, Qb, • • • , Qi, I : std_logic;component JKFlipFlop is

port(J, K, Clock: in std_logic; Q, QNot: inout std_logic);

end component JKFlipFlop;begin

I<=‘1’;FF1: JKFlipFlop port map(J=>I, K=>I, Clock=>clock,

Q=>Qa);FF2: JKFlipFlop port map(J=>I, K=>I, Clock=>Qa, Q=>Qb);

• • • • • • • • • FF10: JKFlipFlop port map(J=>I, K=>I, Clock=>Qi, Q=> fout);end architecture FreqDivBehavior;

J QClock

K QNot

J QClock

K QNot

J QClock

K QNot• • • •

Qa Qb Qi fout‘1’

78


library ieee;use ieee.std_logic-1164.all;entity Timer is

port(Enable, Clock: in std_logic; SetCount: in integer; Qout : buffer std_logic);end entity Timer;architecture TimerCounter of Timer isbegin

process(Enable, Clock)variable Cnt: integer;begin

if(Clock’Event and Clock=‘1’) thenif Enable=‘0’ then

Cnt:=0; Qout<=‘1’;elsif Cnt=SetCount-1 then

Qout<=‘0’;else

Cnt:=Cnt+1;end if;

end if;end process;

end architecture TimerCounter;

VHDL Code for Variable Count Timer

SetCount QoutEnable

Clock

79


State Equations for Flip-Flops(***)

•The logic equations for the next state of the flip-flop Q(t+1) = f(X, Q(t)), where X is the flip-flop input and Q(t) is the current state of the flip-flop

D flip-flop T flip-flopsInputD Q(t)

OutputQ(t+1)

0 0 0

0 1 0

1 0 1

1 1 1

Q(t+1) = D InputT Q(t)

OutputQ(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

Q(t+1) = T’Q(t) +TQ(t)’ = TQ(t)

80


J-K Flip-flop

InputJ K Q(t)

OutputQ(t+1)

Comments

0 0 0 0 No change

0 0 1 1 No change

0 1 0 0 Reset

0 1 1 0 Reset

1 0 0 1 Set

1 0 1 1 Set

1 1 0 1 Toggle

1 1 1 0 Toggle

JKQ(t) 00 01 11 10

0 1 1

1 1 1

State Equation(J-K flip-flop)

Q(t+1) = JQ(t)’ + K’Q(t)

How is it for S-R flip-flop?

81


•The input conditions for the state transitions of each flip-flop

Excitation Tables for D, T, J-K, and S-R flip-flops

Excitation(or Transition) Tables for Flip-Flops(***)

State ChangeQt Qt+1

F/F input

D

0 0 0

0 1 1

1 0 0

1 1 1

State ChangeQt Qt+1

F/F input

T

0 0 0

0 1 1

1 0 1

1 1 0

State ChangeQt Qt+1

F/F input J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

State ChangeQt Qt+1

F/F input S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0SR=1 : not

allowedEx) State: 00 J K: 0 0 0 1 0X

82


Summary

• Symbols for latches and flip-flops

+ T type

83


Summary ( 계속 )

•Multivibrators– Bistable(latches and flip-flops): two stable states – Monostable Multivibrator(one-shot or single-shot): one

stable state, time Ext R and Ext C– Astable Multivibrator(clock or oscillator): no stable state,

time Ext R and Ext C•Latches: normally depends on asynchronous

inputs•Edge-triggered flip-flops•Pulse-triggered master-slave flip-flops•Asynchronous inputs for preset or clear the flip-

flops•VHDL

– inout(a bidirectional port), wait until rising_edge(clock), wait until falling_edge(clock), buffer(a port read and updated)

•State equations and Excitation tables for flip-flops(*)

End of Chapter 8

Documents

Ch.8 Flip-Flops and Related Devices