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Ch. 5. Junctions. Prof. Yun-Heub Song. Study of Previous Chapters. Chapter 3~4 1. The Fermi-Dirac Distribution Function 2. The Fermi Function Applied to Semiconductors 3. Schematic Diagrams 4. Diffusion and Drift of Carriers - PowerPoint PPT Presentation
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Solid State Electronic Devices
Ch. 5. JunctionsCh. 5. Junctions
Prof. Yun-Heub SongProf. Yun-Heub Song
Solid State Electronic Devices
Study of Previous ChaptersStudy of Previous Chapters
Chapter 3~4Chapter 3~4
1. The Fermi-Dirac Distribution Function
2. The Fermi Function Applied to Semiconductors
3. Schematic Diagrams
4. Diffusion and Drift of Carriers
5. Semiconductor in an Electric Field
Solid State Electronic Devices
f(E)
1
1/2
T=0K
T1
T2
T2>T1
EF
E
f Ee E E kTF
( )( )/
1
1
Energy state Density :
N(E)
E
2/12/3
22
2
2
1)( E
mEN
E
ECdEENEfn )()(0
VE
EdEENEfp )()](1[0
The Fermi-Dirac Distribution FunctionThe Fermi-Dirac Distribution Function
Solid State Electronic Devices
The Fermi Function Applied to SemiconductorsThe Fermi Function Applied to Semiconductors
Solid State Electronic Devices
Schematic DiagramsSchematic Diagrams
Solid State Electronic Devices
If carriers is in the electric fields,
J x q n x x qDdn x
dx
J x q p x x qDdp x
dx
n n n
p p p
( ) ( ) ( )( )
( ) ( ) ( )( )
p (diff.) and p (drift.)
Jp (diff.) and Jp (drift.) n (diff.)
n(drift.)
Jn (diff.)
Jn (drift.)
Diffusion and Drift of CarriersDiffusion and Drift of Carriers
E(x)
n(x)
p(x)
Solid State Electronic Devices
Ex) If injecting donor in order that Nd= N0exp(-ax) relation is satisfied, E(x) ?
Equilibrium State : Flow of current is ‘0(zero)’
n(x)
N0
n ix
EC
EF
EiEv
x
aq
kT
eN
eaN
q
kT
dx
dn
n
DxE
ax
ax
n
n
0
0 )()(
→ Electrons move through direction reducing energy in E-field
dx
dE
E
dx
d
dx
xdVxE ii 1
)(
)()(
Built in electric field
q n x x qDdn x
dxn n ( ) ( )( )
0
Semiconductor in an Electric FieldSemiconductor in an Electric Field
Solid State Electronic Devices
ContentsContents
Ch. 5. JunctionCh. 5. Junctionss
1. Fabrication of p-n Junctions
2. Equilibrium Conditions
3. Forward- and Reverse-Biased Junctions ; Steady State Conditions
4. Reverse-Bias Breakdown
5. Transient and A-C Conditions
6. Deviations from the Simple Theory
7. Metal-Semiconductor Junctions
8. Hetero-Junctions
Solid State Electronic Devices
1.1. Thermal Oxidation1.1. Thermal Oxidation
Many fabrication steps involve heating up the
wafer in order to enhance a chemical process.
Fig. 1. Silicon wafers being loaded into a furnace
The overall reactions that occur during oxidation
Si + O2 → SiO2 (dry oxidation)
Si + 2H2O → SiO2 + 2H2 (wet oxidation)
1. 44% of Si is consumed from the surface of
the substrate.
2. One of the very important reasons why Si
integrated circuits exist is that a stable
thermal oxide can be grown on Si with
excellent interface electrical properties.
Solid State Electronic Devices
Dry and Wet Thermal Oxide Grown on SiDry and Wet Thermal Oxide Grown on Si
Oxide thickness depends on process time and temperature.
(Refered to appendix VI(534~535 page), textbook)
Solid State Electronic Devices
1.2. Diffusion1.2. Diffusion
Dopants such as B, P or As are introduced into
wafers in a high temp. diffusion furnace.
Fig. 2. Impurity concentration profile
D = D0 exp-(EA/kT)
D0 is a constant depending on the material and dopant
EA is the activation energy
- Calculating methods : Gaussian and erfc
1. Gaussian : The source of dopant atoms at the
surface of the sample is limited.
2. erfc : The dopant atoms are supplied
continuously, such that the concentration at
the surface is maintained at a constant value.
The diffusivity of dopants in solids,
Solid State Electronic Devices
1.3. Rapid Thermal Processing1.3. Rapid Thermal Processing
• A key parameter in all thermal processing
steps is Dt. • Because an excessive Dt product leads to loss
of control over compact doping profiles,
which is detrimental to ultra-small devices,
we try to minimize this quantity.• In furnace processing, Dt is minimized by
operating at as low a temp. as feasible so that
D is small.• RTP operates at higher temperatures
(~1,000 ) but does so for only a few ℃seconds(compared to minutes or hours in a
furnace).Fig. 3. Schematic diagram of a rapid
thermal processor
Solid State Electronic Devices
1.4. Ion Implantation1.4. Ion Implantation
A beam of impurity ions is accelerated to kinetic
energies ranging from several keV to several MeV
and is directed onto the surface of the semiconductor.
Fig. 4. Distributions of implanted impurities
Mainly ParametersMainly Parameters
- Rp : As the impurity atoms enter the crystal, they
give up their energy to the lattice in collisions and
finally come to rest at some average penetration
depth, we called the projected range.
- △Rp : It called the straggle, measures the half-width
of the distribution at peak of Fig. 4(a). - Both parameters increase with increasing
implantation energy. By performing several
implantations at different energies, it is possible to
synthesize a desired impurity distribution, such as
the uniformly doped region in Fig. 4 (b).
Solid State Electronic Devices
1.4. Ion Implantation1.4. Ion Implantation
Fig. 5. Schematic diagram of an ion implantation system
2
2
1exp
2)(
p
p
p R
Rx
RxN
Gaussian Formula
Solid State Electronic Devices
1.5. Chemical Vapor Deposition(CVD)1.5. Chemical Vapor Deposition(CVD)
Fig. 6. Low pressure chemical vapor deposition(LPCVD) reactor
- SiO2 films can also be formed by CVD.
1. Thermal oxidation consumes Si from the substrate, and very high temperatures
are required.
2. CVD of SiO2 does not consume Si from the substrate and can be done at much
lower temperatures.
Solid State Electronic Devices
1.6. Photolithography1.6. Photolithography
• Patterns corresponding to complex circuitry are
formed on a wafer using photolithography.
• A thin layer of electron beam sensitive material
called electron beam resist is placed on the iron-
oxide-covered quartz plate, and the resist is exposed
by the electron beam.
• A resist is a thin organic polymer layer that
undergoes chemical changes if it is exposed to
energetic particles. This is exposed selectively.
• After exposure, the resist is developed in a chemical
solution.
• The developer is either used to remove the exposed
or unexposed material.Fig. 7. Schematics of optical stepper
Solid State Electronic Devices
1.6. Photolithography1.6. Photolithography
• Diffraction-limited minimum geometry
NAl
8.0min
- NA is the numerical aperture. This expression implies that for finer patterns, we
should work with lager lenses and shorter wavelengths.
• Depth-of-focus
2)(2 NADOF
- This tells the range of distances around the focal plane where the image quality
is sharp.
Solid State Electronic Devices
1.6. Photolithography1.6. Photolithography
Fig. Simple Image System
Solid State Electronic Devices
1.7. Etching1.7. Etching
Fig. 8. Reactive ion etcher
• After the photoresist pattern is formed, it can be
used as a mask to etch the material underneath.
• Isotropic
Etch as fast laterally as etching vertically.
• Anisotropic : Etches vertically but not laterally
along the surface.
• As shown in Fig. 8., RIE, appropriate etch gases
flow into the chamber at reduced pressure, and a
plasma is struck by applying an rf voltage across
a cathode and an anode.
• The rf voltage accelerates the light electrons in
the system to much higher kinetic energies than
the heavier ions.
• The high energy electrons collide with neutral atoms and molecules to create ions and molecular
fragments called radicals.
Solid State Electronic Devices
1.8. Metallization1.8. Metallization
1. Ar ions bombard the Al and physically dislodge Al atoms by momentum transfer.
2. Many of the Al atoms ejected from the target deposit on the Si wafers held in close
proximity to the target.
Fig. 9. Aluminum sputtering by Ar+ ions
Solid State Electronic Devices
Flows of FabricationFlows of Fabrication
Fig. 10. Simplified description of steps in the fab. of p-n junctions.
For Simplicity, only four
diodes per wafer are shown,
and the relative thicknesses of
the oxide, PR, and the Al
layers are exaggerated
Solid State Electronic Devices
2. Equilibrium Conditions2. Equilibrium Conditions
< Preface >< Preface >
• The mathematics of p-n junctions is greatly simplified for the case of the step
junction, which has uniform p doping on one side of a sharp junction and uniform n
doping on the other side.
• Diffused or implanted junctions are actually graded(Nd – Na varies over a significant
distance on either side of the junction). In these discussions we shall assume one-
dimensional current flow in samples of uniform cross-sectional area.
• The difference in doping on each side of the junction causes a potential difference
between the two types of material.
• There are four components of electrons and holes. These combine to give zero net
current for the equilibrium case.
Solid State Electronic Devices
2.1. The Contact Potential2.1. The Contact Potential
Before they are joined ;Before they are joined ;
• nn material material
A large concentration of electrons and few holes.
Fermi energy level is above Ei level.
• pp material material
A large concentration of holes and few electrons.
Fermi energy level is below Ei level.
Fig. 11. (a) Before the junction
Solid State Electronic Devices
2.1. The Contact Potential2.1. The Contact Potential
After they are joined ;After they are joined ;
1. Many carriers diffuse to take place because of the
large carrier concentration gradients at the junction.
2. Holes diffuse from the p side into the n side, and
electrons diffuse from n to p.
3. The resulting diffusion current cannot build up
indefinitely, because an opposing electric field is
created at the junction.
Fig. 11. (b) After the junction
Equilibrium State :dE
dxF 0
Solid State Electronic Devices
2.1. The Contact Potential2.1. The Contact Potential
• Electrons diffusing from n to p leave behind uncompensated donor ions is the n
material, and holes leaving the p region leave behind uncompensated acceptors.
• It is easy to visualize the development of a region of positive space charge near the
n side of the junction and negative charge near the p side.