Certain Audiovisual Components and Products Containing ......MT5391, MT5392, MT8551, MT8560, all ofwhich have substantially or exactly the same structure in relevant part as those

EXHIBIT 51EXHIBIT 51

Infringement Chart

Patent No. 5,870,087 (“‘087 Patent”)

Claim Language Accused Instrumentality

1. An MPEG decoder system

which includes a single

memory for use by transport,

decode and system controller

functions, comprising:

The Accused Single Memory Products include an MPEG decoder system which includes a single memory for

use by transport, decode and system controller functions. The Accused Single Memory Products include,

without limitation, digital television, DVD player/recorder, Blu-ray disc player/recorder and other

substantially similar audiovisual products in relevant part which contain integrated circuits (“ICs”) that utilize

a single memory for the designated functions (“single memory structure”), and which are manufactured,

imported and/or distributed by or on behalf of Funai’s1 under brand names such as Philips, Magnavox, Funai,Sylvania, Emerson, Symphonic, Sharp, and Denon.

Specific non-limiting examples of ICs contained in the Accused Single Memory Products include MT5382,

MT5391, MT5392, MT8551, MT8560, all of which have substantially or exactly the same structure in

relevant part as those in MediaTek MT53xx family and MT5 8xx family.

MediaTek Chips

As an example, the Philips 42PFL6704D Television product contains a MediaTek chip in the MT53xx family,

MT5392. Ex. 50 [Philips 42PFL6704D/F7 SVM] at 9-2.

Chips in the MT5 3xx, MT5 8xx and similar families in relevant part include MPEG video and audio decoders.

See, e. g., Ex. 89 [Philips 42PFL6704D/F7 User Manual] at 20 (supported video codecs include H.246,

MPEG1, MPEG2, and supported audio codecs include MPEG1 L1/L2 and L3), see also, e.g., Ex. 142 [Vizio

E420VO SVM] at 7-2 (listing “MPEG2 video decoder” and “AC3/MPEG2 audio decoder” as key features of

MT5387 chipset) (available from: http://www.scribdcom/doc/52381651/E420VO-ServiceManual (last visited

03/09/2012).

MediaTek chips in the MT53xx, MT5 8xx and similar families in relevant part include a single memory for use

b trans ort, decode and s stem controller functions. A block diaram of MT5392 chi set is shown below.

1 “Funai” refers collectively to Funai Corporation, Inc., P&F USA, Inc. and Funai Electric Company, Ltd, and any and all parties acting for, with or otherwise onbehalf of Funai Corporation, P&F USA and Funai Electric Co.

Kilpatrick Townsend 640179971

1


The chipset is shown as including, in addition to other components, a “TS Demux” (transport logic), a “Video

Decoder” (MPEG decoder), and an “ARM1 1” controller (system controller). The DRAM (single memory) is

controlled by the DRAM controller and shared by the “transport logic”, “MPEG decoder”, and “system

controller” Via the DRAM Bus. See, e. g., EX. 91 [Philips LC9.2L Service Manual] at 43:

See also, e.g., EX. 50 [Philips 42PFL6704D SVM] at 10-5, 10-14 (showing a single DRAM (“7B02”) coupled

to the main processor (“7701”)):



a channel receiver for

receiving and MPEG encoded


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".3------------iii‘:

Similar structures in relevant part are found in other MediaTek chips. See, e. g., Ex. 142 [Vizio E420VO

SVM] at 7-2, 7-3, 7-4, 7-30 (MT5387), Ex. 90 “Global and China Flat-Panel TV IC Industry Report, 2009-

2010 (MT5387).

To the extent that the Accused Single Memory Products do not infringe literally, they infringe under the

doctrine of equivalents because, in the Accused Single Memory Products, the claimed and identified features

perform substantially or exactly the same function, in substantially or exactly the same way, to achieve

substantially or exactly the same result.

The MPEG decoder system in the Accused Single Memory Products includes a channel receiver (such as a

tuner receiver or o tical disc receiver) for receivin an MPEG encoded stream.


For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

DTV 42PFL6704D/F7, include a “DTD” receiver which receives MPEG encoded streams from a digital tuner

(such as an ATSC tuner):

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Ex. 91 [Philips LC9.2L Service Manual] at 43, see also, e. g., EX. 142 [Vizio E420VO SVM] at 7-4 (noting

that the transport demultiplexer “[s]upports ATSC, MPEG-2 transport stream input”), EX. 97 [ATSC Part 4-

MPEG2 Video System Characteristics] at 8, Section 6 (“Source Coding Specification”) (“The DTV video

compression algorithm shall conform to the Main Profile syntax of ISO/IEC 13818-2”) [i.e., MPEG-2]

(available from htt ://www.atsc.or/cms/standards/a53/a 53—Part—4—2009. df), EX. 98



[http://wwwhdtvprimercom/ISSUES/what_is_ATSC.html] at l (“ATSC employs MPEG-2....”).



perform substantially or exactly the same function, in substantially or exactly the same way, to achievesubstantiall or exactl the same result.

transport logic coupled to the The MPEG decoder system in the Accused Single Memory Products includes transport logic (such as a

channel receiver which transport demultiplexer or a stream controller) coupled to the channel receiver which demultiplexes one or

demultiplexes one or more more multimedia data streams from the encoded stream.multimedia data streams from

the encoded stream, For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

DTV 42PFL6704D/F7 include a “TS Demux” or transport demultiplexer that is coupled to the channel

receiver and which demultiplexes one or more multimedia data streams from the encoded stream:

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Kilpatrick Townsend 640 17997.1


Ex. 91 [Philips LC9.2L Service Manual] at 43, see also, e.g., Ex. 142 [Vizio E420VO SVM] at 7-3 (showing a

“TS Demux” coupled to an “ATSC” tuner that receives MPEG2 streams), 7-4 (general features of “Transport

Multiplexer”); Ex. 99 [ITU-T H.222.0 (2006)] at x, Section Intro. 8.1 (“Demultiplexing”) (“On decoding,

demultiplexing is required to reconstitute elementary streams from the multiplexed Program Stream or

Transport Stream.”), id. at 121, Figure 2-11 (showing “Transport Stream demultiplexing”), id. at 123, Figure

2-12 (showing “Program Stream demultiplexing”).




a system controller coupled to The MPEG decoder system in the Accused Single Memory Products includes a system controller (such as a

the transport logic which CPU) coupled to the transport logic which controls operations within the MPEG decoder system.

controls operations within the For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

MPEG decoder system, DTV 42PFL6704D/F7, include an “ARM 11” system controller (e. g. , an ARM 926 E] processor) which

controls operation within the MPEG decoder system:



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Ex. 91 [Philips LC9.2L Service Manual] at 43, see also, e.g., Ex. 142 [Vizio E420VO SVM] at 7-3 (similar

block diagram for MT5387 in relevant part and listing the ARM chip, such as ARM 926E] as the “Host

CPU”), Ex. 143 [Vizio GV42L_HTDV SVM] at 7-31, 7-32 (listing ARM 926E] as the host CPU for

MT5351).

The system controller is coupled to the transport logic. Ex. 142 at 7-4 (noting that the transport demultiplexer

“[s]upports a micro-processor for stream process and MPEG start code detection”).




an MPEG decoder coupled to The Accused Single Memory Products include an MPEG decoder (e. g. an MPEG video or audio decoder)

receive one or more coupled to receive one or more multimedia data streams output from the transport logic (such as the transport

multimedia data streams demultiplexer or the stream controller), wherein the MPEG decoder operates to perform MPEG decoding on



output from the transport logic, the multimedia data streams.wherein the MPEG decoder

operates to perform MPEG For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

decoding on the multimedia DTV 42PFL6704D/F7, include a “Video Decoder” that is coupled to receive one or more multimedia data

data streams; streams output from the transport logic via, for example, the system bus. The video decoder operates to

perform MPEG decoding on the multimedia data streams:

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Ex. 91 [Philips LC9.2L Service Manual] at 43, see also, e.g., Ex. 89 [Philips 42PFL6704D/F7 User Manual] at

20 (supported video codecs include H.246, MPEG1, MPEG2, and supported audio codecs include MPEG1

L1/L2 and L3), Ex. 142 [Vizio E420VO SVM] at 7-3 (similar block diagram for MT5387 in relevant part), 7-

4 (listing “MPEG2 Decoder”), Ex. 99 [ITU-T H.222.0 (2006)] at 13, Section 2.4.2.3 (“Buffering”) (“Complete

Transport Stream packets containing system information, for the program selected for decoding, enter the

system transport buffer ...”), id. at 52, Section 2.5.2.2 (“Data from the Program Stream enters the system target

decoder”), id. at 121, Section 2.14.3.1 (“The T-STD model includes a transport buffer TBn and a multiplex

buffer MBn prior to buffer EBn for decoding of each ITU-T Rec. H.264 @■ video elementary stream n”), id. at

123, Section 2.14.3.2 (“The P-STD model for the decodin of an ITU-T rec. H.264 ■ elementa stream



wherein the MPEG decoder is

operable to access the memory

during MPEG decoding

operations;

wherein the transport logic is

operable to access the memoryto store and retrieve data

during demultiplexing

operations; and wherein the

system controller is operable

to access the memory to

retrieve code and data during

system control functions.


includes a multiplex buffer Bn and a decoder Dn followed by a buffer DPBn.”).





In the Accused Single Memory Products, the MPEG decoder is operable to access the memory during MPEG

decoding operations, the transport logic is operable to access the memory to store and retrieve data during

demultiplexing operations, and the system controller is operable to access the memory to retrieve code and

data during system control functions.


DTV 42PFL6704D/F7, have a “Video Decoder” including the MPEG decoder, “TS Demux” (transport logic)

and “ARMl 1” (CPU or system controller”) that are operable to access the single memory through the DRAMBus.


EX. 91 [Philips LC9.2L Service Manual] at 43, see also, e. g., EX. 142 [Vizio E420VO SVM] at 7-3 (similar

block diagram for MT5387).

In both examples, the MPEG decoder accesses the memory during MPEG decoding operation; Transport

logic, which typically requires buffering space on the memory (see e. g., EX. 99 [ITU-T H.222.0 (2006)] at 13,

Section 2.4.2.3 (“Buffering”), at 53, Section 2.5.2.3 (“Buffering”)), accesses the memory to store and retrieve

data during demultiplexing operations, the ARM CPU (such as ARM 926EJ or AM34-SMP) accesses the

memory to retrieve code and data during system control functions. See, e. g., EX. 100 [ARM926EJ-S

Technical Reference Manual] (available from

http://infocenterarm.com/help/topic/com.arm.doc.ddi0198e/DDI0198E arm926eis r0p5 t1m.pdf (last visited

(03/09/2012)) at 6-3, Section 6.2.1 (“Memory Map”) (“The ARM926EJ-S processor is a cached processor

with two AHB interfaces. It is a key system design issue that the D side must be able to access the same

as the I side, with the same memo ma. This is reuired not onl to load code, but to enable access



to PC-relative literal pools, and for SWI and emulated instruction handlers to work”),


doctrines of equivalents because, in the Accused Single Memory Products, the claimed and identified features



10. A method for performing The operation of the Accused Single Memory Products (the “Accused Single Memory Processes”) involves

video decoding in a MPEG methods for performing video decoding in an MPEG decoder system.

decoder system

As an example, Philips 42PFL6704D Television can decode MPEG-formatted video files. See, e. g., Ex. 89

[Philips 42PFL6704D/F7 User Manual at 20 (supported video codecs include H.246, MPEG1, MPEG2).

As another example Magnavox Blu-ray disc player MBP5220F can decode MPEG-2 and H.264 video files.

See, e. g., Ex 93 [Magnavox MBP5220F SVM] at l-l l-3, l-l2-l2 (showing MPEG-2 and H.264 decoder):

ll



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To the extent that the Accused Single Memory Processes do not infringe literally, they infringe under the

doctrines of equivalents because in the Accused Single Memory Processes and Products, the claimed and

identified features perform substantially or exactly the same function, in substantially or exactly the same way,to achieve substantiall or exactl the same result.

which includes a single In the Accused Single Memory Products, the MPEG decoder system includes a single memory for use by

memory for use by transport, transport, decoder and system controller functions. Examples of ICs contained in the Accused Single Memory

decode and s stem controller Products include, without limitation, MT5382, MT539l, MT5392, MT855 l, MT8560, MN2WSO06AAF,

12



functions, the method MN2WS0062AFF(B), MN2WS0062DFF, MN2WSOl50A3, MN2WS02l0A2, MN2WS0043DA,

comprising: MN2WS0l2A, MN2WS0l2OA, MN2WS0l70, MN2DS00l9AA, MN2DS00l8VP, all of which have

substantially the same structure as those in MediaTek MT53XX family and MT5 8);): family.

As an example, the Philips 42PFL6704D Television product contains a MediaTek chip in the MT53XX family,

MT5392. EX. 50 [Philips 42PFL6704D/F7 SVM] at 9-2.

MediaTek chips in the MT53XX, MT5 8):): and similar families in relevant part include a single memory for use

by transport, decode and system controller functions. For example, a block diagram of MT5392 chipset is

shown below. The chipset is shown as including, in addition to other components, a “TS Demux” (transport

logic), a “Video Decoder” (MPEG decoder), and an “ARMl 1” controller (system controller). The DRAM

(single memory) is controlled by the DRAM controller and shared by the “transport logic”, “MPEG decoder”,

and “system controller” via the DRAM Bus. See, e.g., EX. 91 [Philips LC9.2L Service Manual] at 43:

Ifarset

13



See also, e. g., EX. 50 [Philips 42PFL6704D SVM] at 10-5, 10-14 (showing a single DRAM (“7B02”) coupled


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Similar structures in relevant part are found in other MediaTek chips. See, e.g., Ex. 142 [Vizio E420VO


2010 (MT5373).




receiving an MPEG encoded The operation of the Accused Single Memory Products includes receiving an MPEG encoded stream.stream,




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Ex. 91 [Philips LC9.2L Service Manual] at 43, see also, e. g., Ex. 142 [Vizio E420VO SVM] at 7-4 (noting

that the transport demultiplexer “[s]upports ATSC, MPEG-2 transport stream input”), Ex. 97 [ATSC Part 4-


compression algorithm shall conform to the Main Profile syntax of ISO/IEC 13818-2”) [i.e. MPEG-2]

To the extent that the Accused Single Memory Processes do not infringe literally, they infringe under the

doctrines of equivalents because, in the Accused Single Memory Processes and Products, the claimed and

identified features perform substantially or exactly the same function, in substantially or exactly the same way,

to achieve substantially or exactly the same result.

demultiplexing one or more The MPEG decoder system in the Accused Single Memory Products includes transport logic (such as a

multimedia data streams from transport demultiplexer or a stream controller) coupled to the channel receiver which demultiplexes one or

the encoded stream, wherein more multimedia data streams from the encoded stream using a first unified memory.

said demultiplexing one or

more multimedia data streams For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

from the encoded stream DTV 42PFL6704D/F7 include a “TS Demux” or transport demultiplexer that is coupled to the channel

operates using a first unified receiver and which demultiplexes one or more multimedia data streams from the encoded stream:memory,

16



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Multiplexer”); Ex. 99 [ITU-T H.222.0 (2006)] at x, Section Intro. 8.] (“Demultiplexing”) (“On decoding,







performing MPEG decoding The Accused Single Memory Products include an MPEG decoder (e. g. an MPEG video or audio decoder)

on the multimedia data which decodes the multimedia data streams using the first unified memory.

streams, wherein said

17



performing MPEG decoding For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

operates using said first DTV 42PFL6704D/F7, include a “Video Decoder” that operates to perform MPEG decoding on the

unified memory; multimedia data streams using the first unified memory:

EX. 91 [Philips LC9.2L Service Manual] at 43, see also, e. g., EX. 89 [Philips 42PFL6704D/F7 User Manual] at


L1/L2 and L3), EX. 142 [Vizio E420VO SVM] at 7-3 (similar block diagram for MT5387 in relevant part), 7-

4 (listing “MPEG2 Decoder”), EX. 99 [ITU-T H.222.0 (2006)] at 13, Section 2.4.2.3 (“Buffering”) (“Complete


system transport buffer ...”), id. at 52, Section 2.5.2.2 (“Data from the Program Stream enters the system target

decoder”), id. at 121, Section 2.14.3.1 (“The T-STD model includes a transport buffer TBn and a multiplex

buffer MBn prior to buffer EBn for decoding of each ITU-T Rec. H.264 )■ video elementary stream n”), id. at

123, Section 2.14.3.2 (“The P-STD model for the decoding of an ITU-T rec. H.264 P1■ elementary stream

includes a multi lex buffer Bn and a decoder Dn followed b a buffer DPBn.”).






and a system controller The Accused Single Memory Products include a system controller (such as a CPU) that control the operations

controlling operations within within the MPEG decoder system and accesses code and data from said first unified memory.

the MPEG decoder system,

wherein said controlling For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

operations accesses code and DTV 42PFL6704D/F7, include an “ARM ll” system controller (e.g., an ARM 926 E] processor) which

data from said first unified controls operation within the MPEG decoder system:memory

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block diagram for MT5387 in relevant part and listing the ARM chip, such as ARM 926EJ as the “Host




MT5351).

The system controller is coupled to the transport logic. Ex. 142 at 7-4 (noting that the transport demultiplexer





wherein said demultiplexing In the Accused Single Memory Products, the multiplexing of the data streams, the MPEG decoding and the

one or more multimedia data controlling of operations each use the first unified memory.

streams, said performing

MPEG decoding, and said For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

controlling operations each use DTV 42PFL6704D/F7, have a “Video Decoder” including the MPEG decoder, “TS Demux” (transport logic)

said first unified memory. and “ARMl 1” (CPU or system controller”) that are operable to access the single memory through the DRAMBus.

20



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data during demultiplexing operations. The ARM CPU (such as ARM 926EJ or AM34-SMP) accesses the



ht ://infocenter.armcom/hel /to ic/co1n.arm.doc.ddi0l98e/DDI0198E arm926e's r0 f trm. df (last visited



memory as the I side, with the same memory map. This is required not only to load code, but to enable access

to PC-relative literal ools, and for SWI and emulated instruction handlers to work”),






16. A video decoder system The Accused Single Memory Products include a decoder system which includes a single memory for use by

which includes a single transport, decode and system controller functions. The Accused Single Memory Products include, without

memory for use by transport, limitation, digital television, DVD player/recorder, Blu-ray disc player/recorder and other substantially similar

decode and system controller audiovisual products in relevant part which contain integrated circuits (“ICs”) that utilize a single memory for

functions, comprising: the designated functions (“single memory structure”), and which are manufactured, imported and/or

distributed by or on behalf of Funai’s2 under brand names such as Philips, Magnavox, Funai, Sylvania,Emerson, Symphonic, Sharp, and Denon.

Specific non-limiting examples of ICs contained in the Accused Single Memory Products include MT5382,

MT5391, MT5392, MT8551, MT8560, all of which have substantially or exactly the same structure in

relevant part as those in MediaTek MT53xx family and MT5 8xx family.

MediaTek Chips

As an example, the Philips 42PFL6704D Television product contains a MediaTek chip in the MT53xx family,

MT5392. Ex. 50 [Philips 42PFL6704D/F7 SVM] at 9-2.

Chips in the MT5 3xx, MT5 8xx and similar families in relevant part include MPEG video and audio decoders.

See, e.g., Ex. 89 [Philips 42PFL6704D/F7 User Manual] at 20 (supported video codecs include H.246,

MPEG1, MPEG2, and supported audio codecs include MPEG1 L1/L2 and L3), see also, e.g., Ex. 142 [Vizio

E420VO SVM] at 7-2 (listing “MPEG2 video decoder” and “AC3/MPEG2 audio decoder” as key features of

MT5387 chipset) (available from h :/XWWW.scribd.com/doc;’52381651/E420VO—ServiceManual (last visited

03/09/2012).

MediaTek chips in the MT53xx, MT5 8xx and similar families in relevant part include a single memory for use

b trans ort, decode and s stem controller functions. A block diaram of MT5392 chi set is shown below.

2 “Funai” refers collectively to Funai Corporation, Inc., P&F USA, Inc. and Funai Electric Company, Ltd, and any and all parties acting for, with or otherwise onbehalf of Funai Corporation, P&F USA and Funai Electric Co.

22



The chipset is shown as including, in addition to other components, a “TS Demux” (transport logic), a “Video

Decoder” (MPEG decoder), and an “ARM1 1” controller (system controller). The DRAM (single memory) is

controlled by the DRAM controller and shared by the “transport logic”, “MPEG decoder”, and “system

controller” Via the DRAM Bus. See, e. g., EX. 91 [Philips LC9.2L Service Manual] at 43:

See also, e.g., EX. 50 [Philips 42PFL6704D SVM] at 10-5, 10-14 (showing a single DRAM (“7B02”) coupled


23



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".3------------iii‘:

Similar structures in relevant part are found in other MediaTek chips. See, e. g., Ex. 142 [Vizio E420VO


2010 (MT5387).





a channel receiver for The MPEG decoder system in the Accused Single Memory Products includes a channel receiver (such as a

receivin an encoded video tuner receiver or o tical disc receiver) for receivin an MPEG encoded stream.






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Ex. 91 [Philips LC9.2L Service Manual] at 43, see also, e. g., EX. 142 [Vizio E420VO SVM] at 7-4 (noting

that the transport demultiplexer “[s]upports ATSC, MPEG-2 transport stream input”), EX. 97 [ATSC Part 4-


compression algorithm shall conform to the Main Profile syntax of ISO/IEC 13818-2”) [i.e. MPEG-2]

(available from htt ://www.atsc.or/cms/standards/a53/a 53—Part—4—2009. df), EX. 98

25



[http://wwwhdtvprimercom/ISSUES/what_is_ATSC.html] at l (“ATSC employs MPEG-2....”).




transport logic coupled to the The MPEG decoder system in the Accused Single Memory Products includes transport logic (such as a

channel receiver which transport demultiplexer or a stream controller) coupled to the channel receiver which demultiplexes one or

demultiplexes one or more more multimedia data streams from the encoded stream.multimedia data streams from

the encoded stream, For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

DTV 42PFL6704D/F7 include a “TS Demux” or transport demultiplexer that is coupled to the channel

receiver and which demultiplexes one or more multimedia data streams from the encoded stream:

‘*g§E¥s!@_;» , £urra;;.vz2s::<uaa=s1_ ‘£53-‘ mw - %%%l ‘tum-av T QQFQd E51;:Iw1 @ p! ' ■

26





Multiplexer”); Ex. 99 [ITU-T H.222.0 (2006)] at x, Section Intro. 8.1 (“Demultiplexing”) (“On decoding,







a system controller coupled to The MPEG decoder system in the Accused Single Memory Products includes a system controller (such as a

the transport logic which CPU) coupled to the transport logic which controls operations within the MPEG decoder system.

controls operations within the

video decoder system, For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

DTV 42PFL6704D/F7, include an “ARM 11” system controller (e.g., an ARM 926 E] processor) which

controls operation within the MPEG decoder system:

27



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psK■ ■[■


block diagram for MT5387 in relevant part and listing the ARM chip, such as ARM 926E] as the “Host


MT5351).

The system controller is coupled to the transport logic. See Ex. 142 (noting that the transport demultiplexer





a video decoder coupled to The Accused Single Memory Products include an MPEG decoder (e. g. an MPEG video or audio decoder)

receive one or more coupled to receive one or more multimedia data streams output from the transport logic (such as the transport

multimedia data streams demultiplexer or the stream controller), wherein the MPEG decoder operates to perform MPEG decoding on



output from the transport logic, the multimedia data streams.wherein the video decoder

operates to perform video For example, chips in the MediaTek family and similar families in relevant part, such as MT5392 in Philips

decoding on the multimedia DTV 42PFL6704D/F7, include a “Video Decoder” that is coupled to receive one or more multimedia data

data streams; streams output from the transport logic via, for example, the system bus. The video decoder operates to

perform MPEG decoding on the multimedia data streams:

■■ C355 giiflgfyim Haws Tum: :macsace=7‘ vriamaara pm,‘ sag; an .:sstmH

33:51:33 Wt

EX. 91 [Philips LC9.2L Service Manual] at 43, see also, e. g., EX. 89 [Philips 42PFL6704D/F7 User Manual] at


L1/L2 and L3), EX. 142 [Vizio E420VO SVM] at 7-3 (similar block diagram for MT5387 in relevant part), 7-

4 (listing “MPEG2 Decoder”), EX. 99 [ITU-T H.222.0 (2006)] at 13, Section 2.4.2.3 (“Buffering”) (“Complete


system transport buffer `■■■ ), id. at 52, Section 2.5.2.2 (“Data from the Program Stream enters the system target

decoder”), id. at 121, Section 2.14.3.1 (“The T-STD model includes a transort buffer TBn and a multilex



and

a memory coupled to the video

decoder, wherein the memory

is used by the video decoder

during video decoding

operations, wherein the

memory stores code and data

useable by the systemcontroller which enables the

system controller to performcontrol functions within the

video decoder system, wherein

the memory is used by the

transport logic for

demultiplexing operations;wherein the video decoder is

operable to access the memory

during video decoding

operations, wherein the

transport logic is operable to

access the memory to store and

retrieve data during

demultiplexing operations, and

wherein the system controller

is operable to access theto retrieve code and


buffer MBn prior to buffer EBn for decoding of each ITU-T Rec. H.264 0■ video elementary stream n”), id. at

123, Section 2.14.3.2 (“The P-STD model for the decoding of an ITU-T rec. H.264 pj■ elementary stream

includes a multiplex buffer Bn and a decoder Dn followed by a buffer DPBn.”).




In the Accused Single Memory Products, the MPEG decoder is operable to access the memory during MPEG

decoding operations, the transport logic is operable to access the memory to store and retrieve data during

demultiplexing operations, and the system controller is operable to access the memory to retrieve code and

data during system control functions.


DTV 42PFL6704D/F7, have a “Video Decoder” including the MPEG decoder, “TS Demux” (transport logic)

and “ARMl 1” (CPU or system controller”) that are operable to access the single memory through the DRAMBus.

30

data during system controlfunctions.


SF3‘mF'_ I338






data during demultiplexing operations. The ARM CPU (such as ARM 926EJ or AM34-SMP) accesses the



ht ://infocenter.armcom/hel /to ic/co1n.arrn.doc.ddi0l98e/DDI0198E arm926e's r0 f trrn. df (last visited



memory as the I side, with the same memory map. This is required not only to load code, but to enable access

to PC-relative literal ools, and for SWI and emulated instruction handlers to work”),






32


Documents

Certain Audiovisual Components and Products Containing ......MT5391, MT5392, MT8551, MT8560, all ofwhich have substantially or exactly the same structure in relevant part as those