CEC 320 and 322Microprocessor Systems

Class and Lab

FINAL EXAM REVIEW

Exams and the “Real World”R&D, r&D, R&d, D

– Intel, Microsoft, IBM, Arm Ltd., National Labs - R&D– Smaller companies and service organizations - r&D– Gov’t Agencies, Universities, Non-profits, etc. - R&d, R&D– Training institutes, contract developers, operations - D

Exams assess how much you learned with a quick method– Hands-on projects, design, Capstone, etc. preferred, but time consuming– Difficult to do design before you have a working knowledge, basic understanding,

and vocabulary– Exams are to prepare you and to assess that you are ready to do real work

(design, development, analysis to support, communicate results, etc.)

Real World cares about1. Working systems2. Design that can be maintained and understood3. Efficiency, optimization, performance4. Ease of use5. Solves a problem and meets a need6. Solving problems under time constraints (similar to an exam)7. Thinking on the spot (most like an exam)

© Sam Siewert

Final Exam - CompositionFormat (2 hours, should be easily completed in that time)

– 2x length of a Chapter Exam (Exam-1, Exam-2)– Basic calculator (not programmer’s or smart phone) allowed– One page of notes (written on both sides) allowed– 40% from Part-1 (Exam-1) Materials– 40% from Part-2 (Exam-2) Materials– 20% from new material (since Exam-2) on Platforms

Emphasis on Knowledge and Concepts with Basic Analysis– Problems that you have seen before, but with new parameters– Knowledge you should recall for efficient engineering (now and in the future)

Design is done in CE322 Lab– code design, implement, test– circuit implementation and analysis, etc. - not on CEC320 Final Exam

Knowledge and Concepts– T/F, Multiple Choice, Fill-in, Short Answer - e.g. what is EDA?, what is an IDE?– Terminology used in book and notes (commonly used acronyms and definitions)

Analysis– Computations, ALU and Pipeline diagrams, Simple ISA, performance– Cache configurations, how to debug, how to create diagrams to explain (simple UML)– How to select an MCU– Analysis of design - e.g. interpretation of a UML diagram, ALU diagram, Pipeline, etc.

© Sam Siewert

Review Outline - Book and NotesPart-1 - MCU Systems and ISA Fundamentals– CAC Chapters 1.1-1.3– CAC 1.6– CAC 2.1-2.3– Notes - Week-1 to Week-5, LC3-Notes, UML-Overview-Notes

Part-2 - MCU CPU Cores and Pipelines– CAC Chapters 2.5-2.7– CAC 3.1-3.8– CAC 3.10– Week-7 to Week-12

Platforms - MCU and SoC– CAC Chapter 4.1 - 4.9– CAC 4.11 – Week-13 and Week-14 (up to Breakpoints!)

© Sam Siewert

Review MaterialsSummarization of Key Concepts (Review in class)– Summary of key concepts provided here– Please also make your one page of notes with same goal

Q&A in class and office hours

Study Guide– Exam #1 and #2 Solutions posted on Canvas– Assignment Book problem solutions posted on Canvas– Notes posted - cec320/documents/Lectures/– Reading assigned (use SQ3R)

ScanQuestion (on note page)Read (to answer your own questions)Recite and review your own notes

– Make your Own 1-page of notes!

© Sam Siewert

Key ConceptsOutline of concepts may include, but not limited to the following slides …

Please review all reading, assignments, prior exams and quizzes (solutions)

The outline here includes knowledge, concepts, and methods of analysis that we spent time on in class, homework, and on exams

Consider examples from lab and how they relate to knowledge, concepts, and theory in class

© Sam Siewert

Key Concepts - Part-1Instruction Set Architecture– LC-3 16 bit example – Addressing modes - PC relative, Indirect, Base+Offset– ARM 32-bit ISA examples from class and book– Opcode, Operands, and format variants (reserved bits)– One-to-one ASM (mneumonics) to machine code (bits)

EDA– Tools used for hardware design– Flow from architecture to routing netlist for manufacturing (“fab”)– IC Digital design synthesis, RTL, simulation (cycle approximate,

cycle accurate), placement, routing (GDSII)– PCB schematic capture, place and route, netlist, manufacturing

© Sam Siewert

Key Concepts - Part-1IDE (e.g. IAR Tools)– Cross compile– Cross debug– Edit, download code (via JTAG)

Binary Computations– For addresses and address ranges– For machine code formats– General size, range, and units (KB, MB, GB, TB, PB, EB)– Hex, Binary and bits to represent a range or value

UML Basics– Structural Models - Class Diagram, etc.– Behavioral Models - State Machine, Sequence Diagram, etc.

© Sam Siewert

Key Concepts - Part-1ALU and Pipeline Fundamentals– Basic 3-stage and 5-stage ALU– Pipeline start-up, steady-state, speed-up, stall impact– IPC (Instructions per Clock), CPI (Clocks per Instruction)

History of the IC– Scale of integration from first IC to MSI, LSI, VLSI, to ULSI– Texas Instruments and Intel– Fairchild– Relationship in time to computing in general

General Architecture– Flynn’s Taxonomy– MCU and the ARM Series A, M, and R– DSP VLIW, 8-bit, 16-bit and 32-bit MCUs

© Sam Siewert

Key Concepts - Part-2Pipeline Details– Difference between simple pipeline, super-pipeline, super-scalar– Pipeline hazards - e.g. cache miss, data dependency, branch

mis-prediction, limited registers (pressure), etc. and impact– Pipeline stages (depth) and speed-up, ideal and actual– 3-stage, 5-stage analysis and advanced 7/8 stage (knowledge

only)– Stall cycles and pipeline diagrams

Cache– Direct mapped– Set Associative (Fully Associative)– Mutli-layer - Harvard split L1, Unified L2, L3– Performance based on hit rates– Cache trace analysis

© Sam Siewert

Key Concepts - Part-2Memory Mapping– Memory Controller– Memory Management Unit (Virtual Memory) and purpose– MMIO– Memory Map Layout (in binary) for address range

Power Management– Dynamic Voltage and Frequency Scaling– Peripheral disablement

MCU and DSP Examples– ARM - ARM-7, 11, and M, R, A Series– TI DSPs from book (C55x, C64x)

© Sam Siewert

Key Concepts - Part-2NVIC, Exceptions, and FIQ/IRQ– NVIC (Nested, Vector, Interrupt Controller) used in M Series– FIQ and IRQ concepts for A Series– NMI (Non-Maskable Interrupts) and Exceptions

Advantages of DSP and Problems that Benefit– 1D and 2D DSP– 1D Signals, e.g. audio– 2D Signals, e.g. images and video– Convolution concept - transform signals (1D or 2D) with a

mathematical operator applied over all samples– Comparison of VLIW to Super-scalar

© Sam Siewert

Key Concepts - Part-3 (Platforms)HAL

– What is it, Examples (e.g. PDL), Value

DMA– What it is for– How it interacts with the CPU– How to specify a transfer– How to know when it is done– Bus cycle timing diagram

Timers– How they are used (Timer interrupts, time-outs, delays)– How they work– Why they are important to operating systems and platforms

Local CPU-Memory Bus and I/O Bus– Difference– Bus cycle timing diagrams for basic transactions studied– Examples - Signals (Address, Data, Control) and Transfers

© Sam Siewert

Key Concepts - Part-3 (Platforms)IDE for a Platform and Single Board Computers– Connecting to an SBC (Serial, JTAB, USB bridge)– How debugging works– What breakpoints are– PCB concepts - chip count (e.g. MCU reduces), layers (2-layer

and 4 layer with internal ground/power layers)– Memory technology

Advanced Bus Transfer Concepts– Burst transfer and DMA– Split-transaction (for read from slow devices)– Posting writes (for slow devices)– Difference between programmed I/O and DMA I/O– Wait-States

© Sam Siewert

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Single-Step DebuggingJTAG TAP – IEEE 1149.1– Derived from Original JTAG Boundary Scan Chain

Used for Board/Device Factory VerificationTDI/TDO Shift Register Interface for Test Data In/Out

– Verify Bits Shifted Out of Chain for Given Bit Pattern Shifted In– BSDL – an HDL use to Specify Scan Chain

– TAP Added For Firmware (Boot-Strapping) Debug– Replaces or Enhances PROM Monitor– Obviates “Burn and Learn” and/or PROM Monitor Boot-Strapping

CPU Clocked/Controlled By External JTAG – HW Single-Step

Many Variants and Extensions of JTAG TAP– BDM (Background Debug Mode), OnCE (On-Chip Emulator), OCD (On-

Chip Debugger)– Variants/Extensions Provide HW-Supported Features

Internal Break-points (HW raised Debug EXC on PC-Addr Match)Debug SRAM or Instruction Cache for JTAG controlled Debug HandlerHot-Debug

Read “Zen of BDM” for History and Background

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JTAG TAP ToolsJTAG Probe– Host Interface

Parallel, Serial, USB, Ethernet Port Connection to HostTranslation of Debugger Commands to JTAG TDI/TDO and JTAG Commands for TAP Execution

– Debugger ToolTraditional Single-Step Debugger Interface – E.g. DDD/GDBExtensions for Core Specific Registers and Features

– JTAG Personality ModuleConforms to Specific JTAG Pin-out (10, 16, 20 pin)Interface to JTAG Standard Signals: TDI, TDO, TRST, TMS, TCLK

Modern JTAG & USB ICDI ToolsMost JTAG interfaces are on-chip, USB host interface– Rather than a USB to

JTAG Bridge Device– E.g. Jetson – JetPack

or JTAG

TIVA – 10-pin header– IEEE Standard– Or USB to JTAG Bridge

and Monitor (ICDI – In Circuit Debug Interface)

– Used in CEC322

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https://www.jann.cc/2015/05/16/jtag_debugging_nvidia_jetson_tk1_pro_devkit.html

Jetson with Lauterbach JTAGZephyr with Flyswatter