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CCD-based Pixel Detectors by LCFI Andrei Nomerotski (U.Oxford) on behalf of LCFI collaboration May 7 2006, UK HEP Forum Outline LCFI Collaboration Pixel Sensors and their Readout Column-Parallel CCDs Storage Pixels : ISIS Mechanical Studies Summary. - PowerPoint PPT Presentation
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Andrei Nomerotski
1
CCD-based Pixel Detectors by LCFI
Andrei Nomerotski (U.Oxford) on behalf of LCFI collaboration May 7 2006, UK HEP Forum
Outline LCFI Collaboration Pixel Sensors and their Readout
Column-Parallel CCDs Storage Pixels : ISIS
Mechanical Studies Summary
Andrei Nomerotski
2
LCFI :Linear Collider Flavour
Identification
Valencia
Goals : Development of technologies and algorithms for the ILC vertex detector
Andrei Nomerotski
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Pixel Sensors
Traditionally LFCI develops CCD-based sensors
Builds on successes of the SLD vertex detector
The VXD3 upgrade vertex detector: 96 large CCDs, 307 Million pixels (1996)
Andrei Nomerotski
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Vertex Detector for ILC
Main requirements: Excellent point resolution (3-4 μm), ~1 Gigapixel 20x20 μm Low material budget ( 0.1% X0 per layer) Low power dissipation Moderate radiation hardness ( 20 krad/year) Tolerance to Electro-Magnetic Interference (EMI) Operation in 5T magnetic field Fast Readout – The Challenge
Andrei Nomerotski
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The Challenge
What readout speed is needed? If read once per train : occupancy ~200 hits/mm2 : too slow Need to read once accumulated occupancy ~10 hits/mm2
=> 20 times per train = 50µs/MPixel Fastest commercial CCDs ~ 1 ms/MPixel
Two approaches1. Parallel Readout of traditional CCD: CPCCD – information
leaves the sensor as fast as it can 2. Storage Sensors : each pixel has a ‘memory’ filled up during
collisions and read out between trains at slow rate: ISIS technology – information is stored in the sensor
337 ns
2820x
0.2 s
0.95 ms
LC Beam Time Structure:
= one train
Andrei Nomerotski
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“Classic CCD”Readout time
NM/fout
N
M
N
Column Parallel CCD
Readout time = N/fout
M
Simple idea : read out a vector instead of a matrix Readout time shortened by orders of magnitude
BUT
Despite ‘parallel processing’ readout rate is still challenging : 50 MHz clock moves charge 2500 times in 50 µs. 2500x20 µm = 50 mm
Every column needs own amplifier and ADC requires readout chip
Column Parallel CCD
Andrei Nomerotski
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Column Parallel CCD Readout Chip is a difficult but clearly feasible problem
Geometrically concept of columns is similar to the silicon strips - strip detectors have complex readout chips integrated in ladder
However density of channels and 0.1% Xo constraint requires bump-bonding – non-trivial anyway
Difference wrt Strips: to move the charge need to clock all columns of the CCD simultaneously
Simple exercise : typical capacitance of CCD sensor : 100nF 50MHz 10 ns rise time Clock current = 100 nF x 2 V / 10 nsec = 20A ! Voltage drops 20 A x 0.1 Ohm = 2 V Inductance of 1mm long bond wire = 1 nH :
corresponds to 0.3 Ohm at 50 MHz
Driving a full area CPCCD is a major challenge! Need a special high current clock driver Need to be extra careful with the design of clock distribution
Andrei Nomerotski
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CPCCD : LCFI R&D Milestones Established proof of principle for small area
sensors : CPC1 Established proof of principle for readout chip :
CPR1, developed and produced more sophisticated CPR2
Moved on to large area sensors : CPC2 Need to handle the problem of clock driver 1. Design dedicated clock driver : CPD12. Find ways to reduce the CCD capacitance3. Find ways to reduce the required clock voltage
Next slides: Results from prototypes
Andrei Nomerotski
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CPC1 : Two phase CCD, 400 (V) 750 (H) pixels, 20 μm square;
CMOS readout chip (CPR1) designed by the Microelectronics Group at RAL:
0.25 μm process
Charge and voltage amplifiers matching the outputs of CPC1
Correlated double sampling
5-bit flash ADCs and 132-deep FIFO per column
Everything on 20 μm pitch
Size : 6 mm 6.5 mm
Manufactured by IBM
Bump-bonded by VTT (Finland) using solder bumpsBump-bonded CPC1/CPR1 in a test PCB
CPC1 Bump-bonded to CPR1
Andrei Nomerotski
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5.9 keV X-ray hits, 1 MHz column-parallel readout
Voltage outputs, non-inverting (negative signals)
Noise 60 e-Charge outputs, inverting (positive signals)
Noise 100 e-
First time e2V CCDs have been bump-bonded
High quality bumps, but assembly yield only 30% : mechanical damage during compression suspected
Differential non-linearity in ADCs (100 mV full scale) : addressed in CPR2
Bump bonds on CPC1 under microscope
CPC1/CPR1 Performance
K.Stefanov RAL
Andrei Nomerotski
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CPR2 designed for CPC2
Results from CPR1 taken into account
Numerous test features
Size : 6 mm 9.5 mm
0.25 μm CMOS process (IBM)
Manufactured and delivered February 2005
Bump bond pads
Wire/Bump bond pads
CPR1
CPR2
Voltage and charge amplifiers 125 channels each
Analogue test I/O
Digital test I/O
5-bit flash ADCs on 20 μm pitch
Cluster finding logic (22 kernel)
Sparse readout circuitry
FIFO
Next Generation CPCCD Readout Chip – CPR2
Steve Thomas, RAL
Andrei Nomerotski
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CPR2 Test Results
Tim Woolliscroft, Liverpool U
●Tests on the cluster finder: works!
● Several minor problems, but chip is usable
● Design occupancy is 1%
● Cluster separation studies:
Errors as the distance between the clusters decreases
Reveal dead time
Many of the findings have already been input into the CPR2A design
Tim Woolliscroft, Liverpool U
Parallel cluster finder with 22 kernel
Global threshold
Upon exceeding the threshold, 49 pixels around the cluster are flagged for readout
Test clusters in Sparsified output
Andrei Nomerotski
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Clock bus
Main clock wire bonds
Main clock wire bonds
CPR1 CPR2
Temperature diode on
CCD
Charge injection
Four 1-stage and 2-stage SF in adjacent
columns
Four 2-stage SF in adjacent columns
Standard Field-enhanced Standard
No connections
this side
Image area
Extra pads for clock monitoring and
drive every 6.5 mm
Next Generation CPCCD : CPC2
Three different chip sizes with common design:
CPC2-70 : 92 mm 15 mm image area
CPC2-40 : 53 mm long
CPC2-10 : 13 mm long
Compatible with CPR1 and CPR2
Two charge transport sections
Choice of epitaxial layers for different depletion depth: 100 .cm (25 μm thick) and 1.5 k.cm (50 μm thick)
Andrei Nomerotski
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CPC2 + ISIS1 WaferISIS1
CPC2-70
CPC2-40
CPC2-10
5” wafers
One CPC2-70 : 105 mm 17 mm total chip size
Two CPC2-40 per wafer
6 CPC2-10 per wafer
14 In-situ Storage Image Sensors (ISIS1)
3 wafers delivered
Andrei Nomerotski
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Clock monitor pads
CPR1/CPR2 pads
CPC2-40 in MB4.0
Johan Fopma, Oxford UTransformer drive for CPC2
“Busline-free” CCD: the whole image area serves as a distributed busline
50 MHz achievable with suitable driver in CPC2-10 and CPC2-40
First clocking tests have been done
Transformer
Andrei Nomerotski
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55Fe spectrum from CPC2-10 at 1 MHz
● First 55Fe spectrum at 1 MHz, -40 C, reset every pixel
CPC2: First Results
K.Stefanov RAL
Andrei Nomerotski
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IC driver: CPD1
Transformer is bulky: IC driver could be a better solution;
Design of the first CPCCD driver chip (CPD1) has started, manufacture in June
CPD1: 2-phase CMOS driver chip for 20 Amp current load at 25 MHz (L2-L5 CCDs)
0.35 μm process, size 3 x 8 mm2
32 W peak power but 0.5% duty cycle
Thermal and electromigration issues seems to be under control
Clock Drivers for CPC2 Transformer Driver
Requirements: 2 Vpk-pk at 50 MHz over 40 nF (half CPC2-40);
Planar air core transformers on 10-layer PCB, 1 cm square
Parasitic inductance of bond wires is a major effect – fully simulated;
Brian Hawes, Oxford U
Andrei Nomerotski
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Next Steps for CPCCD
Evaluate performance of CPC2 bump-bonded to CPC2/CPR2
Designing with e2V test devices to study how to reduce CCD capacitance and how to reduce clock voltage Theoretically can achieve factor of 4 reduction
in C
Design of CPC3 will depend on results of these tests
Andrei Nomerotski
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Radiation Damage Effects in CCDs: Simulations
Simulation at 50 MHz
Operating window
L. Dehimi, K. Bekhouche (Biskra U); G. Davies, C. Bowdery, A.Sopczak (Lancaster U)
●Full 2D simulation based on ISE-TCAD developed
● Trapped signal electrons can be counted
● CPU-intensive and time consuming
● Simpler analytical model also used, compares well with the full simulation
● Window of low Charge Transfer Inefficiency (CTI) between -40 C and 0 C
● Will be verified by measurements on CPC2
Signal density of trapped electrons in 2D
Andrei Nomerotski
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Storage Pixels Industry analogy is “Burst mode” : capturing a limited
number of images at short intervals Burst mode imagers are available commercially (ex. DALSA)
with rates up to 100MHz : the rate is limited by the charge transfer between neighboring cells
Memory is implemented as a CCD register associated with an imaging pixel : whatever one can fit in an area of one pixel
2003: Dart bursting a ballon : 100 consecutive frames at 1M frame/sec
Andrei Nomerotski
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Storage Pixels as Particle Detectors
ILC requirements : capture charge every 50 us 20kHz – no problem
Challenges : Used as particle (not visible light) detector
– need efficient charge collection from the whole area
Need to fit 20 cell CCD register into 20x20 square micron pixel (together with photogate and some logic)
Need a more complicated than pure CCD process
Andrei Nomerotski
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In-situ Storage Image Sensor : ISIS
Charge is collected into a photogate Each pixel has its own 20-cell CCD register : store raw charge during collisions Increased resistance to RF Column-parallel readout during quiet time at ~1 MHz: much reduced clocking
requirements
To column load
Source followerReset transistor Row select transistor
p+ shielding implant
n+
buried channel (n)
storage
pixel #1
storage
pixel #20 sense node (n+)
Charge collection
row select
reset gate
VDD
p+ well
reflected charge
reflected charge
photogate
transfer
gate
output
gate
High resistivity epitaxial layer (p)
Andrei Nomerotski
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In-situ Storage Image Sensor (ISIS)
RG RD OD RSEL
Column transistor
Additional ISIS advantages:
~100 times more radiation hard than CCDs – less charge transfers
Easier to drive because of the low clock frequency: 20 kHz during capture, 1 MHz during readout
ISIS combines CCDs, active pixel transistors and edge electronics in one device: specialised process
Development and design of ISIS is more ambitious goal than CPCCD
“Proof of principle” device (ISIS1) designed and manufactured by e2V Technologies
On-
chip
logi
c
On-
chip
sw
itche
s
Global Photogate and Transfer gate
ROW 1: CCD clocks
ROW 2: CCD clocks
ROW 3: CCD clocks
ROW 1: RSEL
Global RG, RD, OD
5 μm
Andrei Nomerotski
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Output and reset transistors
Photogate aperture (8 μm square)
CCD (56.75 μm pixels)
The ISIS1 Cell
OG RG OD RSEL
OUT
Column transistor
1616 array of ISIS cells with 5-pixel buried channel CCD storage register each;
Cell pitch 40 μm 160 μm, no edge logic (pure CCD process)
Chip size 6.5 mm 6.5 mm
Andrei Nomerotski
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Tests of ISIS1
Tests with Fe-55 source The top row and 2 side columns are not protected and collect diffusing charge
The bottom row is protected by the output circuitry
ISIS1 without p-well tested first and works OK
ISIS1 with p-well has very large transistor thresholds, permanently off
K.Stefanov RAL
Andrei Nomerotski
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Mechanical OptionsTarget of 0.1% X0 per layer (100μm
silicon equivalent) Unsupported Silicon
Longitudinal tensioning provides stiffness No lateral stability Not believed to be promising
Thin Substrates Detector can be thinned to epitaxial layer (~20 μm) Silicon glued to low mass substrate for lateral stability Longitudinal stiffness still from moderate tension Beryllium has best specific stiffness
Rigid Structures Foams look very promising Will start to investigate shell structure supports
Andrei Nomerotski
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Laser Survey System
Laser displacement meter Z precision ~ 1 µm
2D motorised stage X-Y precision < 1 µm
Ladder in cryostat: ∆T ~ 100C
Fast: 1D scan < 1 minute Scan during cooling E.Johnson RAL
Andrei Nomerotski
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Ladder testing with Be and Carbon Fibre Beryllium substrate
Minimum thickness 0.15% X0
Good qualitative agreement from FEA models and measurement
Carbon Fibre substrate Better CTE match than Be ~0.09% X0, no rippling to
<200K lateral stability insufficient
Tension Silicon
GlueBeryllium
J.Goldstein RAL
Andrei Nomerotski
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Rigid Structures: Foams Properties:
Open-cell foam Macroscopically uniform No tensioning needed
3% RVC prototype Sandwich with foam core 0.09% X0
Mechanically unsatisfactory Working on glue application
8% Silicon Carbide prototype Single-sided: substrate + foam 0.14% X0
3-4% believed possible
20 µm silicon
1.5 mm silicon carbide
Andrei Nomerotski
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Silicon Carbide Foam
Glue “pillars” (right plot) are better than thin glue layer (left plot)
Andrei Nomerotski
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Cooling Studies Gas cooling test stand established Cold nitrogen flow Model of 1/4 detectorMeasurements from test stand:
CFD simulation of the same setup In agreement with mesurements
Next step: more detailed comparison
S.Yang, Oxford
G.Leithall RAL
Andrei Nomerotski
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Summary
LCFI is a viable and growing collaboration to develop technologies and algorithms for VD
First generation sensors extensively studied Column parallel CCD principle proven
First results from the second generation of sensors
and readout chips Detector-scale CCDs Sparsified readout Developing advanced clock drivers First prototypes of storage devices
Mechanics : 0.1% X0 ladders seems achievable