CC1000 Data Sheet 2 2

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SmartRFSmartRFSmartRFSmartRF CC1000

Chipcon AS SmartRFCC1000 Datasheet (rev. 2.2) 2004-04-22 Page 1 of 50

CC1000Single Chip Very Low Power RF Transceiver

Applications Very low power UHF wireless data

transmitters and receivers

315 / 433 / 868 and 915 MHz ISM/SRDband systems

RKE Two-way Remote Keyless Entry

Home automation Wireless alarm and security systems AMR Automatic Meter Reading Low power telemetry Game Controllers and advanced toys

Product Description

CC1000 is a true single-chip UHF trans-ceiver designed for very low power andvery low voltage wireless applications. Thecircuit is mainly intended for the ISM(Industrial, Scientific and Medical) andSRD (Short Range Device) frequencybands at 315, 433, 868 and 915 MHz, butcan easily be programmed for operation atother frequencies in the 300-1000 MHzrange.

The main operating parameters ofCC1000

can be programmed via a serial bus, thus

making CC1000a very flexible and easy touse transceiver. In a typical system

CC1000 will be used together with amicrocontroller and a few external passivecomponents.

CC1000 is based on Chipcons SmartRF

technology in 0.35 m CMOS.

Features

True single chip UHF RF transceiver Very low current consumption Frequency range 300 1000 MHz

Integrated bit synchroniser High sensitivity (typical -110 dBm at 2.4kBaud)

Programmable output power 20 to10 dBm

Small size (TSSOP-28 package) Low supply voltage (2.1 V to 3.6 V) Very few external components required No external RF switch / IF filter required RSSI output

Single port antenna connection FSK data rate up to 76.8 kBaud Complies with EN 300 220 and FCC

CFR47 part 15 Programmable frequency in 250 Hzsteps makes crystal temperature driftcompensation possible without TCXO

Suitable for frequency hoppingprotocols

Development kit available Easy-to-use software for generating the

CC1000configuration data

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Table of Contents

Absolute Maximum Ratings .......................................................................................... 4

Operating Conditions.................................................................................................... 4

Electrical Specifications................................................................................................4

Pin Assignment.............................................................................................................8

Circuit Description.........................................................................................................9

Application Circuit ....................................................................................................... 10

Configuration Overview............................................................................................... 12

Configuration Software ............................................................................................... 12

3-wire Serial Configuration Interface........................................................................... 13

Microcontroller Interface ............................................................................................. 15

Signal interface ........................................................................................................... 16

Bit synchroniser and data decision .............................................................................19

Receiver sensitivity versus data rate and frequency separation ................................. 22

Frequency programming.............................................................................................23

Recommended RX settings for ISM frequencies........................................................24

VCO............................................................................................................................25

VCO and PLL self-calibration ..................................................................................... 25

VCO and LNA current control .....................................................................................28

Power management....................................................................................................28

Input / Output Matching ..............................................................................................31

Output power programming........................................................................................ 32

RSSI output ...............................................................................................................33

IF output.....................................................................................................................34

Crystal oscillator..........................................................................................................35

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Optional LC Filter........................................................................................................ 36

System Considerations and Guidelines......................................................................37

PCB Layout Recommendations..................................................................................38

Antenna Considerations ............................................................................................. 38

Configuration registers................................................................................................ 39

Package Description (TSSOP-28) ..............................................................................48

Soldering Information..................................................................................................48

Plastic Tube Specification........................................................................................... 48

Carrier Tape and Reel Specification........................................................................... 48

Ordering Information...................................................................................................49

General Information.................................................................................................... 49

Address Information.................................................................................................... 50

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Absolute Maximum Ratings

Parameter Min. Max. Units Condition

Supply voltage, VDD -0.3 5.0 VVoltage on any pin -0.3 VDD+0.3,

max 5.0V

Input RF level 10 dBm

Storage temperature range -50 150 CReflow soldering temperature 260 C T = 10 s

Under no circumstances the absolutemaximum ratings given above should beviolated. Stress exceeding one or more of

the limiting values may cause permanentdamage to the device.

Caution!ESD sensitive device.Precaution should be used when handlingthe device in order to prevent permanent

damage.

Operating Conditions

Parameter Min. Typ. Max. Unit Condition / Note

RF Frequency Range 300 1000 MHz Programmable in steps of 250 Hz

Operating ambient temperaturerange

-40 85 C

Supply voltage 2.1 3.0 3.6 V Note: The same supply voltageshould be used for digital (DVDD)

and analogue (AVDD) power.

Electrical SpecificationsTc = 25C, VDD = 3.0 V if nothing else stated


Transmit Section

Transmit data rate 0.6 76.8 kBaud NRZ or Manchester encoding.76.8 kBaud equals 76.8 kbit/susing NRZ coding. See page 16.

Binary FSK frequency separation 0 65 kHzThe frequency separation isprogrammable in 250 Hz steps.65 kHz is the maximumguaranteed separation at 1 MHzreference frequency. Largerseparations can be achieved athigher reference frequencies.

Output power433 MHz868 MHz

-20-20

105

dBmdBm

Delivered to 50 load.The output power isprogrammable.

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RF output impedance433/868 MHz

140 / 80 Transmit mode. For matchingdetails see Input/ outputmatching p.31.

Harmonics -20 dBc An external LC or SAW filtershould be used to reduceharmonics emission to complywith SRD requirements. Seep.36.

Receive Section

Receiver Sensitivity, 433 MHzOptimum sensitivity (9.3 mA)Low current consumption (7.4 mA)

Receiver Sensitivity, 868 MHzOptimum sensitivity (11.8 mA)

Low current consumption (9.6 mA)

-110-109

-107

-105

dBmdBm

dBm

dBm

2.4 kBaud, Manchester codeddata, 64 kHz frequencyseparation, BER = 10

-3

See Table 6 and Table 7 page 22for typical sensitivity figures at

other data rates.

System noise bandwidth 30 KHz 2.4 kBaud, Manchester codeddata

Cascaded noise figure433/868 MHz

12/13 dB

Saturation 10 dBm 2.4 kBaud, Manchester codeddata, BER = 10

-3

Input IP3 -18 dBm From LNA to IF output

Blocking 40 dBc At +/- 1 MHz

LO leakage -57 dBm

Input impedance88-j2670-j2652-j752-j4

Receive mode, series equivalentat 315 MHzat 433 MHzat 868 MHz.at 915 MHzFor matching details see Input/output matching p. 31.

Turn on time 11 128 Baud The turn-on time is determined bythe demodulator settling time,which is programmable. See p.19

IF Section

Intermediate frequency (IF) 15010.7

kHzMHz

Internal IF filterExternal IF filter

IF bandwidth 175 kHz

RSSI dynamic range -105 -50 dBm

RSSI accuracy 6 dB See p.33 for details

RSSI linearity 2 dB

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Frequency Synthesiser

Section

Crystal Oscillator Frequency 3 16 MHz Crystal frequency can be 3-4, 6-8or 9-16 MHz. Recommendedfrequencies are 3.6864, 7.3728,11.0592 and 14.7456. See page35 for details.

Crystal frequency accuracyrequirement

5025

ppm 433 MHz868 MHzThe crystal frequency accuracyand drift (ageing andtemperature dependency) willdetermine the frequencyaccuracy of the transmittedsignal.

Crystal operation Parallel C171 and C181 are loadingcapacitors, see page 35

Crystal load capacitance 121212

221616

303016

pFpFpF

3-4 MHz, 22 pF recommended6-8 MHz, 16 pF recommended9-16 MHz, 16 pF recommended

Crystal oscillator start-up time 51.52

msmsms

3.6864 MHz, 16 pF load7.3728 MHz, 16 pF load16 MHz, 16 pF load

Output signal phase noise -85 dBc/Hz At 100 kHz offset from carrier

PLL lock time (RX / TX turn time) 200 s Up to 1 MHz frequency step

PLL turn-on time, crystal oscillatoron in power down mode

250 s Crystal oscillator running

Digital Inputs/Outputs

Logic "0" input voltage 0 0.3*VDD V

Logic "1" input voltage 0.7*VDD VDD V

Logic "0" output voltage 0 0.4 V Output current -2.5 mA,3.0 V supply voltage

Logic "1" output voltage 2.5 VDD V Output current 2.5 mA,3.0 V supply voltage

Logic "0" input current NA -1 A Input signal equals GND

Logic "1" input current NA 1 A Input signal equals VDD

DIO setup time 20 ns TX mode, minimum time DIOmust be ready before the positiveedge of DCLK

DIO hold time 10 ns TX mode, minimum time DIOmust be held after the positiveedge of DCLK

Serial interface (PCLK, PDATA andPALE) timing specification

See Table 2 page 14

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Current Consumption

Power Down mode 0.2 1 A Oscillator core off

Current Consumption,receive mode 433/868 MHz

7.4/9.6 mA Current is programmable and canbe increased for improvedsensitivity

Current Consumption,average in receive mode usingpolling 433/868 MHz

74/96 A Polling controlled by micro-controller using 1:100 receive topower down ratio

Current Consumption,transmit mode 433/868 MHz:

P=0.01mW (-20 dBm)

P=0.3 mW (-5 dBm)

P=1 mW (0 dBm)

P=3 mW (5 dBm)

P=10 mW (10 dBm)

5.3/8.6

8.9/13.8

10.4/16.5

14.8/25.4

26.7/NA

mA

mA

mA

mA

mA

The ouput power is delivered to a

50load, see also p. 32

Current Consumption, crystal osc.

Current Consumption, crystal osc.and bias

Current Consumption, crystal osc.,bias and synthesiser, RX/TX

3080105

860

4/55/6

AAA

A

mAmA

3-8 MHz, 16 pF load9-14 MHz, 12 pF load14-16 MHz, 16 pF load

< 500 MHz> 500 MHz

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Pin Assignment

Pin no. Pin name Pin type Description

1 AVDD Power (A) Power supply (3 V) for analog modules (mixer and IF)2 AGND Ground (A) Ground connection (0 V) for analog modules (mixer and IF)

3 RF_IN RF Input RF signal input from antenna

4 RF_OUT RF output RF signal output to antenna

5 AVDD Power (A) Power supply (3 V) for analog modules (LNA and PA)

6 AGND Ground (A) Ground connection (0 V) for analog modules (LNA and PA)

7 AGND Ground (A) Ground connection (0 V) for analog modules (PA)

8 AGND Ground (A) Ground connection (0 V) for analog modules (VCO and prescaler)

9 AVDD Power (A) Power supply (3 V) for analog modules (VCO and prescaler)

10 L1 Analog input Connection no 1 for external VCO tank inductor

11 L2 Analog input Connection no 2 for external VCO tank inductor

12 CHP_OUT(LOCK)

Analog output Charge pump current outputThe pin can also be used as PLL Lock indicator. Output is highwhen PLL is in lock.

13 R_BIAS Analog output Connection for external precision bias resistor (82 k, 1%)

14 AGND Ground (A) Ground connection (0 V) for analog modules (backplane)15 AVDD Power (A) Power supply (3 V) for analog modules (general)

16 AGND Ground (A) Ground connection (0 V) for analog modules (general)

17 XOSC_Q2 Analog output Crystal, pin 2

18 XOSC_Q1 Analog input Crystal, pin 1, or external clock input

19 AGND Ground (A) Ground connection (0 V) for analog modules (guard)

20 DGND Ground (D) Ground connection (0 V) for digital modules (substrate)

21 DVDD Power (D) Power supply (3 V) for digital modules

22 DGND Ground (D) Ground connection (0 V) for digital modules

23 DIO Digitalinput/output

Data input/output. Data input in transmit mode. Data output inreceive mode

24 DCLK Digital output Data clock for data in both receive and transmit mode

25 PCLK Digital input Programming clock for 3-wire bus

26 PDATA Digitalinput/output

Programming data for 3-wire bus. Programming data input forwrite operation, programming data output for read operation

27 PALE Digital input Programming address latch enable for 3-wire bus. Internal pull-up.28 RSSI/IF Analog output The pin can be used as RSSI or 10.7 MHz IF output to optional

external IF and demodulator. If not used, the pin should be leftopen (not connected).

A=Analog, D=Digital(Top View)

1

14 15

AVDD

AGND

RF_IN

RF_OUT

AVDD

AGND

AGND

AGND

AVDD

L1

L2

R_BIAS

CHP_OUT

AGND

CC1000

2

3

4

6

5

7

8

9

11

12

13

10

28RSSI/IF

PALE

PDATA

PCLK

DCLK

DIO

DGND

DVDD

DGND

AGND

XOSC_Q1

AGND

XOSC_Q2

AVDD

27

26

25

23

24

22

21

20

18

17

16

19

1

14 15

AVDD

AGND

RF_IN

RF_OUT

AVDD

AGND

AGND

AGND

AVDD

L1

L2

R_BIAS

CHP_OUT

AGND

CC1000

2

3

4

6

5

7

8

9

11

12

13

10

28RSSI/IF

PALE

PDATA

PCLK

DCLK

DIO

DGND

DVDD

DGND

AGND

XOSC_Q1

AGND

XOSC_Q2

AVDD

RSSI/IF

PALE

PDATA

PCLK

DCLK

DIO

DGND

DVDD

DGND

AGND

XOSC_Q1

AGND

XOSC_Q2

AVDD

27

26

25

23

24

22

21

20

18

17

16

19

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Circuit Description

Figure 1. Simplified block diagram of the CC1000

A simplified block diagram of CC1000 isshown in Figure 1. Only signal pins areshown.

In receive mode CC1000is configured as a

traditional superheterodyne receiver. TheRF input signal is amplified by the low-noise amplifier (LNA) and converted downto the intermediate frequency (IF) by themixer (MIXER). In the intermediatefrequency stage (IF STAGE) thisdownconverted signal is amplified andfiltered before being fed to thedemodulator (DEMOD). As an option aRSSI signal, or the IF signal after themixer is available at the RSSI/IF pin. After

demodulation CC1000 outputs the digitaldemodulated data on the pin DIO.

Synchronisation is done on-chip providingdata clock at DCLK.

In transmit mode the voltage controlledoscillator (VCO) output signal is feddirectly to the power amplifier (PA). TheRF output is frequency shift keyed (FSK)by the digital bit stream fed to the pin DIO.

The internal T/R switch circuitry makes theantenna interface and matching very easy.

The frequency synthesiser generates thelocal oscillator signal which is fed to theMIXER in receive mode and to the PA intransmit mode. The frequency synthesiserconsists of a crystal oscillator (XOSC),phase detector (PD), charge pump(CHARGE PUMP), VCO, and frequencydividers (/R and /N). An external crystalmust be connected to XOSC, and only anexternal inductor is required for the VCO.

The 3-wire digital serial interface(CONTROL) is used for configuration.

PDATA, PCLK, PALE

LNA

PA

DEMOD

VCO PD OSC~

/N

MIXER

CHARGE

PUMP

L1

RF_IN DIO

CHP_OUT

IF STAGE

RF_OUT

RSSI/IF

3

CONTROL

XOSC_Q2

XOSC_Q1

/R

DCLK

L2

LPF

BIAS R_BIAS

PDATA, PCLK, PALE

LNA

PA

DEMOD

VCO PD OSC~

/N

MIXER

CHARGE

PUMP

L1

RF_IN DIO

CHP_OUT

IF STAGE

RF_OUT

RSSI/IF

3

CONTROL

XOSC_Q2

XOSC_Q1

/R

DCLK

L2

LPF

BIAS R_BIAS

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Application Circuit

Very few external components are

required for the operation of CC1000. Atypical application circuit is shown in Figure2. Component values are shown in Table1.

Input / output matchingC31/L32 is the input match for thereceiver. L32 is also a DC choke forbiasing. C41, L41 and C42 are used to

match the transmitter to 50 . An internalT/R switch circuit makes it possible toconnect the input and output together and

match the CC1000 to 50 in both RX andTX mode. See Input/output matchingp.31 for details.

VCO inductorThe VCO is completely integrated exceptfor the inductor L101.

Component values for the matching

network and VCO inductor are easilycalculated using the SmartRF Studiosoftware.

Additional filteringAdditional external components (e.g. RFLC or SAW-filter) may be used in order toimprove the performance in specificapplications. See also Optional LC filterp.36 for further information.

Power supply decoupling and filteringPower supply decoupling and filtering must

be used (not shown in the applicationcircuit). The placement and size of thedecoupling capacitors and the powersupply filtering are very important toachieve the optimum performance.Chipcon provides a reference design(CC1000PP) that should be followed veryclosely.

Figure 2. Typical CC1000application circuit (power supply decoupling not shown)

LC-filter

1

14 15

AVDD

AGND

RF_IN

RF_OUT

AGND

AGND

AGND

AVDD

L1

AVDD

L2

R_BIAS

CHP_OUT

AGND

RSSI/IF

PALE

PDATA

PCLK

DCLK

DIO

DVDD

DGND

AGND

XOSC_Q1

AGND

XOSC_Q2

AVDD

L101

TO/FROM

MICROCONTROLLER

2

3

4

6

5

7

8

9

11

12

13

10

28

27

26

25

23

24

22

21

20

18

17

16

19

C181C181C171C171

Monopole

antenna

(50 Ohm)

CC1000

AVDD=3V

DVDD=3V

Optional

XTALXTALNC

NC

L41C41

C42

L32

C31

R131

DGND

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Item 315 MHz 433 MHz 868 MHz 915 MHz

C31 8.2 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 10 pF, 5%, C0G, 0603 10 pF, 5%, C0G, 0603

C41 2.2 pF, 5%, C0G, 0603 8.2 pF, 5%, C0G, 0603 Not used Not used

C42 5.6 pF, 5%, C0G, 0603 5.6 pF, 5%, C0G, 0603 4.7 pF, 5%, C0G, 0603 4.7 pF, 5%, C0G, 0603

C141 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603C151 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603

L32 39 nH, 10%, 0805(Coilcraft 0805CS-390XKBC)

68 nH, 10%, 0805(Coilcraft 0805CS-680XKBC)



L41 20 nH, 10%, 0805(Coilcraft 0805HQ-20NXKBC)

6.2 nH, 10%, 0805(Coilcraft 0805HQ-6N2XKBC)



L101 56 nH, 5%, 0805(Koa KL732ATE56NJ)

33 nH, 5%, 0805(Koa KL732ATE33NJ)

4.7 nH, 5%, 0805(Koa KL732ATE4N7C)

4.7 nH, 5%, 0805(Koa KL732ATE4N7C)

R131 82 k, 1%, 0603 82 k, 1%, 0603 82 k, 1%, 0603 82 k, 1%, 0603XTAL 14.7456 MHz crystal,

16 pF load14.7456 MHz crystal,16 pF load

14.7456 MHz crystal,16 pF load

14.7456 MHz crystal,16 pF load

Note: Items shaded are different for different frequencies

Table 1. Bill of materials for the application circuit

Note that the component values for868/915 MHz can be the same. However,it is important the layout is optimised forthe selected VCO inductor in order tocentre the tuning range around theoperating frequency to account for inductortolerance. The VCO inductor must beplaced very close and symmetrical withrespect to the pins (L1 and L2).

Chipcon provide reference layouts thatshould be followed very closely in order toachieve the best performance. TheCC1000PP Plug & Play reference designcan be downloaded from the Chipconwebsite

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Configuration Overview

CC1000 can be configured to achieve the

best performance for different applications.Through the programmable configurationregisters the following key parameters canbe programmed:

Receive / transmit mode RF output power Frequency synthesiser key parameters:

RF output frequency, FSK frequency

separation (deviation), crystal oscillator

reference frequency Power-down / power-up mode Crystal oscillator power-up / power

down

Data rate and data format (NRZ,Manchester coded or UART interface)

Synthesiser lock indicator mode Optional RSSI or external IF

Configuration Software

Chipcon provides users of CC1000with a

software program, SmartRF Studio(Windows interface) that generates all

necessary CC1000 configuration databased on the user's selections of variousparameters. These hexadecimal numberswill then be the necessary input to themicrocontroller for the configuration of

CC1000. In addition the program willprovide the user with the componentvalues needed for the input/outputmatching circuit and the VCO inductor.

Figure 3 shows the user interface of the

CC1000configuration software.

Figure 3. SmartRFStudio user interface

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3-wire Serial Configuration Interface

CC1000 is configured via a simple 3-wire

interface (PDATA, PCLK and PALE).There are 28 8-bit configuration registers,each addressed by a 7-bit address. ARead/Write bit initiates a read or write

operation. A full configuration of CC1000requires sending 22 data frames of 16 bitseach (7 address bits, R/W bit and 8 databits). The time needed for a fullconfiguration depend on the PCLKfrequency. With a PCLK frequency of 10MHz the full configuration is done in less

than 46 s. Setting the device in powerdown mode requires sending one frame

only and will in this case take less than 2s. All registers are also readable.

In each write-cycle 16 bits are sent on thePDATA-line. The seven most significantbits of each data frame (A6:0) are theaddress-bits. A6 is the MSB (MostSignificant Bit) of the address and is sentas the first bit. The next bit is the R/W bit(high for write, low for read). Duringaddress and R/W bit transfer the PALE(Program Address Latch Enable) must bekept low. The 8 data-bits are then

transferred (D7:0). See Figure 4.

The timing for the programming is also

shown in Figure 4 with reference to Table2. The clocking of the data on PDATA isdone on the negative edge of PCLK. Whenthe last bit, D0, of the 8 data-bits has beenloaded, the data word is loaded in theinternal configuration register.

The configuration data is stored in internalRAM. The data is retained during power-down mode, but not when the power-supply is turned off. The registers can beprogrammed in any order.

The configuration registers can also beread by the microcontroller via the sameconfiguration interface. The seven addressbits are sent first, then the R/W bit set low

to initiate the data read-back. CC1000 thenreturns the data from the addressedregister. PDATA is in this case used as anoutput and must be tri-stated (or set high nthe case of an open collector pin) by themicrocontroller during the data read-back(D7:0). The read operation is illustrated inFigure 5.

Figure 4. Configuration registers write operation

PCLK

PDATA

PALE

Address Write mode

6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Data byte

THD

TSA

TCH,min

TCL,min

THA

W

TSD

TSA

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Figure 5. Configuration registers read operation

Parameter Symbol Min Max Units Conditions

PCLK, clockfrequency

FCLOCK - 10 MHz

PCLK lowpulseduration

TCL,min 50 ns The minimum time PCLK must be low.

PCLK highpulseduration

TCH,min 50 ns The minimum time PCLK must be high.

PALE setuptime

TSA 10 - ns The minimum time PALE must be low beforenegative edge of PCLK.

PALE hold

time

THA 10 - ns The minimum time PALE must be held low after

thepositiveedge of PCLK.

PDATA setuptime

TSD 10 - ns The minimum time data on PDATA must be readybefore the negative edge of PCLK.

PDATA holdtime

THD 10 - ns The minimum time data must be held at PDATA,after the negative edge of PCLK.

Rise time Trise 100 ns The maximum rise time for PCLK and PALE

Fall time Tfall 100 ns The maximum fall time for PCLK and PALE

Note: The set-up- and hold-times refer to 50% of VDD.

Table 2. Serial interface, timing specification

PCLK

Address Read mode

6 5 4 3 2 1 0 R 7 6 5 4 3 2 1 0

Data byte

PALE

PDATA

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Microcontroller Interface

Used in a typical system, CC1000 will

interface to a microcontroller. Thismicrocontroller must be able to:

Program CC1000 into different modesvia the 3-wire serial configurationinterface (PDATA, PCLK and PALE).

Interface to the bi-directionalsynchronous data signal interface(DIO and DCLK).

Optionally the microcontroller can do

data encoding / decoding. Optionally the microcontroller can

monitor the frequency lock status frompin CHP_OUT (LOCK).

Optionally the microcontroller canmonitor the RSSI output for signalstrength acquisition.

Connecting the microcontrollerThe microcontroller uses 3 output pins for

the configuration interface (PDATA, PCLKand PALE). PDATA should be a bi-directional pin for data read-back. A bi-directional pin is used for data (DIO) to betransmitted and data received. DCLKproviding the data timing should beconnected to a microcontroller input.Optionally another pin can be used tomonitor the LOCK signal (available at theCHP_OUT pin). This signal is logic levelhigh when the PLL is in lock. See Figure 6.

Also the RSSI signal can be connected to

the microcontroller if it has an analogueADC input.

The microcontroller pins connected to

PDATA and PCLK can be used for otherpurposes when the configuration interfaceis not used. PDATA and PCLK are highimpedance inputs as long as PALE is high.

PALE has an internal pull-up resistor andshould be left open (tri-stated by themicrocontroller) or set to a high levelduring power down mode in order toprevent a trickle current flowing in the pull-up. The pin state in power down mode issummarized in Table 3.

Pin Pin state Note

PDATA Input Should be driven high or low

PCLK Input Should be driven high or low

PALE Input with internal pull-up resistor

Should be driven high or high-impedance to minimizepower consumption

DIO Input Should be driven high or low

DCLK High-impedanceoutput

Table 3. CC1000 pins in power-down mode

CC1000CC1000CC1000CC1000

PDATA

PCLK

PALE

DIO

CHP_OUT

(LOCK)

Micro-

controller

DCLK

(Optional)

RSSI/IF

(Optional)

ADC

Figure 6. Microcontroller interface

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Signal interface

The signal interface consists of DIO andDCLK and is used for the data to betransmitted and data received. DIO is thebi-directional data line and DCLK providesa synchronous clock both during datatransmission and data reception.

The CC1000 can be used with NRZ (Non-Return-to-Zero) data or Manchester (alsoknown as bi-phase-level) encoded data.

CC1000can also synchronise the data fromthe demodulator and provide the dataclock at DCLK.

CC1000 can be configured for threedifferent data formats:

Synchronous NRZ mode.In transmit mode

CC1000 provides the data clock at DCLK,and DIO is used as data input. Data is

clocked into CC1000 at the rising edge ofDCLK. The data is modulated at RF

without encoding. CC1000 can beconfigured for the data rates 0.6, 1.2, 2.4,4.8, 9.6, 19.2, 38.4 or 76.8 kbit/s. For 38.4

and 76.8 kbit/s a crystal frequency of14.7456 MHz must be used. In receive

mode CC1000 does the synchronisationand provides received data clock at DCLKand data at DIO. The data should beclocked into the interfacing circuit at therising edge of DCLK. See Figure 7.

Synchronous Manchester encoded mode.

In transmit mode CC1000provides the dataclock at DCLK, and DIO is used as data

input. Data is clocked into CC1000 at therising edge of DCLK and should be in NRZ

format. The data is modulated at RF withManchester code. The encoding is done

by CC1000. In this mode CC1000 can beconfigured for the data rates 0.3, 0.6, 1.2,2.4, 4.8, 9.6, 19.2 or 38.4 kbit/s. The 38.4kbit/s rate corresponds to the maximum76.8 kBaud due to the Manchesterencoding. For 38.4 and 76.8 kBaud acrystal frequency of 14.7456 MHz must be

used. In receive mode CC1000 does thesynchronisation and provides receiveddata clock at DCLK and data at DIO.

CC1000does the decoding and NRZ data ispresented at DIO. The data should beclocked into the interfacing circuit at therising edge of DCLK. See Figure 8.

Transparent Asynchronous UART mode.In transmit mode DIO is used as datainput. The data is modulated at RF withoutsynchronisation or encoding. In receivemode the raw data signal from thedemodulator is sent to the output. Nosynchronisation or decoding of the signal

is done in CC1000and should be done bythe interfacing circuit. The DCLK pin isused as data output in this mode. Datarates in the range from 0.6 to 76.8 kBaudcan be used. For 38.4 and 76.8 kBaud acrystal frequency of 14.7456 MHz must beused. See Figure 9.

Manchester encoding and decodingIn the Synchronous Manchester encoded

mode CC1000 uses Manchester coding

when modulating the data. The CC1000also performs the data decoding andsynchronisation. The Manchester code isbased on transitions; a 0 is encoded as alow-to-high transition, a 1 is encoded asa high-to-low transition. See Figure 10.

The CC1000 can detect a Manchesterdecoding violation and will set aManchester Violation Flag when such aviolation is detected in the incoming signal.The threshold limit for the ManchesterViolation can be set in the MODEM1register. The Manchester Violation Flagcan be monitored at the CHP_OUT

(LOCK) pin, configured in the LOCKregister.

The Manchester code ensures that thesignal has a constant DC component,which is necessary in some FSKdemodulators. Using this mode alsoensures compatibility with CC400/CC900designs.

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Figure 7. Synchronous NRZ mode

Figure 8. Synchronous Manchester encoded mode

DIO

DCLK

RF

Clock provided by CC1000

FSK modulating signal (NRZ),

internal in CC1000

Data provided by microcontroller

Transmitter side:


Demodulated signal (NRZ),

internal in CC1000

Data provided by CC1000

Receiver side:

RF

DCLK

DIO

DIO

DCLK

RF


FSK modulating signal (NRZ),

internal in CC1000

Data provided by microcontroller

Transmitter side:


Demodulated signal (NRZ),

internal in CC1000

Data provided by CC1000

Receiver side:

RF

DCLK

DIO

DIO

DCLK

RF


FSK modulating signal (Manchester encoded),

internal in CC1000

Data provided by microcontroller (NRZ)

Transmitter side:


Demodulated signal (Manchester encoded),

internal in CC1000

Data provided by CC1000 (NRZ)

Receiver side:

RF

DCLK

DIO

DIO

DCLK

RF


FSK modulating signal (Manchester encoded),

internal in CC1000

Data provided by microcontroller (NRZ)

Transmitter side:


Demodulated signal (Manchester encoded),

internal in CC1000

Data provided by CC1000 (NRZ)

Receiver side:

RF

DCLK

DIO

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Figure 9. Transparent Asynchronous UART mode

Time

TX

data

1 0 1 1 0 0 0 1 1 0 1

Time

TX

data

1 0 1 1 0 0 0 1 1 0 1

Figure 10. Manchester encoding

DIO

DCLK

RF

DCLK is not used in transmit mode.

Used as data output in receive mode.

FSK modulating signal,

internal in CC1000

Data provided by UART (TXD)

Transmitter side:

DIO is not used in receive mode. Used only

as data input in transmit mode.

Demodulated signal,

internal in CC1000

Data output provided by CC1000.

Connect to UART (RXD).

Receiver side:

RF

DIO

DCLK

DIO

DCLK

RF

DCLK is not used in transmit mode.

Used as data output in receive mode.

FSK modulating signal,

internal in CC1000

Data provided by UART (TXD)

Transmitter side:

DIO is not used in receive mode. Used only

as data input in transmit mode.

Demodulated signal,

internal in CC1000

Data output provided by CC1000.

Connect to UART (RXD).

Receiver side:

RF

DIO

DCLK

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Bit synchroniser and data decision

Sampler

Average

filter

Datafilter

DecimatorFrequencydetector

Data slicercomparator

Figure 11. Demodulator block diagram

A block diagram of the digital demodulatoris shown in Figure 11. The IF signal issampled and its instantaneous frequencyis detected. The result is decimated andfiltered. In the data slicer the data filteroutput is compared to the average filteroutput to generate the data output.

The averaging filter is used to find theaverage value of the incoming data. While

the averaging filter is running andacquiring samples, it is important that thenumber of high and low bits received isequal (e.g. Manchester code or a balancedpreamble).

Therefore all modes, also synchronousNRZ mode, need a DC balanced preamblefor the internal data slicer to acquirecorrect comparison level from theaveraging filter. The suggested preambleis a 010101 bit pattern. The same bitpattern should also be used in Manchester

mode, giving a 011001100110chippattern. This is necessary for the bitsynchronizer to synchronize correctly.

The averaging filter must be locked beforeany NRZ data can be received. If theaveraging filter is locked(MODEM1.LOCK_AVG_MODE='1'), theacquired value will be kept also after

Power Down or Transmit mode. After amodem reset(MODEM1.MODEM_RESET_N), or a mainreset (using any of the standard resetsources), the averaging filter is reset.

In a polled receiver system the automaticlocking can be used. This is illustrated inFigure 12. If the receiver is operatedcontinuously and searching for a

preamble, the averaging filter should belocked manually as soon as the preambleis detected. This is shown in Figure 13. Ifthe data is Manchester coded there is noneed to lock the averaging filter(MODEM1.LOCK_AVG_IN='0'), as shownin Figure 14.

The minimum length of the preambledepends on the acquisition mode selectedand the settling time. Table 4 gives theminimum recommended number of chipsfor the preamble in NRZ and UART

modes. In this context chips refer to thedata coding. Using Manchester codingevery bit consists of two chips. ForManchester mode the minimumrecommended number of chips is shownin Table 5.

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Manual Lock Automatic LockSettling

MODEM1.SETTLING(1:0)

NRZ mode

MODEM1.LOCK_AVG_MODE='1'MODEM1.LOCK_

AVG_IN='0'=1**

UART mode


AVG_IN='0'=1**

NRZ mode


AVG_IN='X'***

UART mode


AVG_IN='X'***

00 14 11 16 16

01 25 22 32 32

10 46 43 64 64

11 89 86 128 128

Notes:** The averaging filter is locked when MODEM1.LOCK_AVG_INis set to 1

*** X = Do not care. The timer for the automatic lock is started when RX mode is set in the RFMAIN

registerAlso please note that in addition to the number of bits required to lock the filter, you need to add thenumber of bits needed for the preamble detector. See the next section for more information.

Table 4. Minimum preamble bits for locking the averaging filter, NRZ and UART mode

Settling

MODEM1.SETTLING(1:0)

Free-running

Manchester mode

MODEM1.LOCK_

AVG_MODE='1'MODEM1.LOCK_

AVG_IN='0'

00 23

01 34

10 55

11 98

Table 5. Minimum number preamble chips for averaging filter, Manchester mode

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Preamble NRZ data

Data package to be received

RX

Noise

RXPD

Averaging filter

free-running / not used

Automatically locked after a short period depending on SETTLING

Noise

Averaging filter locked

Preamble NRZ data


RX

Noise

RXPD

Averaging filter

free-running / not used

Automatically locked after a short period depending on SETTLING

Noise


Figure 12. Automatic locking of the averaging filter

Preamble NRZ data


RX

Noise

PD

Averaging filter free-running

Manually locked after preamble is detected

Noise


Preamble NRZ data


RX

Noise

PD

Averaging filter free-running

Manually locked after preamble is detected

Noise


Figure 13. Manual locking of the averaging filter

Preamble Manchester encoded data


RX

Noise

PD

Averaging filter always free-running

NoisePreamble Manchester encoded data


RX

Noise

PD

Averaging filter always free-running

Noise

Figure 14. Free-running averaging filter

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Receiver sensitivity versus data rate and frequency separation

The receiver sensitivity depends on thedata rate, the data format, FSK frequencyseparation and the RF frequency. Typicalfigures for the receiver sensitivity (BER =10

-3) are shown in Table 6 for 64 kHz

frequency separations and Table 7 for 20kHz separations. Optimised sensitivity

configurations are used. For bestperformance the frequency separationshould be as high as possible especially athigh data rates. Table 8 shows thesensitivity for low current settings. Seepage 28 for how to program differentcurrent consumption.

433 MHz 868 MHzData rate

[kBaud]

Separation

[kHz] NRZ

mode

Manchester

mode

UART

mode

NRZ

mode

Manchester

mode

UART

mode

0.6 64 -113 -114 -113 -110 -111 -110

1.2 64 -111 -112 -111 -108 -109 -108

2.4 64 -109 -110 -109 -106 -107 -106

4.8 64 -107 -108 -107 -104 -105 -1049.6 64 -105 -106 -105 -102 -103 -102

19.2 64 -103 -104 -103 -100 -101 -100

38.4 64 -102 -103 -102 -98 -99 -98

76.8 64 -100 -101 -100 -97 -98 -97

Average currentconsumption 9.3 mA 11.8 mA

Table 6. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3

,

frequency separation 64 kHz, normal current settings

433 MHz 868 MHzData rate

[kBaud]

Separation

[kHz] NRZ

mode

Manchester

mode

UART

mode

NRZ

mode

Manchester

mode

UART

mode

0.6 20 -109 -111 -109 -106 -108 -1061.2 20 -108 -110 -108 -104 -106 -104

2.4 20 -106 -108 -106 -103 -105 -103

4.8 20 -104 -106 -104 -101 -103 -101

9.6 20 -103 -104 -103 -100 -101 -100

19.2 20 -102 -103 -102 -99 -100 -99

38.4 20 -98 -100 -98 -98 -99 -98

76.8 20 -94 -98 -94 -94 -96 -94



,

frequency separation 20 kHz, normal current settings

433 MHz 868 MHzData rate[kBaud]

Separation[kHz] NRZ

modeManchester

modeUARTmode

NRZmode

Manchestermode

UARTmode

0.6 64 -111 -113 -111 -107 -109 -107

1.2 64 -110 -111 -110 -106 -107 -106

2.4 64 -108 -109 -108 -104 -105 -104

4.8 64 -106 -107 -106 -102 -103 -102

9.6 64 -104 -105 -104 -100 -101 -100

19.2 64 -102 -103 -102 -98 -99 -98

38.4 64 -101 -102 -101 -96 -97 -96

76.8 64 -99 -100 -99 -95 -96 -95



,

frequency separation 64 kHz , low current settings

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Frequency programming

RX mode:

fLO

(low-side) f LO

(high-side)fRF

(Receive frequency)

fIF

fIF

TX mode:

fRF

(Center frequency)

fsep

f0

(Lower FSK

frequency)

f1

(Upper FSK

frequency)

fvco

fvco

Figure 15. Relation between fvco, fif, and LO frequency

The frequency synthesiser (PLL) iscontrolled by the frequency word in theconfiguration registers. There are twofrequency words, A and B, which can be

programmed to two different frequencies.One of the frequency words can be usedfor RX (local oscillator frequency) and theother for TX (transmitting frequency, f0).This makes it possible to switch very fastbetween RX mode and TX mode. Theycan also be used for RX (or TX) on twodifferent channels. The MAIN.F_REGcontrol bit performs selection of frequencyword A or B.

The frequency word, FREQ, is 24 bits (3bytes) located in

FREQ_2A:FREQ_1A:FREQ_0A andFREQ_2B:FREQ_1B:FREQ_0B for the Aand Bword, respectively.

The frequency word FREQ can becalculated from:

16384

8192++=

TXDATAFSEPFREQff refVCO ,

where TXDATAis 0 or 1 in transmit modedepending on the data bit to be transmittedon DIO. In receive mode TXDATA is

always 0.

The reference frequency fref is the crystaloscillator clock divided by PLL.REFDIV, anumber between 2 and 14 that should bechosen such that:

1.0 MHz fref2.46 MHz

Thus, the reference frequency frefis:

REFDIV

ff xoscref =

fVCO is the Local Oscillator (LO) frequencyin receive mode, and the f0 frequency intransmit mode (lower FSK frequency). TheLO frequency must be fRF fIFor fRF+ fIFgiving low-side or high side LO injectionrespectively. Note that the data on DIO willbe inverted if high-side LO is used.

The upper FSK transmit frequency is givenby:

f1= f0+ fsep,

where the frequency separation fsep is setby the 11 bit separation word(FSEP1:FSEP0):

16384

FSEPff refsep =

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Clearing PLL.ALARM_DISABLE willenable generation of the frequency alarmbits PLL.ALARM_H and PLL.ALARM_L.

These bits indicate that the frequencysynthesis PLL is near the limit of generatethe frequency requested, and the PLLshould be recalibrated.

It is recommended that theLOCK_CONTINOUS bit in the LOCKregister is checked when changing

frequencies and when changing betweenRX and TX mode. If lock is not achieved, acalibration should be performed.

Recommended RX settings for ISM frequencies

Shown in Table 9 are the recommended RX frequency synthesiser settings for a fewoperating frequencies in the popular ISM bands. These settings ensure optimum configurationof the synthesiser in receive mode for best sensitivity. For some settings of the synthesiser(combinations of RF frequencies and reference frequency), the receiver sensitivity is

degraded. The FSK frequency separation is set to 64 kHz. The SmartRFStudio can be usedto generate optimised configuration data as well. Also an application note (AN011) and a

spreadsheet are available from Chipcon generating configuration data for any frequencygiving optimum sensitivity.

ISM

Frequency

[MHz]

Actual

frequency

[MHz]

Crystal

frequency

[MHz]

Low-side /

high- side

LO*

Reference

divider

REFDIV(decimal)

Frequency word

RX mode

FREQ(decimal)

Frequency word

RX mode

FREQ(hex)

315 315.037200 3.6864 High-side 3 4194304 400000

7.3728 6 4194304 400000

11.0592 9 4194304 400000

14.7456 12 4194304 400000

433.3 433.302000 3.6864 Low-side 3 5775168 580000

7.3728 6 5775168 580000

11.0592 9 5775168 580000

14.7456 12 5775168 580000433.9 433.916400 3.6864 Low-side 3 5775360 582000

7.3728 6 5775360 582000

11.0592 9 5775360 582000

14.7456 12 5775360 582000

434.5 434.530800 3.6864 Low-side 3 5783552 584000

7.3728 6 5783552 584000

11.0592 9 5783552 584000

14.7456 12 5783552 584000

868.3 868.297200 3.6864 Low-side 2 7708672 75A000

7.3728 4 7708672 75A000

11.0592 6 7708672 75A000

14.7456 8 7708672 75A000

868.95 868.918800 3.6864 High-side 2 7716864 75C000

7.3728 4 7716864 75C000

11.0592 6 7716864 75C00014.7456 7716864 75C000

869.525 869.526000 3.6864 Low-side 3 11583488 B0C000

7.3728 6 11583488 B0C000

11.0592 9 11583488 B0C000

14.7456 12 11583488 B0C000

869.85 869.840400 3.6864 High-side 2 7725056 75E000

7.3728 4 7725056 75E000

11.0592 6 7725056 75E000

14.7456 8 7725056 75E000

915 914.998800 3.6864 High-side 2 8126464 7C0000

7.3728 4 8126464 7C0000

11.0592 6 8126464 7C0000

14.7456 8 8126464 7C0000

*Note: When using high-side LO injection the data at DIO will be inverted.

Table 9. Recommended settings for ISM frequencies

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VCO

Only one external inductor (L101) is

required for the VCO. The inductor willdetermine the operating frequency rangeof the circuit. It is important to place theinductor as close to the pins as possible inorder to reduce stray inductance. It isrecommended to use a high Q, lowtolerance inductor for best performance.

Typical tuning range for the integrated

varactor is 20-25%.

Component values for various frequenciesare given in Table 1. Component valuesfor other frequencies can be found using

the SmartRFStudio software.

VCO and PLL self-calibration

To compensate for supply voltage,temperature and process variations the

VCO and PLL must be calibrated. Thecalibration is done automatically and setsmaximum VCO tuning range and optimumcharge pump current for PLL stability. Aftersetting up the device at the operatingfrequency, the self-calibration can beinitiated by setting the CAL_START bit.The calibration result is stored internally inthe chip, and is valid as long as power isnot turned off. If large supply voltagevariations (more than 0.5 V) ortemperature variations (more than 40degrees) occur after calibration, a new

calibration should be performed.

The self-calibration is controlled throughthe CAL register (see configurationregisters description p. 39). TheCAL_COMPLETE bit indicates completecalibration. The user can poll this bit, orsimply wait for 34 ms (calibration wait timewhen CAL_WAIT = 1). The wait time isproportional to the internal PLL referencefrequency. The lowest permitted referencefrequency (1 MHz) gives 34 ms wait time,which is therefore the worst case.

Referencefrequency [MHz]

Calibration time[ms]

2.4 14

2.0 17

1.5 23

1.0 34

The CAL_COMPLETE bit can also bemonitored at the CHP_OUT (LOCK) pin(configured by LOCK_SELECT[3:0]) andused as an interrupt input to themicrocontroller.

The CAL_START bit must be set to 0 bythe microcontroller after the calibration is

done.

There are separate calibration values forthe two frequency registers. If the twofrequencies, A and B, differ more than 1MHz, or different VCO currents are used(VCO_CURRENT[3:0] in the CURRENTregister) the calibration should be doneseparately. When using a 10.7 MHzexternal IF the LO is 10.7 MHzbelow/above the transmit frequency, henceseparate calibration must be done. TheCAL_DUALbit in the CALregister controls

dual or separate calibration.

The single calibration algorithm, usingseparate calibration for RX and TXfrequency, is illustrated in Figure 16.

In Figure 17 the dual calibration algorithmis shown for two RX frequencies. It couldalso be used for two TX frequencies, oreven for one RX and one TX frequency ifthe same VCO current is used.

In multi-channel and frequency hopping

applications the PLL calibration valuesmay be read and stored for later use. Byreading back calibration values andfrequency change can be done withoutdoing a re-calibration which could take upto 34 ms. The calibration value is stored inthe TEST0 and TEST2 registers after acalibration is completed. Note that whenusing single calibration, calibration valuesare stored separately for frequencyregisters A and B. This means that theTEST0 and TEST2 registers will containcalibration settings for the currently

selected frequency register (selected byF_REG in the MAIN register). The

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calibration value can later be written intoTEST5 and TEST 6 to bypass thecalibration. Note that you must set

VCO_OVERRIDE=1 in TEST5 andCHP_OVERRIDE=1 in the TEST6 register.

Write CAL:CAL_START=0

End of calibration

Wait for maximum 34 ms, or

Read CAL and wait until

CAL_COMPLETE=1

Start single calibration

RX frequency register A is calibrated firstWrite MAIN:

RXTX = 0; F_REG = 0

RX_PD = 0; TX_PD = 1; FS_PD = 0

CORE_PD = 0; BIAS_PD = 0; RESET_N=1

Write FREQ_A, FREQ_B

If DR>=9.6kBd then write TEST4: L2KIO=3Fh

Write CAL: CAL_DUAL = 0

Frequency register A is used for

RX mode, register B for TX

Write CAL:

CAL_START=1

Calibration is performed in RX mode,

Result is stored in TEST0 and TEST2,

RX register

Write CURRENT = RX current

Write PLL = RX pll

Update CURRENT and PLL for RX mode

Write CAL:

CAL_START=0

Wait for 34 ms, or


CAL_COMPLETE=1

TX frequency register B is calibrated second

Write MAIN:

RXTX = 1; F_REG = 1

RX_PD = 1; TX_PD = 0; FS_PD = 0



Calibration is performed in TX mode,


TX registers

Write CURRENT = TX current

Write PLL = TX pll

Write PA_POW = 00h

Update CURRENT and PLL for TX mode

PA is turned off to prevent spurious emission

Calibration time depend on the reference

frequency, see text.


End of calibration



CAL_COMPLETE=1

Start single calibration

RX frequency register A is calibrated firstWrite MAIN:

RXTX = 0; F_REG = 0

RX_PD = 0; TX_PD = 1; FS_PD = 0



If DR>=9.6kBd then write TEST4: L2KIO=3Fh


Frequency register A is used for


Write CAL:

CAL_START=1

Calibration is performed in RX mode,


RX register

Write CURRENT = RX current

Write PLL = RX pll


Write CAL:

CAL_START=0

Wait for 34 ms, or


CAL_COMPLETE=1

TX frequency register B is calibrated second

Write MAIN:

RXTX = 1; F_REG = 1

RX_PD = 1; TX_PD = 0; FS_PD = 0



Calibration is performed in TX mode,


TX registers

Write CURRENT = TX current

Write PLL = TX pll

Write PA_POW = 00h

Update CURRENT and PLL for TX mode

PA is turned off to prevent spurious emission



Figure 16. Single calibration algorithm for RX and TX

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Write CAL:

CAL_START=0

End of calibration



CAL_COMPLETE=1

Start dual calibration

Either frequency register A or B is selectedWrite MAIN:

RXTX = 0; F_REG = 0

RX_PD = 0; TX_PD = 1; FS_PD = 0



If DR>=38kBd then write TEST4: L2KIO=3Fh


Frequency registers A and B are both used

for RX mode

Write CAL:

CAL_START=1

Dual calibration is performed.


for both frequency A and B registers

Write CURRENT= RX current

Write PLL= RX pll




Write CAL:

CAL_START=0

End of calibration



CAL_COMPLETE=1

Start dual calibration

Either frequency register A or B is selectedWrite MAIN:

RXTX = 0; F_REG = 0

RX_PD = 0; TX_PD = 1; FS_PD = 0



If DR>=38kBd then write TEST4: L2KIO=3Fh


Frequency registers A and B are both used

for RX mode

Write CAL:

CAL_START=1

Dual calibration is performed.


for both frequency A and B registers

Write CURRENT= RX current

Write PLL= RX pll




Figure 17. Dual calibration algorithm for RX mode

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VCO and LNA current control

The VCO current is programmable and

should be set according to operatingfrequency RX/TX mode and output power.Recommended settings for theVCO_CURRENT bits in the CURRENTregister are shown in the tables on page41.

The bias current for the LNA, and the LO

and PA buffers are also programmable.Table 10 shows the current consumptionand receiver sensitivity for differentsettings (2.4 kBaud Manchester encodeddata).

CURRENT register FRONT_END registerRF freq-uency

[MHz]

Currentconsumption

[mA]

Sensitivity[dBm] VCO_

CURRENT[3:0]

LO_DRIVE

[1:0]

PA_DRIVE

[1:0]

BUF_CUR

RENT

LNA_CUR

RENT[1:0]

433 9.3 -110 0100 01 00 0 10

433 7.4 -109 0100 00 00 0 00

868 11.8 -107 1000 11 00 1 10868 9.6 -105 1000 10 00 0 00

Note: Current consumption and sensitivity are typical figures at 2.4 kBaud Manchester encoded data, BER 10-3

Table 10. Receiver sensitivity as function of current consumption

Power management

CC1000 offers great flexibility for powermanagement in order to meet strict powerconsumption requirements in batteryoperated applications. Power Down modeis controlled through the MAIN register.

There are separate bits to control the RXpart, the TX part, the frequencysynthesiser and the crystal oscillator (seepage 39). This individual control can beused to optimise for lowest possiblecurrent consumption in a certainapplication.

A typical power-on and initialisingsequence for minimum powerconsumption is shown in Figure 18 andFigure 19.

PALE should be tri-stated or set to a highlevel during power down mode in order toprevent a trickle current from flowing in theinternal pull-up resistor.

PA_POW should be set to 00h beforepower down mode to ensure lowestpossible leakage current.

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Figure 18. Initializing sequence

Power Down

Power Off

Power turned on

Initialise and reset CC1000

MAIN:

RXTX = 0

F_REG = 0

RX_PD = 1

TX_PD = 1

FS_PD = 1

CORE_PD = 0

BIAS_PD = 1

RESET_N = 0

Program all registers except MAINFrequency register A is used for


Calibrate VCO and PLLCalibration is performed according

to single calibration algorithm for both

RX and TX mode

MAIN: RESET_N = 1

Wait 2 ms*

Reset and turning on the

crystal oscillator core

*Time to wait depends on the crystal frequency

and the load capacitance

MAIN: RX_PD = 1, TX_PD = 1, FS_PD = 1,

CORE_PD = 1, BIAS_PD = 1PA_POW = 00h

Power Down

Power Off

Power turned on

Initialise and reset CC1000

MAIN:

RXTX = 0

F_REG = 0

RX_PD = 1

TX_PD = 1

FS_PD = 1

CORE_PD = 0

BIAS_PD = 1

RESET_N = 0

Program all registers except MAINFrequency register A is used for


Calibrate VCO and PLLCalibration is performed according

to single calibration algorithm for both

RX and TX mode

MAIN: RESET_N = 1

Wait 2 ms*

Reset and turning on the

crystal oscillator core

*Time to wait depends on the crystal frequency

and the load capacitance

MAIN: RX_PD = 1, TX_PD = 1, FS_PD = 1,

CORE_PD = 1, BIAS_PD = 1PA_POW = 00h

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Input / Output Matching

A few passive external components

combined with the internal T/R switchcircuitry ensures match in both RX and TXmode. The matching network is shown inFigure 20.

Component values for various frequencies

are given in Table 1. Component valuesfor other frequencies can be found usingthe configuration software.

Figure 20. Input/output matching network

RF_IN

RF_OUTTO ANTENNA

CC1000

L41C41

C42

AVDD=3V

L32

C31RF_IN

RF_OUTTO ANTENNA

CC1000

L41C41

C42

AVDD=3V

L32

C31RF_IN

RF_OUTTO ANTENNA

CC1000

L41C41

C42

AVDD=3V

L32

C31RF_IN

RF_OUTTO ANTENNA

CC1000

L41C41

C42

AVDD=3V

L32

C31

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RSSI output

CC1000 has a built-in RSSI (Received

Signal Strength Indicator) giving ananalogue output signal at the RSSI/IF pin.The IF_RSSI bits in the FRONT_ENDregister enable the RSSI. When the RSSIfunction is enabled, the output current ofthis pin is inversely proportional to theinput signal level. The output should beterminated in a resistor to convert thecurrent output into a voltage. A capacitor isused in order to low-pass filter the signal.

The RSSI voltage range from 0 1.2 V

when using a 27 k terminating resistor,

giving approximately 50 dB/V. This RSSIvoltage can be measured by an A/Dconverter. Note that a higher voltagemeans a lower input signal.

The RSSI measures the power referred to

the RF_IN pin. The input power can becalculated using the following equations:

P = -51.3 VRSSI 49.2 [dBm] at 433 MHzP = -50.0 VRSSI 45.5 [dBm] at 868 MHz

The external network for RSSI operation is

shown in Figure 21.R281 = 27 k, C281 =1nF.

A typical plot of RSSI voltage as functionof input power is shown in Figure 22.

Figure 21. RSSI circuit

00.10.20.30.40.50.60.70.8

0.91

1.11.21.3

-105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50

dBm

Voltage

433Mhz

868Mhz

Figure 22. RSSI voltage vs. input power

RSSI/IF

TO ADCCC1000

R281C281

RSSI/IF

TO ADCCC1000

R281C281

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IF output

CC1000 has a built-in 10.7 MHz IF output

buffer. This buffer could be applied innarrowband applications with requirementson mirror image filtering. The system is

then built with CC1000, a 10.7 MHz ceramicfilter and an external 10.7 MHzdemodulator. The external network for IFoutput operation is shown in Figure 23.

R281 = 470 , C281 = 3.3nF.

The external network provides 330

source impedance for the 10.7 MHzceramic filter.

RSSI/IF

CC1000

R281

C281

To 10.7MHz filter

and demodulator

RSSI/IF

CC1000

R281

C281

To 10.7MHz filter

and demodulator

Figure 23. IF output circuit

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Crystal oscillator

CC1000 has an advanced amplitude

regulated crystal oscillator. A high currentis used to start up the oscillations. Whenthe amplitude builds up, the current isreduced to what is necessary to maintain a600 mVpp amplitude. This ensures a faststart-up, keeps the current consumption aswell as the drive level to a minimum andmakes the oscillator insensitive to ESRvariations.

An external clock signal or the internalcrystal oscillator can be used as mainfrequency reference. An external clock

signal should be connected to XOSC_Q1,while XOSC_Q2 should be left open. TheXOSC_BYPASS bit in the FRONT_ENDregister should be set when an externalclock signal is used.

The crystal frequency should be in therange 3-4, 6-8 or 9-16 MHz. Because thecrystal frequency is used as reference forthe data rate (as well as other internalfunctions), the following frequencies arerecommended: 3.6864, 7.3728, 11.0592 or14.7456 MHz. These frequencies will give

accurate data rates. The crystal frequencyrange is selected by XOSC_FREQ1:0 inthe MODEM0register.

To operate in synchronous mode at datarates different from the standards at 1.2,2.4, 4.8 kBaud and so on, the crystalfrequency can be scaled. The data rate(DR) will change proportionally to the newcrystal frequency (f). To calculate the newcrystal frequency:

DR

DRff newxtalnewxtal =_

Using the internal crystal oscillator, thecrystal must be connected betweenXOSC_Q1 and XOSC_Q2. The oscillatoris designed for parallel mode operation ofthe crystal. In addition loading capacitors(C171 and C181) for the crystal arerequired. The loading capacitor valuesdepend on the total load capacitance, CL,specified for the crystal. The total loadcapacitance seen between the crystalterminals should equal CLfor the crystal tooscillate at the specified frequency.

parasiticL C

CC

C ++=

181171

11

1

The parasitic capacitance is constituted bypin input capacitance and PCB straycapacitance. Typically the total parasiticcapacitance is 8 pF. A trimming capacitormay be placed across C171 for initialtuning if necessary.

The crystal oscillator circuit is shown inFigure 24. Typical component values fordifferent values of CL are given in Table

12.

The initial tolerance, temperature drift,ageing and load pulling should be carefullyspecified in order to meet the requiredfrequency accuracy in a certainapplication. By specifying the totalexpected frequency accuracy in

SmartRF Studio together with data rateand frequency separation, the software willcalculate the total bandwidth and compareto the available IF bandwidth.

C171C181

XTAL

XOSC_Q1 XOSC_Q2

C171C181

XTALXTAL

XOSC_Q1 XOSC_Q2

Figure 24. Crystal oscillator circuit

Item CL= 12 pF CL= 16 pF CL= 22 pF

C171 6.8 pF 18 pF 33 pF

C181 6.8 pF 18 pF 33 pF

Table 12. Crystal oscillator component values

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Optional LC Filter

An optional LC filter may be addedbetween the antenna and the matchingnetwork in certain applications. The filterwill reduce the emission of harmonics andincrease the receiver selectivity.

The filter topology is shown in Figure 25.Component values are given in Table 13.

The filter is designed for 50 terminations. The component values mayhave to be tuned to compensate for layoutparasitics.

L71

C71 C72

L71

C71 C72

Figure 25. LC filter

Item 315 MHz 433 MHz 868 MHz 915 MHz

C71 30 pF 20 pF 10 pF 10 pF

C72 30 pF 20 pF 10 pF 10 pF

L71 15 nH 12 nH 5.6 nH 4.7 nH

Table 13. LC filter component values

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System Considerations and Guidelines

SRD regulations

International regulations and national lawsregulate the use of radio receivers andtransmitters. SRDs (Short Range Devices)for licence free operation are allowed tooperate in the 433 and 868-870 MHzbands in most European countries. In theUnited States such devices operate in the

260470 and 902-928 MHz bands. CC1000is designed to meet the requirements foroperation in all these bands. A summary ofthe most important aspects of theseregulations can be found in ApplicationNote AN001 SRD regulations for licence

free transceiver operation, available fromChipcons web site.

Low cost systemsIn systems where low cost is of great

importance the CC1000 is the ideal choice.Very few external components keep thetotal cost at a minimum. The oscillatorcrystal can then be a low cost crystal with50 ppm frequency tolerance.

Battery operated systemsIn low power applications the power down

mode should be used when not beingactive. Depending on the start-up timerequirement, the oscillator core can bepowered during power down. See page 28for information on how effective powermanagement can be implemented.

Crystal drift compensation

A unique feature in CC1000is the very finefrequency resolution of 250 Hz. This canbe used to do the temperaturecompensation of the crystal if thetemperature drift curve is known and a

temperature sensor is included in thesystem. Even initial adjustment can bedone using the frequency programmability.This eliminates the need for an expensive

TCXO and trimming in some applications.

In less demanding applications a crystalwith low temperature drift and low ageingcould be used without furthercompensation. A trimmer capacitor in thecrystal oscillator circuit (in parallel withC171) could be used to set the initialfrequency accurately. The fine frequencystep programming cannot be used in RXmode if optimised frequency settings arerequired (see page 24).

High reliability systemsUsing a SAW filter as a preselector will

improve the communication reliability inharsh environments by reducing theprobability of blocking. The receiversensitivity and the output power will bereduced due to the filter insertion loss. Byinserting the filter in the RX path only,together with an external RX/TX switch,only the receiver sensitivity is reduced, andoutput power is remained. The CHP_OUT(LOCK) pin can be configured to control anexternal LNA, RX/TX switch or poweramplifier. This is controlled byLOCK_SELECTin the LOCKregister.

Frequency hopping spread spectrum

systemsDue to the very fast frequency shift

properties of the PLL, the CC1000 is alsosuitable for frequency hopping systems.Hop rates of 1-100 hops/s are usually useddepending on the bit rate and the amountof data to be sent during eachtransmission. The two frequency registers(FREQ_A and FREQ_B) are designedsuch that the next frequency can beprogrammed while the present frequency

is used. The switching between the twofrequencies is done through the MAINregister.

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PCB Layout Recommendations

Chipcon provide reference layouts that

should be followed in order to achieve thebest performance. The CC1000PP Plug &Play reference design can be downloadedfrom the Chipcon website.

A two layer PCB is highly recommended.The bottom layer of the PCB should be theground-layer.

The top layer should be used for signalrouting, and the open areas should befilled with metallisation connected toground using several vias.

The ground pins should be connected toground as close as possible to thepackage pin using individual vias. The de-coupling capacitors should also be placedas close as possible to the supply pins andconnected to the ground plane by separatevias.

The external components should be assmall as possible and surface mount

devices are required. The VCO inductor

must be placed as close as possible to thechip and symmetrical with respect to theinput pins.

Precaution should be used when placingthe microcontroller in order to avoidinterference with the RF circuitry.

In certain applications where the groundplane for the digital circuitry is expected tobe noisy, the ground plane may be split inan analogue and a digital part. All AGNDpins and AVDD de-coupling capacitors

should be connected to the analogueground plane. All DGND pins and DVDDde-coupling capacitors should beconnected to the digital ground. Theconnection between the two ground planesshould be implemented as a starconnection with the power supply ground.

A development kit with a fully assembledPCB is available, and can be used as aguideline for layout.

Antenna ConsiderationsCC1000can be used together with varioustypes of antennas. The most commonantennas for short range communicationare monopole, helical and loop antennas.

Monopole antennas are resonant antennaswith a length corresponding to one quarter

of the electrical wavelength (/4). They arevery easy to design and can beimplemented simply as a piece of wire oreven integrated into the PCB.

Non-resonant monopole antennas shorter

than /4 can also be used, but at theexpense of range. In size and cost criticalapplications such an antenna may verywell be integrated into the PCB.

Helical antennas can be thought of as acombination of a monopole and a loopantenna. They are a good compromise insize critical applications. But helicalantennas tend to be more difficult tooptimise than the simple monopole.

Loop antennas are easy to integrate intothe PCB, but are less effective due to

difficult impedance matching because oftheir very low radiation resistance.

For low power applications the /4-monopole antenna is recommended givingthe best range and because of itssimplicity.

The length of the /4-monopole antenna isgiven by:

L = 7125 / f

where f is in MHz, giving the length in cm.An antenna for 869 MHz should be 8.2 cm,and 16.4 cm for 434 MHz.

The antenna should be connected asclose as possible to the IC. If the antennais located away from the input pin theantenna should be matched to the feeding

transmission line (50 ).

For a more thorough primer on antennas,please refer to Application Note AN003

SRD Antennas available from Chipconsweb site.

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Configuration registers

The configuration of CC1000 is done by

programming 22 8-bit configurationregisters. The configuration data based onselected system parameters are most

easily found by using the SmartRF

Studio software. A complete description of

the registers are given in the followingtables. After a RESET is programmed allthe registers have default values.

REGISTER OVERVIEW

ADDRESS Byte Name Description

00h MAIN MAIN Register

01h FREQ_2A Frequency Register 2A



04h FREQ_2B Frequency Register 2B

05h FREQ_1B Frequency Register 1B

06h FREQ_0B Frequency Register 0B07h FSEP1 Frequency Separation Register 1

08h FSEP0 Frequency Separation Register 0

09h CURRENT Current Consumption Control Register

0Ah FRONT_END Front End Control Register

0Bh PA_POW PA Output Power Control Register

0Ch PLL PLL Control Register

0Dh LOCK LOCK Status Register and signal select to CHP_OUT (LOCK) pin

0Eh CAL VCO Calibration Control and Status Register

0Fh MODEM2 Modem Control Register 2

10h MODEM1 Modem Control Register 1

11h MODEM0 Modem Control Register 0

12h MATCH Match Capacitor Array Control Register for RX and TX impedance matching

13h FSCTRL Frequency Synthesiser Control Register14h Reserved

15h Reserved

16h Reserved

17h Reserved

18h Reserved

19h Reserved

1Ah Reserved

1Bh Reserved

1Ch PRESCALER Prescaler and IF-strip test control register

40h TEST6 Test register for PLL LOOP

41h TEST5 Test register for PLL LOOP

42h TEST4 Test register for PLL LOOP (must be updated as specified)

43h TEST3 Test register for VCO

44h TEST2 Test register for Calibration45h TEST1 Test register for Calibration

46h TEST0 Test register for Calibration

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MAIN Register (00h)

REGISTER NAME Defaultvalue

Active Description

MAIN[7] RXTX - - RX/TX switch, 0 : RX , 1 : TXMAIN[6] F_REG - - Selection of Frequency Register, 0 : Register A, 1 :Register B

MAIN[5] RX_PD - H Power Down of LNA, Mixer, IF, Demodulator, RX part ofSignal Interface

MAIN[4] TX_PD - H Power Down of TX part of Signal Interface, PA

MAIN[3] FS_PD - H Power Down of Frequency Synthesiser

MAIN[2] CORE_PD - H Power Down of Crystal Oscillator Core

MAIN[1] BIAS_PD - H Power Down of BIAS (Global_Current_Generator)and Crystal Oscillator Buffer

MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write defaultvalues to all other registers than MAIN. Bits in MAIN donot have a default value, and will be written directlythrough the configurations interface. Must be set high to

complete reset.

FREQ_2A Register (01h)


Active Description

FREQ_2A[7:0] FREQ_A[23:16] 01110101 - 8 MSB of frequency control word A



Active Description

FREQ_1A[7:0] FREQ_A[15:8] 10100000 - Bit 15 to 8 of frequency control word A



Active Description

FREQ_0A[7:0] FREQ_A[7:0] 11001011 - 8 LSB of frequency control word A

FREQ_2B Register (04h)


Active Description

FREQ_2B[7:0] FREQ_B[23:16] 01110101 - 8 MSB of frequency control word B



Active Description

FREQ_1B[7:0] FREQ_B[15:8] 10100101 - Bit 15 to 8 of frequency control word B



Active Description

FREQ_0B[7:0] FREQ_B[7:0] 01001110 - 8 LSB of frequency control word B

FSEP1 Register (07h)


Active Description

FSEP1[7:3] - - - Not used

FSEP1[2:0] FSEP_MSB[2:0] 000 - 3 MSB of frequency separation control

FSEP0 Register (08h)

REGISTER NAME Default

value

Active Description

FSEP0[7:0] FSEP_LSB[7:0] 01011001 - 8 LSB of frequency separation control

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CURRENT Register (09h)


Active Description

CURRENT[7:4] VCO_CURRENT[3:0] 1100 - Control of current in VCO core for TX and RX0000 : 150A0001 : 250A0010 : 350A0011 : 450A0100 : 950A, use for RX, f= 400 - 500 MHz0101 : 1050A0110 : 1150A0111 : 1250A1000 : 1450A, use for RX, f500MHz; and TX, f= 400 - 500 MHz

1001 : 1550A, use for TX, f500 MHz

CURRENT[3:2] LO_DRIVE[1:0] 10 Control of current in VCO buffer for LO drive00 : 0.5mA, use for TX01 : 1.0mA , use for RX, f500 MHz *

* LO_DRIVE can be reduced to save current in

RX mode. See Table 10for detailsCURRENT[1:0] PA_DRIVE[1:0] 10 Control of current in VCO buffer for PA

00 : 1mA, use for RX01 : 2mA, use for TX, f500 MHz

FRONT_END Register (0Ah)


Active Description

FRONT_END[7:6] - 00 - Not used

FRONT_END[5] BUF_CURRENT 0 - Control of current in the LNA_FOLLOWER0 : 520uA, use for f500 MHz *

*BUF_CURRENT can be reduced to save

current in RX mode. See Table 10for details.FRONT_END[4:3] LNA_CURRENT

[1:0]01 - Control of current in LNA

00 : 0.8mA, use for f500 MHz *11 : 2.2mA

*LNA_CURRENT can be reduced to save

current in RX mode. See Table 10for details.FRONT_END[2:1] IF_RSSI[1:0] 00 - Control of IF_RSSI pin

00 : Internal IF and demodulator, RSSI inactive01 : RSSI active, RSSI/IF is analog RSSI output10 : External IF and demodulator, RSSI/IF ismixer output. Internal IF in power down mode.11 : Not used

FRONT_END[0] XOSC_BYPASS 0 - 0 : Internal XOSC enabled1 : Power-Down of XOSC, external CLK used

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PA_POW Register (0Bh)


Active Description

PA_POW[7:4] PA_HIGHPOWER[3:0] 0000 - Control of output power in high power array.Should be 0000 in PD mode . See Table 11page 32 for details.

PA_POW[3:0] PA_LOWPOWER[3:0] 1111 - Control of output power in low power arrayShould be 0000 in PD mode. See Table 11page 32 for details.

PLL Register (0Ch)


Active Description

PLL[7] EXT_FILTER 0 - 1 : External loop filter0 : Internal loop filter

1-to-0 transition samples F_COMP

comparator when BREAK_LOOP=1(TEST3)

PLL[6:3] REFDIV[3:0] 0010 - Reference divider

0000 : Not allowed0001 : Not allowed0010 : Divide by 20011 : Divide by 3...........

1111 : Divide by 15

PLL[2] ALARM_DISABLE 0 h 0 : Alarm function enabled1 : Alarm function disabled

PLL[1] ALARM_H - - Status bit for tuning voltage out of range

(too close to VDD)PLL[0] ALARM_L - - Status bit for tuning voltage out of range(too close to GND)

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LOCK Register (0Dh)

REGISTER

NAME Defaultvalue

Active Description

LOCK[7:4] LOCK_SELECT[3:0] 0000 - Selection of signals to CHP_OUT (LOCK) pin

0000 : Normal, pin can be used as CHP_OUT0001 : LOCK_CONTINUOUS (active high)0010 : LOCK_INSTANT (active high)0011 : ALARM_H (active high)0100 : ALARM_L (active high)0101 : CAL_COMPLETE (active high)0110 : IF_OUT0111 : REFERENCE_DIVIDER Output1000 : TX_PDB (active high, activates externalPA when TX_PD=0)1001 : Manchester Violation (active high)1010 : RX_PDB (active high, activates externalLNA when RX_PD=0)

1011 : Not defined1100 : Not defined1101 : LOCK_AVG_FILTER1110 : N_DIVIDER Output1111 : F_COMP

LOCK[3] PLL_LOCK_ACCURACY

0 - 0 : Sets Lock Threshold = 127, Reset LockThreshold = 111. Corresponds to a worst caseaccuracy of 0.7%1 : Sets Lock Threshold = 31, Reset LockThreshold =15. Corresponds to a worst caseaccuracy of 2.8%

LOCK[2] PLL_LOCK_LENGTH

0 - 0 : Normal PLL lock window1 : Not used

LOCK[1] LOCK_INSTANT - - Status bit from Lock DetectorLOCK[0] LOCK_CONTINUOUS - - Status bit from Lock Detector

CAL Register (0Eh)


Active Description

CAL[7] CAL_START 0 1 : Calibration started0 : Calibration inactiveCAL_START must be set to 0 aftercalibration is done

CAL[6] CAL_DUAL 0 H 1 : Store calibration in both A and B0 : Store calibration in A or B defined byMAIN[6]

CAL[5] CAL_WAIT 0 H 1 : Normal Calibration Wait Time0 : Half Calibration Wait Time

The calibration time is proportional to theinternal reference frequency. 2 MHzreference frequency gives 14 ms wait time.

CAL[4] CAL_CURRENT 0 H 1 : Calibration Current Doubled0 : Normal Calibration Current

CAL[3] CAL_COMPLETE 0 H Status bit defining that calibration iscomplete

CAL[2:0] CAL_ITERATE 101 H Iteration start value for calibration DAC000 - 101: Not used110 : Normal start value111 : Not used

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MODEM2 Register (0Fh)

REGISTER NAME Def

Documents

CC1000 Data Sheet 2 2