Capacitor Selection for DC/DC Convertors: From Basic Application to Advanced Topics TI – Silicon Valley Analog in Santa Clara California USA - This course

Capacitor Selection for DC/DC Convertors:

From Basic Application to Advanced Topics

TI – Silicon Valley Analog in Santa Clara California USA -

This course written by: Simple Switcher Applications Team Members:• Alan Martin

• Marc Davis-Marsh

• Giuseppe Pinto

• Ismail Jorio

Additional material provided by Chuck Tinsley of capacitor manufacturer KEMET

1

Table of Contents

2

Capacitors types for DC/DC Conversion

CeramicElectrolytic Tantalum Polymer

Advanced Applications in DC/DC Converters

Typical Characteristics

Advantages and Disadvantages

Failure ModesSelection Process

Buck Boost

Measurement of capacitor parasitics

Simple method to reduce high

frequency noise in SMPS

Estimating output voltage ripple and transient

response

RMS current ratings by topology

2

Capacitor Types

3

Capacitor Chemistry - Value and Voltage rating

4

100uF -10000uF

0.1uF-100uF

1pF – 0.1uF

Cap

acita

nce

Voltage

2V 4V 16V 25V 50V 100V

COG

X5RX5R/X7R

Tantalum

Polymer

Electrolytic

Aluminum Electrolytics - Overview • Least Expensive Capacitors for Bulk Capacitance

– Multiple vendors– Small size, surface mountable

• How is it made?– Etched foil with liquid Electrolyte– Placed in a can with a seal/vent

• Highest ESR

• Low Frequency Cap roll off due to higher ESR

• Wear Out Mechanism – Limited lifetime– Liquid electrolyte – with a vent– Cap changes over time with Voltage and Temp– ESR changes over time

• Mounting– High shock and vibration can cause failure

5

Aluminum Electrolytics - Packaging• Through hole versions, usually in a round can.

– Large ones have screw terminals or solder lugs– Radial or axial leads– Non SMT may have higher inductance because of long leads

• Surface mountable versions, are modified from radial leaded versions.– SMT versions usually have the capacitor value visibly printed on can.– SMT versions may use letter codes instead of numeric rating.

- +- +

6

Aluminum Electrolytics - Advantages

• Low Cost – Mature technology with low cost materials

• Long History– (Industry started in the 1930’s )

• Many Manufacturers to choose from.

• High capacitance values available.

• Only choice for SMPS that need high voltage and high capacitance.

7

Aluminum Electrolytics - Disadvantages• Large swings in ESR vs temperature

– Cold temps have 4-8x higher ESR than at room temperature

8

Aluminum Electrolytics - Disadvantages• Large Parasitics

– High ESR (Effective Series Resistance)– High ESL – (Effective Series Inductance).

• Electrolytic capacitors eventually degrade over the life of the product.– The electrolyte eventually dries out. – Long term storage may cause Aluminum oxide barrier layer to de-form.

• Capacitance drops• ESR increases.

– Higher ESR causes more internal heat causing it to dry out even faster. – This effect is worse at high temperatures.

– (Lesson: Don’t use “old stock” aluminum capacitors in your product.)

• Needs a ceramic in parallel for switch mode applications.– High esr and esl can cause SMPS malfunction.

• Have measurable dc leakage current.– Probably not an issue in power circuits;

• Leakage current can be a problem in timing circuits.

9

Aluminum Electrolytic - Venting failure

450V rated capacitors after accidental application of 600V

10

• Fails open or shorted.

• Catastrophic explosive venting – From Over-Voltage of the capacitor. – From exceeding the Ripple Current Rating of a capacitor

• May have the same effect as overvoltage; but it takes longer for the capacitor to overheat and vent.

Ceramics - Overview• Lowest Cost devices

– Primarily for decoupling and bypass applications– Multiple vendors, sizes– Surface mountable

• How is it made?– Alternating layers of electrodes and ceramic dielectric materials

• Significant effects for Class 2 Dielectrics i.e. X5R, X7R.– Voltage bias effect– Temperature effects– Ageing

• 2%/decade hour for X7R, • 5%/decade hour for X5R• Starts decay after soldering

– High Q • Frequency selective

11

Ceramic Dielectric – 3 Character Codes

• Class 1: (Best Performance)– Temperature Coefficient

Decoder

12

• Class 2: (Higher Capacitance)– Temperature and Capacitance

Tolerance Decoder

• Typical Values:– X5R,X7R, values up to 150uF

• Typical Values:– NP0,C0G, values up to 100,000pF

Ceramic Capacitors - Advantages

• Low Cost – Mature technology with low cost materials

• Many Manufacturers to choose from.

• Reliable and rugged– Extremely tolerant of over voltage surges

• Best Choice for local bypassing

• Not Polarized

• Lowest effective series resistance (Low ESR) – several milliohms– Leads to high RMS current rating

• Low effective series inductance (Low ESL)– < 3nH

13

Ceramic Capacitors - Disadvantages

• Capacitance limited to around 150 uF / 6.3V

• Large body sizes prone to cracking with PCB flexing. Several small units in parallel may be a better choice.

• Have both a voltage and temperature coefficient that reduces capacitance value.

• Some large package size units exhibit piezo-electric audible “singing”. – Difficult to control. (Ceramic speaker effect.)– More noticeable with Class 2 dielectrics

• Incomplete data sheets!! – ESR, ESL, SRF and Ripple Current rating often missing from data sheets – Contact the manufacturer for ripple current

• Capacitance value not printed on SMT device package. – Impossible to visually inspect for value once mounted on the PCB.

• Some power supply circuits are not stable with ceramic output capacitors.– Usually LDO’s and parts using COT control

14

Ceramics - Cracking• Flex cracking – Number 1 Failure Mode!

– Cracks formed after mounting to PCB• Mechanically stressed after assembly• Larger parts, generate cracks more easily• Usually Fails shorted

• Voltage de-rating– Not required for COG, X7R and X5R…but…

• Voltage bias or capacitance loss increases as you approach rated voltage on X5R/X7R devices

15

Voltage Bias Effect on X5R - example• X5R, 10uF, 6.3 volt Ceramic capacitor at 0, 3.15 and 6.3 volt bias

– 10uF becomes 2.9uF under 6.3V bias condition• Doesn’t include, temperature, ageing and initial tolerance!!!!!!!!!

16

10uF

2.9uF

0V Bias

6.3V Bias

3.15V Bias

Voltage Bias Effect Including Case Size

17

1uF 0603

1uF 1206

1uF 0805

X5R, 16V Rated Capacitors

Capacitance decreases more quickly with smaller Case sizes

Ceramic capacitance change due to temperature

AVX Capacitor X5R dielectric - typical of any brand

You lose another 10% over temperature

18

Y5V dielectric characteristics

DO NOT USE! Y5V and Z5U ceramic dielectrics for power supply designs

19

Tantalum – Overview (MnO2 based)• High Capacitance per unit Volume Technology

– Small package sizes available • Thin devices are available

• How is it made?– Tantalum Anode pressed around a tantalum wire– Oxide grown on surface– Cathode formed by dipping and heat conversion MnMnO– Epoxy encapsulated

• Old technology– Requires 50% Voltage derating

• PPM failure rates increase exponentially above 50% voltage derating– Can fail explosively– High ESR compared to Polymer types– Fairly low cap roll off vs. frequency

Tantalum Model

20

2

Solid Tantalum Capacitors - Packaging

Usually rectangular Surface Mount Technology – SMT machine mountable

Capacitance ratings for 1uF to 1000uF

21

+

-

+

-

- +

Solid Tantalum Capacitors - Advantages

• Lots of capacitance in a small package.– 1uF to 1000uF max

• Medium-high effective series resistance (Low ESR) – 10 to 500 milliohms– Medium level of RMS current

• Low effective series inductance (Low ESL)– < 3nH

• Numerous manufacturers

• Good datasheet vs. electrolytic

22

Solid Tantalum Capacitors - Disadvantages

• Limited voltage range 50V rating max. – Therefore for circuit voltages less than 25 or 35VDC.

• Fairly high in cost– Historically Tantalum has had supply shortages

• Limited inrush surge current capability. – Do not use tantalum for hot pluggable input capacitors!

23

Don’t Hot plug tantalum!

Solid Tantalum Capacitors – Application Safety

• ALWAYS observe voltage polarity

• DO NOT exceed voltage rating.

• DO NOT exceed inrush surge rating

• Can fail catastrophically if misapplied.

• Can fail open or short

24

Polymer - Overview• Highest Capacitance per unit Volume Technology

– Small package sizes available

• How is it made?– Tantalum Anode pressed around a tantalum wire– Oxide grown on surface– Cathode formed by dipping into Monomer and cured at room temperature– Epoxy encapsulated

• Lower ESR vs MnO2 based Tantalums– Higher frequency operation – over a Mhz…still looks like a cap!– Lower power dissipation

• Higher ripple current capability• May need less capacitance

25

Polymer & Organic Capacitors - Packaging

• SMT Block style similar to tantalum.

• Round / Radial versions in SMT and through-hole.

• Types– Tantalum polymer / Aluminum polymer / Organic semiconductor

26

-

+

-

+

- +

OSCON

PosCap

Kemet Tantalum Polymer

Polymer & Organic Capacitors - Advantages

• Low ESR – but not as low as equivalent ceramic.

• Low ESL– depending on construction method

• New technology – Designed for SMPS.

• Can be very low profile.

• High capacitance per unit volume.– Much better performance than aluminum electrolytic and much smaller in

size.

• No voltage coefficient.

• Viable alternative to solid tantalum.

27

Polymer - Continued• Voltage de-rating is 10/20% depending on rated voltage

– PPM failure rates significantly reduced

• Can withstand higher transient voltages

28

Polymer & Organic Capacitors - Disadvantages

• High cost

• Voltage surges capability depends on chemistry.– Oscon very intolerant of voltage surges

• Tend to be from a single supplier. – May have availability issues.

Polymer & Organic Capacitors – Failure Mode

• Tantalum Polymer

• Less prone to catastrophic failure than solid tantalum but will still vent and emit smoke.

• Organic (OSCON)

• Emits noxious smoke.

29

Capacitor Chemistry - Quick Comparison

Numerical Rankings from 1 (Best) to 5 (Worst)

30

Capacitor Chemistry – General Parameters

31

DC/DC Converter Topologies

32

Capacitor Selection for DC/DC converters

Design factors that are known before selecting capacitors :

33

• Switching frequency Fsw : From 50KHz (High power) to 6MHz (Low power)• Input voltage range Vin • Output voltage Vout• Switch duty factor Duty Cycle (D) ~ Vout/Vin (for Buck/Step Down)• Output current Iout• Inductance L is usually designed such that the ripple current is

~30 - 40% of Iout at the switching frequency• Topology Chosen in architectural stage

Capacitor Selection for DC/DC converters

RMS current of a capacitor is one of the most important specifications for capacitor reliability

34

It also effects the converters performance, and varies by topology

• Self-Heating Proportional to RMS Current and Internal Losses

• Voltage Ripple Higher RMS Current leads to larger voltage ripple

Let’s calculate RMS current for different topologies

35-

+

Common Topologies - BUCK

Buck Converter

Boost Converter

Buck-Boost Converter

Critical path

Switching Current exist in the input side

36

-+

Common Topologies - BUCK

Buck Converter

Boost Converter


Input Capacitor RMS Current

Output Capacitor RMS Current

37

-+

Common Topologies - BOOST

Buck Converter

Boost Converter


Critical path

38

-+

Common Topologies - BOOST

Buck Converter

Boost Converter


Input Capacitor RMS Current

Output Capacitor RMS Current

39

-+

Common Topologies – BUCK BOOST

Buck Converter

Boost Converter


-+

Critical path

Non-Inverting

Inverting

40

-+

Common Topologies – BUCK BOOST

Buck Converter

Boost Converter


-+

-+

Input Cap RMS Current

Output Cap RMS Current

Mode 1 (Buck) Mode 2 (Boost)

Non-Inverting

Input Cap RMS Current

Output Cap RMS Current

Additional Topologies

41SLUW001A

Capacitor Parasitics

42

Ideal capacitor compared to actual capacitor

You buy this You get this

22uF 4V X5R 0603 Ceramic

Voltage and Temperature De-rated Capacitance

(ESL)

Effective Series Inductance

- Parasitic inductance term -

(ESR)

Effective Series Resistance

- Parasitic resistance term -

Buy one part – Get three for the price of one!

43

Know your parasitics! They are very important!

• Equipment to use to measure capacitor parasitic elements.

• RLC Analyzer– Some can apply DC bias

• RF Network Analyzer – DC bias can easily damage analyzer source and receiver inputs– AC performance measurement very accurate.– Agilent (aka Hewlett Packard) i.e. HP3755A goes to 200MHz – Many other brands

• Frequency Response Analyzer– Allows DC bias so voltage coefficient can be measured. RLC results are less

accurate. Frequency range is lower than network analyzer – 30 MHz max; Usually just 1 or 2 MHz range. May allow plotting on reactance paper

with line of constant capacitance and constant inductance. FRA is also used for loop stability analysis.

– Brands – Venable Industries – Ridley (A/P) several others.

Measure the parasitic terms and include them in the design

44

Comparison of capacitor types using Frequency Response Analyzer- Shown in reactance coordinate system -

5 different types of 22uF capacitor

45

Comparative performance of different capacitor types using RF Network Analyzer

1.0 Ohm

0.1 Ohm

0.01 Ohm

0.316 Ohm

0.0316 Ohm

0 deg

45 Deg

-45 deg

-90 deg

90 deg

Aluminum Electrolytic

Cer

amic

Lead

ed O

S-C

ON

Tant

alum

Pos

-Cap

Same Five 22uF

Capacitors

46

Reducing Ripple and Transient Response

47

Output Caps Selection

The output capacitor must be designed to fulfill mainly two requirements:

1. To keep the steady-state peak-to-peak output voltage ripple below the

maximum allowed value ∆Vopp

2. To keep the output voltage waveform within the required regulation

window [Vo ± ∆Vo_reg] during the overshoot and undershoot caused by

output current transients

The output capacitor design of a buck converter will be discussed in this presentation

48

48

Output Caps Selection – output ripple• Boundary conditions formulated separately for ESR and C of the output capacitor may lead to

selection of oversized commercial components. Please note that there is a phase shift

between the contribute of C and the contribute of ESR.

• In this presentation an approach based on Acceptability Boundary Curves which jointly

considers the effect of ESR and C will be shown.

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49

Output Caps Selection – stray inductances in output ripple analysis

50

50

• Depending on the constant ESR x C, the output

voltage waveform can change from quasi-triangular

to quasi-sinusoidal.

• The effect of stray inductances can be easily

separated from the effect of the principal parameters

ESR and C of the capacitor. In fact, stray

inductances produce additive step-up and step-

down effects on the output voltage, whose

amplitude is given by:

Dominant ESR

NO ESL

Dominant C

Includes ESL

Ceramic Bad layout

ElectrolyticTantalum

Output Voltage Ripple by Chemistry

51

51

Inductor Current

Ceramic

Tantalum Polymer

OSCON

Electrolytic

This plot shows a comparison of the output voltage ripple of a buck converter using 4 different capacitor chemistries. All caps = 47uF. Scale = 20mV/div

Output Caps Selection – stray inductances in output ripple analysis

• In order to take in account the effect determined by the equivalent series inductance (ESL) of

the output capacitor and by the inductance of the printed circuit board trace LPCB it is sufficient

to replace the maximum allowed peak-to-peak output ripple voltage amplitude ΔVOpp with the net

effective peak-to-peak ripple voltage ΔVOppeff allowed to ESR and capacitance C, given by:

• If ESL and LPCB are unknown, the previous formula can also be used to determine the maximum

allowed ESL compatible with the ESR and capacitance C of a capacitor selected with the

algorithm not including the LPCB :

52

52

Output Caps Selection – output ripple analysis

• The remaining part of the peak to peak output ripple voltage can be determined by analyzing the

circuit in the time intervals between switching instants and can be derived by integrating the current

flowing into the output capacitor:

53

53

Where:

ON TIME

OFF TIME

ESR contributeInitial voltage charge

capacitance contribute

• Current flowing into the output capacitor is given by :

ON TIME

OFF TIME

Output Caps Selection – output ripple analysis• In order to determine analytical expression of output voltage ripple,

maximum and minimum values of output voltage waveform must be

computed.

• Instant when minimum occurs is given by:

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• Instant when maximum occurs is given by:vO(tmin)

vO(tmax)

The analytical output ripple is given by:

∆VOpp = vO(tmax) - vO(tmin)

DOMINANT ESR case


• Two different Domain Boundary Curves (DBC) can be defined as for D < 0.5 and D > 0.5

• Three different Acceptability Boundary Curves (ABC) can be defined for HIGH, MID and LOW ESR case

55

55

For D < 0.5 :

ESR ≥ Rs- HIGH ESR

Ri- < ESR < Rs- MID ESR

ESR ≤ Ri- LOW ESR

Please note that boundaries

are duty cycle and switching

frequency dependent

+ESR > Rs+

ESR < Ri+

Rs+< ESR < Ri+

HIGH ESR

HIGH ESR

MID ESR

MID ESR

LOW ESR

LOW ESR


• The following figure shows Domain Boundary Curves (DBC) and the Acceptability Boundary Curves (ABC) in ESR-C plane for D = 33% , ∆iLpp = 0.8A, ∆Vopp_eff = 55mV, fS = 500kHz. In applications where D > 0.5 the DBC are inverted.

• ABCs allow to quickly figure out real feasible capacitors representing possible design solutions when load transient constraints are not needed. A real capacitor whose values of ESR and C correspond to a point located below ABCs (green area) is suitable to meet ripple constraints requirements.

56

56

HIGH ESR

MID ESRLOW ESR

HIGH ESRMID ESRLOW ESR

Output Caps Selection – output ripple analysis – simplified formula

57

57

• A simplified equation can be derived by calculating the fundamental component of the output ripple voltage as:

• There is an overestimation of the needed output cap nearby the MID ESR area

Output Caps Selection – load transient

58

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• The overshoot (or undershoot) occurs because of the surplus (or deficit) of charge in the output capacitor.

• Let’s define the allowed variation for the output voltage as ∆Voreg

• Because of slope constraints due to the inductor: when D < 0.5 the overshoot is greater than the undershoot and vice versa when D > 0.5

OVERSHOOT

UNDERSHOOT

Output Caps Selection – load transient analysis

59

59

• The instant when the peak of the overshoot occurs depends on the type of the output capacitor.

• The exact point where peak overshoot is reached, and its magnitude, must be calculated by taking into account joined influence of C and ESR.

Output Caps Selection – load transient

60

60

• Three different cases can be considered when load transient occurs:

1. stepwise load transient: load transient duration TLT is much smaller than closed loop system’s response time

given by the crossover frequency fC, TLT << 1/(4fC)

2. fast load transient: load transient duration TLT is smaller than closed loop system’s response time TLT < 1/(4fC)

3. slow load transient: load transient duration TLT is larger that closed loop system’s response time TLT > 1/(4fC)

• In 1st and 2nd case the control network is not able to compensate output voltage variations suddenly

after a load variation. Hence, the output filter must be designed to keep the output voltage within the

maximum allowed range in early time after the load transient until the loop has the chance to respond.

The impact of load transient constraint on the output

capacitor size is lower in 3rd case. For this reason worst

case stepwise load transient is treated. The output

current slew rate will be considered as infinite (TLT = 0).

This is a reasonable assumption in application such

FPGA supplies where load-current slew rate may range

up to 100A/µs.

Output Caps Selection – load transient analysis

61

61

• Is it possible to analyze a buck converter during load transient by means of the following circuit.

• tLT is the instant when the load transient occurs, it can occur during ON time or during OFF time.

• Worst case condition occurs when:

• tLT = DTS for overshoot

• tLT = TS for undershoot

ON TIME OFF TIME

Let’s assume a high cross over frequency controller. Minimum duty cycle is assumed to be 0 and maximum duty cycle is assumed to be 1.

Output Caps Selection – load transient analysis – overshoot

62

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• Assuming that the step down load transient occurs at tLT = DT (overshoot worst case), the

instant of peak variation of the output voltage and its maximum overshoot peak value are

given by:

• It tOS = DTS the magnitude of VOS is determined by ESR only (high ESR case ESRH)

• If tOS > DTS the magnitude of VOS jointly depends on C and ESR values (low ESR case ESRL)

CB


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• The three curves cross at the boundary value of capacitance CB given by:

• A real capacitor whose values of ESR and C correspond to a point located

below this curve (green area) can be considered suitable to maintain the output

voltage within the given regulation window in presence of a charging load

transient.

Zero slope

Negative slope

Positive slope


64

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• It makes sense to consider the effect of stray inductances LESL = ESL + LPCB only it the real

slew-rate SR of the load current transition is known.

• After the instant tr, the output voltage evolves in the time as if there was no ESL.

• Load transient constraints are met if C, ESR and ESL are such that both conditions are

fulfilled:

• The effect of LESL can be accounted by

including the following constraints for the ESR

∆VO(tr) < ∆VOreg

∆VO(tos) < ∆VOreg

∆VOreg


65

65

• LESL = 10nH

• SR = 3 A/µs

∆VOreg

Output Caps Selection – load transient analysis – overshoot – simplified equation

66

66

• It is possible to derive simplified boundaries for C and ESR.

• Let’s assume that the minimum output capacitance required is CB previously defined as:

• It is possible to calculate the maximum allowed value of the ESR by replacing CB value into the ESRcrit formula

previously defined:

• Any capacitor whose value of capacitance and ESR is higher than Cmin and lower the ESRmax is suitable to meet

load transient requirements for a buck converter.

Capacitor - Selection Process Summary

Electrical specifications:

• Electrical performance – RMS Current in the capacitor

• Look for RMS current equation in the chosen DC/DC topology – Applied voltage at the capacitor

• De-rate the capacitor based on the chemistry

• Transient requirements – Size bulk capacitance based upon voltage deviation requirements– Check that the selected capacitor meets stability requirements

• Capacitor impedance – Does this capacitor chemistry look inductive at the frequency of interest?

67

Capacitor - Selection Process Summary• Most designs use a combinations of technologies

– Tantalums or Aluminum Electrolytics for bulk Capacitance– Ceramics for decoupling and bypass

• Depends on Mechanical Challenges– Vibration– Temperature– Cooling

• Lifetime comes into play– For longer life, improve the quality of the components– Ceramics and polymer have improved lifetime over electrolytic and tantalum

• Costs - Tradeoffs– Component cost vs Total cost of ownership

68

Capacitors – Selection Process Summary• Use Equations for selected topology

– Calculate RMS Currents, Peak voltages, Minimum capacitance, Maximum esr

• Select Chemistry based upon the designs needs– Remember to de-rate voltage by at least 20% for all chemistries– 50% for tantalum to improve reliability– 50% for class 2 ceramics to decrease capacitance lost to DC biasing– Note: Capacitor data sheet MUST include 100kHz data if the capacitor is to

be applied in a switch mode power supply (SMPS). 120 Hz only versions are not suitable for SMPS

– Consider NP0 (C0G), X7R, X5R and X7S ceramic dielectrics* - in this order.• DO NOT USE Y5V

• Place additional units in parallel if one is not enough– Combine chemistries to benefit from their various advantages

• Use polymer, electrolytic and tantalum for bulk• Use Ceramics as your primary decoupling capacitor

69

Output Caps Selection – References

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• A. De Nardo, N. Femia, G. Petrone, G. Spagnuolo, “A unified method for optimal buck

converter output capacitor design”, Proc. Of ISIE2008, Cambridge, UK, pp. 56-61

• S. Maniktala, Switching Power Supply Design & Optimization, Mc Graw Hill, New York, 2004

• G. Spagnuolo, N. Femia, A. De Nardo, “Optimal Buck Converter Output Filter Design for Point

of Load applications”, IEEE Trans. Ind. Electron., DOI10.1109/TIE.2009.2030219, in press

• R.W. Erickson, D. Maksimovic, “Fundamentals of Power Electronics”, 2001 Kluwer Academic

Publishers

Paralleling capacitors to reduce high frequency output voltage ripple

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A technique for reducing High Frequency output noise

• If the output capacitor(s) is not ceramic; then adding a small ceramic(s) in parallel with the output will reduce high frequency ripple.

• Choose a ceramic capacitor that has an impedance null (self resonance) that is the same as the frequency to be attenuated.

• One, two or three small ceramics can give 10X improvement (-20 dB.)

73

High frequency ripple

Switch waveform (scope trigger)

Vout ripple w/ 20 MHz bandwidth (bw)

5 mV /div 10 mv p-p

HF spikes ignored !

74

Use Zoom function to measure ring frequency

20 MHz bw

200 MHz bw

2 GHz bw

Timebase Zoomed traces

300MHz ring

10 mV/div

100 mV/div

100 mV/div

Need to add 470 pF 0603 bypass SRF ~ 300 MHz

75

Continue the method

20 MHz bw

200 MHz bw

2 GHz bw

10 mV/div

100 mV/div

100 mV/div

115 MHz ring

Measured after adding a 470 pF 0603 but before adding 2200pF 0603


76

Continue the method

20 MHz bw

200 MHz bw

2 GHz bw

10 mV/div

100 mV/div

100 mV/div

60 MHz ring

Measured after adding a 470pF 0603 and a 2200pF 0603 but before 4700pF 0805


77

Results after 3rd added small capacitor

Measured after adding a 470pF 0603, 2200pF 0603, and 4700pF 0805

Ring ~377MHz

20 MHz bw

200 MHz bw

2 GHz bw

10 mV/div

100 mV/div

100 mV/div

78

Final amplitude improvement results

20 MHz bw

200 MHz bw

2 GHz bw

10 mV/div

10 mV/div

10 mV/div

20 mV p-p @ 20MHz bw

80 mV p-p @ 200MHz bw

After 470pF 2200pF 4700pF

79

Starting point for comparison - 3 caps removed

20 MHz bw

200 MHz bw

2 GHz bw

10 mV/div

200 mV/div

200 mV/div

696mVp-p @ 200MHz bw

80

Final schematic and bill of materials: 15 minutes later

Cost Approx < $0.03 USD

3.3µH 6AL1

220µF

0.0075 ohm6.3V

COUT1

GNDGND

+3.3VDC OUT

800 kHz Buck Switcher

Spe

cial

ty P

olym

er

470 pFNP0 (C0G)

COUT2470 pFNP0 (C0G)

COUT34700 pFX7R

COUT4

GNDGND

Remember to reserve locations on the schematic and PCB for these parts.

You will not know the capacitor values until after you test the running power supply for ringing noise.

Plan ahead

1.2VDC OUT @ 5A

2200pF

81

Bench requirements• 2GHz bw / 20Gsps Digital oscilloscope with zoom feature and adjustable

channel bandwidth.

• Selection of small capacitors pre-characterized by Self Resonant Frequency.

• High quality interconnections with controlled impedances.

Example of 3 channel input adapter built for this tutorial (net 4x passive probe)

CH2 - 20MHz

CH3 - 200MHz

CH4 - 2GHz

SOURCE 3 CHANNEL INPUT

50 OHM COAX49.9

RSOURCE

1.2VDC SOURCE

Use C0G (NP0) dielectric for high frequency shunt filter capacitors – lower ESR – more stable over temp

Start with manufacturer data sheets, then measure SRF on bench to confirm

82

Thank You

Questions?

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Documents

Capacitor Selection for DC/DC Convertors: From Basic Application to Advanced Topics TI – Silicon Valley Analog in Santa Clara California USA - This course