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Capacitor model for afloating gate EEPROM cellDAN YANG , ROBERT S. AXLEY & FAT DUEN HOPublished online: 10 Nov 2010.
To cite this article: DAN YANG , ROBERT S. AXLEY & FAT DUEN HO (1998)Capacitor model for a floating gate EEPROM cell, International Journal ofElectronics, 84:6, 561-581, DOI: 10.1080/002072198134418
To link to this article: http://dx.doi.org/10.1080/002072198134418
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INT. J. ELECTRONICS, 1998, VOL. 84, NO. 6, 561± 581
Capacitor model for a ¯ oating gate EEPROM cell
DAN YANG² , ROBERT S. AXLEY ² and FAT DUEN HO² ³
This paper presents a transient simulation model of a ¯ oating gate EEPROM cellbased on the capacitor equivalent circuit of the device. The model is compared witha capacitor equivalent circuit model previously presented in the literature. Themodel is used to simulate the write and erase cycle tunnel currents and the cellthreshold voltages of two di� erent EEPROM cells. The simulation results arecompared with the experimentally measured tunnel currents and with thesimulation results of the previously presented model.
1. Introduction
The ¯ oating gate thin oxide (FLOTOX) MOS transistor is the predominant typeof non-volatile memory (EEPROM) in use today. Device modelling provides a betterunderstanding of the device physics and can be used to establish design guidelines inorder to produce higher reliability devices. The capacitor equivalent circuit modelwill be used to simulate the tunnel current and the cell threshold voltage during thewrite and erase cycles of a FLOTOX cell. The magnitude of the tunnelling currenta� ects oxide aging, and, thus, the reliability of the device. The capacitor equivalentcircuit has been used previously to predict tunnel current and cell threshold voltage(Kolodny et al. 1986). This paper presents a di� erent approach to modelling thetunnel current and cell threshold voltage using the capacitor model and compares theresults of this model with experimental data and a capacitor model previously pre-sented in literature.
The architecture of the FLOTOX cell to be modelled is shown in ® gure 1 (Bezet al. 1990, Concannon et al. 1993). For the write operation, the drain is grounded, awrite pulse with a form as shown in ® gure 2 is applied to the control gate, and thesource is ¯ oating. During the write operation, electrons from the tunnel implant ¯ owto the polysilicon ¯ oating gate. The tunnelling current is related to the electric ® eldacross the tunnel oxide according to the well-known Fowler± Nordheim equation(Lenzlinger and Snow 1969)
Itun = a AtunE2tun exp ( - b
Etun ) (1)
where a and b are Fowler± Nordheim constants, Atun is the tunnel area above theoxide, and Etun is the electric ® eld across the oxide.
As the ¯ oating gate becomes more negatively charged, the voltage across thetunnel oxide decreases, and, consequently, Etun decreases until the Fowler±Nordheim current ceases. For the erase operation, the control gate is grounded,an erase pulse with a form as shown in ® gure 2 is applied to the drain, and thesource is ¯ oating. Electrons from the negatively charged ¯ oating gate ¯ ow across the
0020± 7217/98 $12.00 Ñ 1998 Taylor & Francis Ltd.
Received 15 August 1997; accepted 19 August 1997.² Department of Electrical and Computer Engineering, The University of Alabama in
Huntsville, Huntsville, Alabama 35899, USA.³ Author to whom correspondence should be addressed.
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tunnel oxide back to the tunnel implant. The tunnelling current during the erasecycle is also given by the Fowler± Nordheim relationship. As the ¯ oating gatebecomes more positively charged, the voltage across the tunnel oxide and the tunnelelectric ® eld decrease until the Fowler± Nordheim current ceases.
The cell threshold voltage is related to the ¯ oating gate charge by the followingequation
Vt = Vti - Qf g /Cpp (2)
where Vti is the initial cell threshold voltage with Qf g = 0, Qf g is the charge on the¯ oating gate, and Cpp is the control gate-to-¯ oating gate capacitance.
After a write cycle, the ¯ oating gate is negatively charged so the cell thresholdvoltage is increased. After the erase cycle, the ¯ oating gate is positively charged sothe threshold is reduced. The contents of the cell can be read by applying a voltage to
562 D. Yang et al.
Figure 1. Cross-section of ¯ oating gate EEPROM cell.
Figure 2. Write/erase pulse waveform.
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the control gate which is high enough to sense the condition of the ¯ oating gate, butis not high enough to change the charge on the ¯ oating gate due to the Fowler±Nordheim current. If a cell has been programmed (i.e. written to), the application ofthe read voltage will result in the cell channel remaining o� due to the increase in thethreshold voltage. If a cell has been erased, the application of the read voltage willresult in the channel being turned on. The read cycle cannot be modelled using thecapacitor equivalent circuit model because transistor action is not included in thismodel.
2. Theory
The capacitor equivalent circuit used for both the write and erase simulations isshown in ® gure 3. For both the write and erase models, the primary output will bethe tunnel current. Contact potentials (Asquith 1991, Tsividis 1987) were incorpo-rated into both models. VÂg , VÂs , V Âd and VÂb are de® ned as the terminal voltage plus itscontact potential while Vg, Vs, Vd and Vb only represent the terminal voltages.Contact potentials do not appear to have been taken into account in the previousliterature on EEPROM device models. For both the write and erase models, the onlyminority carrier generation mechanism considered is thermal, which is governed byBoltzmann’s statistics. As will be seen later, considering only the thermal generationmechanism does not accurately predict the tunnel current for the erase model forsome situations.
The EEPROM transient write and erase models presented in this paper anddescribed below will be referred to as the `Capacitor’ model. The Capacitor modelwill be compared with a EEPROM capacitor equivalent circuit model previouslypresented in the literature, which will be referred to as the `Kolodny’ model(Kolodny et al. 1986).
2.1. Write cycle modelFor the write cycle, the space charge region under the channel is assumed to be
inverted with a surface potential ( u s) of 2u f due to the high positive voltage coupledto the ¯ oating gate from the applied control gate voltage. The implant surface will be
Capacitor model for a ¯ oating gate EEPROM cell 563
Figure 3. FLOTOX capacitor equivalent circuit.
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accumulated so u sn = 0V. The tunnel current can be expressed as the derivative ofthe ¯ oating gate charge with respect to time and also in terms of the tunnel electric® eld using the Fowler± Nordheim equation
Itun =dQf g
dt= a AtunE2
tun exp ( - b
Etun ) (3)
Using the capacitor equivalent circuit, the ¯ oating gate charge is given by thefollowing equation
Qf g = Cpp(Vf g - VÂg) + Cgox(Vf g - (VÂb + 2u f ) ) + (Cimp + Ctun) (Vf g - VÂd)
+ Cgs(Vf g - Vs) + Cgd(Vf g - Vd) (4)
dQf g
dt= Ct
dVf g
dt - CppdVÂgdt
(5)
where Ct = Cpp + Cgox + Cimp + Ctun + Cgs + Cgd and VÂb, 2u f , VÂd and Vs are con-stant with time. Equation (5) is obtained by taking the time derivative of equation(4). Equation (6) is derived by setting equation (3) equal to equation (5), substitutingVf g /tox in for the tunnel electric ® eld (Etun) in equation (3), and solving for dVf g /dt
dVf g
dt=
Cpp
Ctslope -
Atun a ( Vf g
tox )2
exp ( - b tox
Vf g )Ct
(6)
where
slope =dVg
dt
Equation (6) is of the form dx /dt = f (x) with x = Vf g and can be solved for Vf g(t)using the Runge± Kutta method (Gerald and Wheatley 1984). (Note: dVg /dt isknown from ® gure 2.) The initial Vf g is determined from equation (4) if the initial¯ oating charge is known. After solving for Vf g(t) , Etun(t) can be calculated( (Vf g - VÂd) /tox) , and Itun(t) can be determined from equation (1). A ¯ ow diagramis given in Appendix A which provides an algorithm that could be used to implementthe Capacitor write model.
A ¯ ow diagram used to implement the Kolodny write method is also given in theAppendix for comparison. The primary di� erence between the Capacitor andKolodny methods for simulating the write cycle is the calculation of Vf g. For theKolodny model, only equation (4) was used to determine Vf g. For the Capacitormodel, a combination of equations (3) and (4) was used to calculate Vf g during eachtime step.
The transient threshold voltage can be calculated by using equation (2). The¯ oating gate charge is the only parameter in equation (2) which varies with time.Qf g can be determined each time step by adding the charge transferred to the ¯ oatinggate during each time step
Qf g(ti+1) = Qf g(ti) + D t(Itun(ti) ) (7)
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2.2. Erase cycle modelModelling of the erase cycle is more complicated because the conditions of the
channel space charge region and implant space charge region are not ® xed through-out the erase cycle (Asquith 1991). The channel space charge region ranges from theaccumulation at the beginning of the simulation, since the initial ¯ oating gate chargeis negative, to inversion at the end of the simulation. For the Capacitor model, thechannel surface potential was assumed to be a constant 2u f throughout the cyclewhile the implant surface potential was calculated for each time step.
An accurate calculation of the implant surface potential ( u sn) is necessary tosimulate accurately the transient tunnel current because u sn is used to determinethe tunnel electric ® eld which is used to calculate the Fowler± Nordheim tunnellingcurrent. For the Kolodny model, the implant surface potential was assumed to beconstant, 2u f n, while the channel surface potential is calculated for each time step.Based on equation (8) below, the implant surface potential is more critical to calcu-lating the tunnel electric ® eld and, thus, the tunnel current, than the channel surfacepotential
Etun =Vf g - u sn - VÂd
tox(8)
If the ¯ oating gate, tunnel oxide, and implant region are considered to form a two-terminal MOS device, the implant surface potential can be related to the ¯ oating gatepotential by using the following approximation to the solution of Poisson’s equationfor a two-terminal device (Tsividis 1987)
Vf g = VÂd + Vf b + u sn - g ( - u sn + VT exp ( - u sn + 2u f n
VT ) )1 /2
(9)
where Vf b is the two terminal MOS device ¯ atband voltage, g is the two terminalMOS device body coe� cient, u f n is the implant Fermi potential, and VT is thethermal voltage (0.0259 V).
Equation (3) also applies to the erase model. Using the capacitor equivalentcircuit, the ¯ oating gate charge is given by the following equation
Qf g = Cpp(Vf g - VÂg) + Cgox(Vf g - (VÂb + 2u f ) ) + Cgs(Vf g - Vs) + Cgd(Vf g - Vd)
+ (Cimp + Ctun) (Vf g - ( u sn + VÂd) ) (10)
dQf g
dt= Ct
dVf g
dt - (Cgd + Cimp + Ctun)Vd - (Ctun + Cimp) du sn
dt(11)
The following equation is derived by substituting the time derivative of equation(9) into equation (11) and substituting the result into equation (3) for dQf g /dt. Also,the Fowler± Nordheim current in equation (3) can be expressed in terms of theimplant surface potential by substituting equation (9) into equation (8).
du sn
dt=
a AtunE2tun exp ( - b
Etun ) - (Cgs + Cgox + Cpp) dVd
dt
Ct - Ctun - Cimp + Ct g1 + exp ( - u sn + 2u f n
VT )2(- u sn + exp (- u sn + 2u sn /VT) )1 /2
(12)
Capacitor model for a ¯ oating gate EEPROM cell 565D
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where Ct = Cpp + Cgd + Cgs + Cgox + Ctun + Cimp and
Etun =Vf b - g ( - u sn + VÂT exp ( - u sn + 2u f n
VT ) )1 /2
tox
Equation (12) can be solved for u sn(t) using the Runge± Kutta method (Gerald andWheatley 1984). (Note: dVd /dt is given by ® gure 2.) Etun(t) can then be calculated,and subsequently, Itun(t) can be determined. A ¯ ow diagram is given in the Appendixwhich provides an algorithm which could be used to implement the Capacitor erasemodel. The transient threshold voltage during the erase cycle can be calculated in thesame manner as the threshold voltage was calculated for the write cycle.
A ¯ ow diagram for the Kolodny erase model is also shown in the Appendix forcomparison. As stated previously, this model assumes the implant surface potentialis constant and calculates the channel surface potential during each time step. Thecondition of the channel surface (depleted or accumulated) is determined during eachtime step by initially assuming that the channel is depleted and using equation (10) tosolve for the channel surface potential. If the solution is imaginary, then the channelsurface is assumed to be accumulated, and the channel surface potential is zero. Ifthe solution is real, then the channel is assumed to be depleted, and the calculatedvalue is used as the channel surface potential. After determining the channel surfacepotential, Vf g is calculated using equation (10), and the tunnel electric ® eld andtunnel current are calculated in the same manner as for the Capacitor model.
Both the write and erase models shown in the Appendix could be easily imple-mented using Mathcad or similar software package. In the next section, simulationresults from the FLOTOX write and erase cycle models described above will becompared to experimental results (Bez et al. 1990, Concannon et al. 1993) as wellas to the Kolodny model.
3. Comparison of results
The EEPROM device parameters given in table 1 were used for the write anderase simulations since experimental data are available for these devices (Bez et al.1990, Concannon et al. 1993). Two di� erent cells were simulated. For cell A, thetunnel implant doping concentration was 5 ´ 1018 cm- 3, the tunnel oxide thickness(tox) was 1 ´ 10- 6 cm, and the maximum applied gate (write) and drain (erase)voltages were 16 V (Vpp). For cell B, the tunnel implant doping level was5 ´ 1019 cm- 3, the tunnel oxide thickness was 1.3 ´ 10- 6 cm, and Vpp as shown in® gure 2 was 19.5 V for both the write and erase simulations.
The Capacitor and Kolodny model simulations of the write cycle tunnel currentfor cell A are compared with the measured tunnel current in ® gure 4. For the writesimulations, the peak tunnel currents for the Capacitor and Kolodny models arewithin approximately 12.6% and 7.7% of the experimental value (0.588 nA), respec-tively.
The Capacitor and Kolodny model simulations of the erase cycle tunnel currentfor cell A are shown along with the measured tunnel current in ® gure 5. For the erasecycle, an anomalous’ peak is seen in the experimentally measured tunnel current;however, it does not appear in either the Capacitor or Kolodny model simulatederase tunnel currents. The existence and explanation of this anomalous peak during
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the erase cycle for moderately doped implants has been previously documented inthe literature (Bez et al. 1990, Concannon et al. 1993, Sune et al. 1991 ). Deepdepletion occurs under the tunnel oxide because the thermal generation rate ofholes is too slow to form an inversion layer. The surface potential ( u sn) increasesabove its thermal equilibrium value in the strong inversion condition (2u f n). Bandbending at the implant surface is su� ciently high such that band-to-band tunnellingcan occur in the silicon, which allows a positive charge layer to form at the implantsurface and establishes the surface potential at a constant value above 2u f n. Thisstationary value corresponds to the magnitude of the band bending at which theband-to-band tunnelling current equals the tunnel oxide current (Bez et al.1990).When signi® cant tunnel current starts to ¯ ow as result of the tunnel electric ® eld,energetic electrons entering the silicon generate hole± electron pairs through impactionization. The production of a large number holes allows the inversion layer toform resulting in the collapse of the deep depletion condition. When the deep deple-tion condition collapses, there is an instantaneous drop in the implant surface poten-tial to 2u f n. This drop causes an instantaneous increase in the tunnel electric ® eld(equation (8)) which results in the `anomalous’ peak. No anomalous peak is presentin the simulations of the erase cycle for cell A using the Capacitor and Kolodnymodels. As stated in section 2, only thermal carrier generation mechanisms wereconsidered for this model. The ramp speed is too fast for thermal generation ofminority carriers to be a factor, and, for cell A, band-to-band tunnelling couldoccur within the implant due to its moderate doping level. If the anomalous peakwere not considered, the Kolodny model (5.1% error) proved to be more accuratethan the Capacitor model presented in this paper (9% error).
Transient simulations of the cell A threshold voltage for the write and erasecycles using the Capacitor model and the Kolodny model are shown in ® gure 6. Thecell threshold voltage was calculated by using equation (2). There were no experi-mental data to compare with the calculated transient cell threshold voltage. There isapproximately a 2V di� erence between the Capacitor and Kolodny simulations. Acomparison of the simulation and experimental results for cell A is given in table 2.
For doping concentrations above 1 ´ 1019 cm- 3, silicon breakdown cannot occurdue to band bending; therefore, the anomalous peak should not occur (Bez et al.1990). The transient erase cycle tunnel current simulations are compared with the
Capacitor model for a ¯ oating gate EEPROM cell 567
Substrate doping 7E14/cm- 3
Tunnel implant doping 5E18cm- 3/5E19cm- 3 (Note 1)Channel width 5.5E-4 cmChannel length 3E-4 cmFloating Gate-to-Channel oxide thickness 5E-6 cmInterpoly oxide thickness 1.4E-6 cmTunnel oxide thickness 1E-6 cm/1.3E-6 cm (Note 1)Tunnel length 2E-5 cmFloating gate thickness 1.5E-5 cmControl gate length 4E-4 cma write / a erase 1.23E-6/1.82E-7 A V- 2 (Note 2)b write / b erase 2.37E8/1.88E8 Vcm- 1 (Note 2)Vpp ( ® gure 2) 16 V/19.5 V (Note 1)Applied gate/drain voltage ramp speed 104 V- 1 s
Note 1: Cell A parameter/Cell B parameter.Note 2: Di� erent Fowler± Nordheim constants are required for the write and erase simulations.
Table 1. EEPROM cell device parameters.
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Capacitor model for a ¯ oating gate EEPROM cell 569
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570 D. Yang et al.
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measured current for cell B (5 ´ 1019 cm- 3) in ® gure 7, and the anomalous peak isnot seen in the experimentally measured tunnel current. The Capacitor and Kolodnysimulations of the cell B write cycle tunnel current are compared with the measuredresults in ® gure 8. For both the write and erase simulations, the Capacitor modelpresented in this paper proved to be more accurate than the Kolodny method. Thepeak tunnel current percent errors for the Capacitor model were 0.2% and 3.3% forthe write and erase cycles while the percent errors for the Kolodny method were5.4% and 14% for the write and erase simulations.
The Capacitor and Kolodny transient simulations of the cell B threshold voltageduring the write and erase cycles are compared in ® gure 9. The di� erence between theCapacitor and Kolodny transient cell threshold voltage plots is approximately 0.7 V.The VTH plots for cell B for the Capacitor and Kolodny models match more closelythan the cell A plots because the di� erence in the tunnel currents (and, thus, the¯ oating gate charge) between the Capacitor and Kolodny methods is less for cell Bthan cell A. A comparison of the simulation and experimental results for cell B isgiven in table 3.
4. Conclusions
This paper demonstrates an alternative approach for using the capacitor equiva-lent circuit model to simulate the write and erase cycles of a ¯ oating gate EEPROMcell. The model can always be used to model the write cycle of a FLOTOX cell. Theanomalous peak seen during the erase cycle of cells with implant doping concentra-tions below 1 ´ 1019 cm- 3 cannot be observed with this model because only thethermal carrier generation mechanism is considered. A more complicated modelsuch as a ® nite element or ® nite di� erence method, which includes band-to-bandtunnelling is needed to simulate the anomalous peak. This model does accuratelymodel the erase cycle tunnel current for cells with implant doping levels above1 ´ 1019 cm- 3.
Capacitor model for a ¯ oating gate EEPROM cell 571
Peak tunnel Peak tunnel Cell threshold Cell thresholdcurrentÐ write currentÐ erase voltageÐ write voltageÐ erase
Method (nA) (nA) (V) (V)Capacitor model 0.662 0.535 5.406 - 5.102Kolodny model 0.543 0.618 3.505 - 7.16Experimental 0.588 0.588 (1) N/A N/A
(1) The anomalous peak (1.1 nA) was ignored.
Table 2. Comparison of cell A simulation and experimental results.
Peak tunnel Peak tunnel Cell threshold Cell thresholdcurrentÐ write currentÐ erase voltageÐ write voltageÐ erase
Method (nA) (nA) (V) (V)Capacitor model 0.573 0.623 3.893 - 8.670Kolodny model 0.543 0.554 3.209 - 8.156Experimental 0.574 0.644 N/A N/A
Table 3. Comparison of cell B simulation and experimental results.
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Capacitor model for a ¯ oating gate EEPROM cell 573
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Appendix
Flow diagrams of the Capacitor and Kolodny write and erase models
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Capacitor model for a ¯ oating gate EEPROM cell 579D
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Sune, J., Lanzoni, M., Bez , R., Olivo, P., and Ricco, B., 1991, Transient simulation of theerase cycle of ¯ oating gate EEPROMs. IEDM Technical Digest, 905.
Tsividis, Y. P., 1987, Operation and Modeling of the MOS Transistor (New York: McGrawHill).
Capacitor model for a ¯ oating gate EEPROM cell 581D
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