California State University,California State University,SacramentoSacramento

MixedMixed--Signal DesignSignal DesignLaboratoryLaboratory

Perry L. Heedley and Thomas W. MatthewsDepartment of Electrical & Electronic Engineering

An Engineering Team Approach toMentoring Graduate Students

through Projects

Perry L. Heedley and Thomas W. Matthews

Department of Electrical and Electronic EngineeringCalifornia State University, Sacramento

Outline

• Introduction• The Design Team Methodology

– Assembling the Team– The Architecture Phase– The Preliminary Design Phase– The Layout Phase– The Final Design Phase

• Chip Layouts & Team Photos• Experiences and Assessment• Results Achieved• Conclusions• Acknowledgments

Introduction

• Increasing pressures to reduce time-to-market fornew products, plus the increasing size & complexityof new “Systems On a Chip” (SOC), have forced thesemiconductor industry to adapt by forming ever-larger design teams to work on integrated circuits (ICs)

Example:

1997 – A 1st generation Gigabit Ethernet IC development employs 5 analog engineers, with 1 designing the ADC

2000 – The 2nd generation of the same IC employed20 analog engineers, with 5 designing the ADC alone!

Introduction

• This trend has increased the importance of teamwork and communications skills for new engineering graduates– Accreditation Board for Engineering and Technology (ABET)1

– Employers value employees with teamwork experience2

So, universities need to adapt as well !

This led the authors to create an “Engineering Team”approach to Master’s projects in IC design in theDepartment of Electrical and Electronics Engineeringat California State University, Sacramento

Introduction

• The Engineering Team approach has multiple benefitsto students. They are able to :– Gain valuable experience using proven industry methods & tools– Work on much larger projects than a single student could do alone,

in a much shorter time• e.g., Two teams of 7 graduate students each designed, laid out, and

taped out for fabrication 2 entire pipelined ADC chips in ~ 7 months!• A third team built a specialized biomedical chip during this same time.

– Learn about other student’s circuit blocks, in addition to their own• Each student is responsible for their own major circuit block

(e.g., a comparator), but assists with the entire chip– Gain valuable experience working together as a team

Exactly the type of experience industry is looking for!

Introduction

• The Engineering Team approach also has benefitsfor faculty members, such as :– Increased efficiency of instruction, e.g., by sharing information

with the entire team at once during group meetings & reviews– The ability to tackle larger, more difficult (and more interesting)

problems with an entire team of eager young engineers!

Example:This year’s teams at CSUS are designing 2 separate chips to:1) Prove a new calibration technique for Flash ADCs, and2) Compare the resistance of LC tank versus Ring Oscillator

based PLLs to supply and substrate noise

The Design Team Methodology

• The design team methodology developed at CSUS closely parallels that used successfully by the authors while working in industry on IC developments at several different semiconductor companies– Multiple phase design process– Reviews at strategic points during the IC development,

to identify and correct potential problems as they occur• Reviews typically occur at the end of each phase of the project• Students gain valuable experience preparing and presenting

professional style engineering reviews– Weekly team meetings between reviews to track progress

and address issues– Experienced engineers from industry act as advisors– Students work as a team to solve real engineering problems!

Assembling the Team

• Since not all interested students have the needed skills to succeed in an effort of this complexity, an interview and selection process is used– Faculty advisors probe both technical and communication skills– Whenever possible, the team leader is selected first and aids

in the selection of the remaining team members– Even those students not selected benefit by identifying areas

for improvement, and being exposed to a technical interview process similar to that used by industry

• Once the team is selected, circuit blocks are assigned– Each team member is responsible for the design, layout and

testing of a major circuit block on the chip (e.g., a comparator)– Both the students’ preferences and skill sets are considered

Assembling the Team

• Role of the team leader– Coordinates the efforts of the team members– Responsible for the system level design– Provides circuit block specifications to the team– Defines special test modes for the chip– Floorplans the IC layout and assigns block area/aspect ratios– Responsible for top-level chip assembly & simulations

(with help from the rest of the team!)

Note the importance of having a strong team lead !

Overview of the Design Team Methodology

• Characteristics of a good Mixed-Signal design methodology– Starts with a through literature review to understand previous work– Is broken into several phases, with peer reviews for each to allow

“mid-course corrections” before going too far down the wrong path

• Design Phases :– Architecture Phase – determine what needs to be built– Preliminary Design Phase – do initial design & get ready for layout– Layout Phase – create the preliminary layout– Final Design Phase – simulate with parasitics & finish the design

Overview of the Design Team Methodology

• Key points to remember :– Mixed-Signal design & layout is an iterative process!

(e.g., layout “tweaks” are typically required after simswith extracted parasitics)

– Think before just jumping in! Designing the wrong thing wastes both your time and the time of others, and may delay the chip

“We pay you to think, not just push transistors!”– Eric Swanson, former Crystal Semiconductor CTO

Purpose & Goals of the Architecture Phase

• The Purpose of the Architecture Phase is to :– Understand what you need to build to solve the problem– Find out how similar problems have been solved in the past– Examine tradeoffs between competing solutions– Identify any possible “show stopper” issues before design begins

• The Goals of the Architecture Phase are to :– Resolve any open issues that could affect your design– Decide exactly what it is that you plan to build in the

Preliminary Design Phase

Completing the design is not the goal of this phase!

Architecture Phase Tasks

• Perform a good literature review to understand :– What is the state-of-the-art for this type of circuit ?– What level of performance is possible in my process ?– What specs/tradeoffs are important to consider ?– What proven circuit topologies have been used in the past

to successfully solve this problem? (or similar problems)

• Decide where innovation is required– What are the new “value added” portions of your design?

• Understand what makes your chip better than the competition,and focus on that !

– What parts of your design can be borrowed from previous work?• Avoid “NIH” (Not Invented Here) thinking and re-inventing the wheel

– Innovation brings risk, so innovate only where required!

“You tried too many new things on that chip for it to work!”– Nav Sooch, Silicon Labs founder & former CEO

Architecture Phase Tasks

• Identify opportunities for reuse– e.g., can you build 1 op amp and use it in several places instead

of having to design & layout multiple op amps?

• Decide exactly what it is that you plan to build in the Preliminary Design Phase– All block architectures & circuit topologies are determined

• e.g., an interpolating flash or a sub-ranging ADC ?Interpolate by 2 or by 4 ?

– All required specs are determined• e.g., required speed and effective number of bits for an ADC ?

– All or most test modes have been identified and considered• It is usually easier and quicker to “build in” a test mode during

design than to add it later as an after thought

Purpose & Goals of the Preliminary Design Phase

• The Purpose of the Preliminary Design Phase is to :– Design any new circuits required– Verify the performance of any “borrowed” circuits in your application– Solve any known issues and flush out new ones– Show that your design meets all specs, including additional margin

to account for expected layout parasitics– Get ready for layout to start

• The Goals of the Preliminary Design Phase are to :– Complete your design to the point where it is ready to enter layout,

not to completely polish and finish the design!– Develop a layout floorplan for your block

• Aspect ratio, signal & power supply routing, device placement, etc.

Preliminary Design Phase Tasks

• Design any new circuits, down to the transistor level– Develop all needed test benches for simulations, including detailed

models for sources and loads– Run simulations to show all specs are met, with extra margin

for expected layout parasitics– Simulate over all standard corner cases defined for the chip, (e.g.,

process, temperature, supply voltage) plus any additional corners which could cause problems for this specific circuit

• Verify the performance of any “borrowed” circuits– Be sure that you understand the circuit, including any known issues– Run any sims needed to verify performance in your application

• A complete set of corner sims may not be needed, depending on the status of the block (e.g., has it already been proven in silicon?)

• Check the interfaces to your other blocks, plus any control signals• Be sure to exercise any unusual modes of operation being used

Preliminary Design Phase Tasks

• Develop a proposed floorplan for the block layout– Aspect ratio and orientation to be used– Requirements of neighboring blocks– Routing plans for noisy, quiet and high speed signals– Plans for power supply routing and bypass

• Plans to achieve goals for IR drops (DC)• Plans to achieve goals for supply bounce (AC)

– Sufficient area reserved for bypass caps?

– Plans for device placement, especially critical portions• High power devices, capacitor/resistor arrays, switches, etc.

Purpose & Goals of the Layout Phase

• The Purpose of the Layout Phase is to :– Layout any new blocks being designed– Place and connect any existing blocks being re-used– Engineer the layout to ensure all design goals are met

• The Goals of the Layout Phase are to :– Create a layout which meets all requirements for your block,

both in terms of how it fits into the overall chip layout and interms of circuit performance

Note that some iteration is virtually always requiredbetween the layout and final design phases!

(e.g., to identify and remove undesired parasitics)

Layout Phase Tasks

• Layout any new circuits– Start with a good floorplan for your layout, including plans for

aspect ratio, power busses, signal routing, device placement, etc.– Identify and layout any critical circuits, paying close attention to

good analog layout techniques (matching, symmetry, etc.)• e.g., differential pairs, current mirrors, capacitor & resistor arrays

– Layout the remaining devices and complete the wiring

• Place and connect all existing blocks being re-used– Be sure to understand the needs of all of the block’s I/O signals– Consider each block’s power requirements

• Are the power supply busses connecting to these blocks sufficientto meet the IR drop goals and electromigration rules?

• Does power for any neighboring blocks flow through these blocks?If so, do the power busses in these blocks need to be beefed up?

Layout Phase Tasks

• Consider any special requirements – For blocks connected to I/O pads: ESD, Latchup– Test-mode requirements: bypass modes, routing of test busses,

getting high speed signals off-chip cleanly, etc.

• Once the block passes all rule checks (DRC, LVS, etc.) plus visual inspection for matching, symmetry, etc., then run parasitic extraction on the block and begin simulations with parasitics (Final Design Phase)

Note that the visual inspection is critical, since problems with matching, symmetry, etc., are NOT detected by automated checks such as DRC & LVS!

Purpose & Goals of the Final Design Phase

• The Purpose of the Final Design Phase is to :– Identify and correct any problems in the block’s layout which

could cause performance problems• e.g., unintended coupling between signals, too much capacitive

loading on a node, lack of symmetry on differential signals, etc.

• The Goals of the Final Design Phase are to :– Complete the circuit design & layout and ensure that the final

design meets all specifications, including layout parasitics

Note that some iteration is virtually always requiredbetween the layout and final design phases!

(e.g., to identify and remove undesired parasitics)

Final Design Phase Tasks

• Repeat all simulations run during the Preliminary Design Phase, using the netlist extracted from the layout

• Check to make sure that all specifications are still met, including layout parasitics

• Finalize the design for Tapeout

• Tapeout your chip!

Layout of the ADC1 chip

Layout of the ADC2 chip

The ADC1 Team at our Tapeout Party!

The ADC2 Team at our Tapeout Party!

Experiences and Assessment

• In November 2003 the 1st design teams were formed– Two teams, each working on a separate 20MHz, 8-bit pipelined

Analog-to-Digital Converter (ADC) in 0.5µm CMOS• An industry standard 1.5 bit/stage architecture3 familiar to the

authors was chosen– Pursuing two projects with the same goal allowed test equipment

and procedures to be shared between the two teams• This redundancy also allowed the digital decode block to be shared

between the two teams when 1 team member left the project

• Due to the large number of qualified students which applied, a 3rd team was formed to build a specialized biomedical chip– Prof. Warren Smith advised this team, with the authors acting

as consultants on the IC portion of the design

Experiences and Assessment

• The Biomedical Design Team– The goal was to build a data acquisition and telemetry system that

could be implanted in a knee joint to measure stress after surgery.– IC includes a dual-slope ADC, a parallel-to-serial converter,

data transmission and power management circuitry• Problems the Biomedical Team encountered

– No team leader was selected initially, and one did not emergefor some time, which led to difficulty in making decisions

– A new system architecture had to be developed for integration.This type of “open ended” problem proved difficult for the team.

• A major problem was the number of unknowns (e.g., the input signal)• The Architecture Phase took much longer than expected• Eventually, some reasonable assumptions were made and

a system architecture was defined

• Although progress was slow, a successful chip resulted!

Experiences and Assessment

• Students are often unsure of their ability to make correct decisions and need to be mentored through the process. Faculty advisors can help them through this by :– Asking students the right questions– Having students make a choice and then defend it

• Students particularly need guidance regarding :– How to perform a good literature search

• General internet searches versus technical databases (e.g., IEEE)– Architecture choices for their circuit blocks

• Some of the first and most important decisions the students make!– The proper role of circuit simulators

• SPICE doesn’t replace sound engineering judgment!– The role of and expectations for design & layout reviews

Experiences and Assessment

• The team lead plays a critical role, so choose carefully!– Designs the system and defines circuit block specifications– Floorplans and assembles the layout for the overall IC– Answers questions when the faculty advisor is not present– Keeps the team enthusiastic and moving forward!

• The weekly team meetings should be focused on status, communication and planning– An additional “help session” to address technical issues helps

• The input of the industry advisors was very valuable,and greatly appreciated by the students

Results Achieved

• Both pipelined ADCs and the Biomedical chip were allfully functional on 1st silicon!– The ADC2 chip achieved 7.8 ENOB !– The ADC1 chip has a bug related to the common-mode output

voltage used in the residue amp. Use of test modes allowed7.0 ENOB to be achieved. Further debug & redesign ispresently underway

– The Dual-Slope ADC on the Biomedical chip is functioningcorrectly; further testing on the rest of the IC is in progress

Die Photo of the ADC2 chip

Conclusions

• The 1st Design Teams at CSUS were quite successful!– Positive feedback from both students & industry advisors– The students learned far more than from individual projects– All student ICs were fully functional and performed well

• The faculty advisors learned several keys to success :– A well defined project to provide clear directions to pursue,

including a clearly stated timeline with milestones– Regular team meetings, with all members in attendance– A strong team leader to keep the team focused and moving forward

Engineering experience is a plus, as is a great deal of enthusiasm– Industry advisors involved throughout the entire IC development

This first effort formed a strong basis forfuture student design teams at CSUS!

Acknowledgments

The authors wish to offer their sincere thanks to :

Kevin Geoghegan – ADC1 Team LeaderVilaysack Savengsueksa – ADC2 Team LeaderDavid Ha – Biomedical Team LeaderKen Dyer – Industry Advisor, KeyEye CommunicationsPatrick Isakanian – Industry Advisor, KeyEye Communications Chad Beach – CAD Advisor, Ample CommunicationsNishant Kajla – Bandgap Reference IC designer, CAD supportProf. Warren Smith – Biomedical Team Advisor, CSUSProf. Paul Hurst – Test equipment support, UC DavisProf. Steven Lewis – Test equipment support, UC Davis

plus all members of the CSUS Grad Student Design Teams!