Upload
others
View
2
Download
0
Embed Size (px)
Citation preview
Calibration of the ProtoDUNEADC Non-linearity
Wenqiang Gu
Brookhaven National Laboratory
1
Outline
• ProtoDUNE TPC readout electronics
• ADC nonlinearity (NL) and other issues
• Motivation and idea of the NL calibration
• Validation with a Monte Carlo study
• Summary and working plan
2
WIRE SIGNAL
• Cold preamplifier• Gain: 4.7, 7.8, 14, or 25 mV/fC
• Shaping time: 0.5, 1.0, 2.0, or 3.0 µs
• Cold ADC (Analog to Digital Converter)• Continuous time & amplitude discrete t & amp.
• 12 bits: 4096 minimum steps in full range (1.2V)
• 2 MHz sampling rate
ProtoDUNE TPC readout electronics
3
µBooNE: 14 mv/fC + 2.0 µs
V. Radeka et al. Cold electronics for ‘Giant’ Liquid
Argon Time Projection Chambers,
J. Phys. Conf. Ser. 308 (2011) 012021.
Readout scheme of ADC circuit
• 16 channels per ADC circuit
4
FPGA
InternalPattern
Generator
2:1MUXRST
READ
IDXM
IDXL
IDL
Clock 200MHz
(100MHz)
RST
READ
IDXM
IDXL
IDL
FEASIC
CHN0
CHN15
Input Buffer
ADC15
ADC0
D0 – D11
D0 – D11
FIFO
CLK1:CLK0
2 Global bits (CLK1:CLK0) 00 or 11 : Control signals from internal logic 01: ADC control signals directly from FPGA
P1 ADC ASIC
• 12 bits /channel saved in FIFO buffere.g. 2048 = 100,000,000,000
Most significant bits (MSB) Least significant bits (LSB)
Readout scheme of ADC circuit
• 16 channels split into two readout chains from FIFO
5
FPGA
InternalPattern
Generator
2:1MUXRST
READ
IDXM
IDXL
IDL
Clock 200MHz
(100MHz)
RST
READ
IDXM
IDXL
IDL
FEASIC
CHN0
CHN15
Input Buffer
ADC15
ADC0
D0 – D11
D0 – D11
FIFO
CLK1:CLK0
2 Global bits (CLK1:CLK0) 00 or 11 : Control signals from internal logic 01: ADC control signals directly from FPGA
P1 ADC ASIC
Readout scheme of ADC circuit
• The read/write logic must be synchronized through five control signals
6
FPGA
InternalPattern
Generator
2:1MUXRST
READ
IDXM
IDXL
IDL
Clock 200MHz
(100MHz)
RST
READ
IDXM
IDXL
IDL
FEASIC
CHN0
CHN15
Input Buffer
ADC15
ADC0
D0 – D11
D0 – D11
FIFO
CLK1:CLK0
2 Global bits (CLK1:CLK0) 00 or 11 : Control signals from internal logic 01: ADC control signals directly from FPGA
P1 ADC ASIC
Readout scheme of ADC circuit
• These five signals can be generated internally inside the ADC by a 200 MHz clock (2 MHz digitization) or taken externally
7
FPGA
InternalPattern
Generator
2:1MUXRST
READ
IDXM
IDXL
IDL
Clock 200MHz
(100MHz)
RST
READ
IDXM
IDXL
IDL
FEASIC
CHN0
CHN15
Input Buffer
ADC15
ADC0
D0 – D11
D0 – D11
FIFO
CLK1:CLK0
2 Global bits (CLK1:CLK0) 00 or 11 : Control signals from internal logic 01: ADC control signals directly from FPGA
P1 ADC ASIC
Known issues for current ProtoDUNE ADC
• Non-linearity (NL)
• Stuck bits• Some bits lost randomly in a wire
waveforme.g. 101,001 ⇒ 000,000 or 111,111
• Can be mitigated by identifying them and interpolating the waveform
• Low temperature degrades the electronics and read/write logics
8
noise
non-linearitystuck bit at 63
stuck bit at 0
Known issues for current ProtoDUNE ADC
• Non-linearity (NL)
• Stuck bits• Some bits lost randomly in a wire
waveforme.g. 101,001 ⇒ 000,000 or 111,111
• Can be mitigated by identifying them and interpolating the waveform
• External clock eases both issues
• NL is sensitive to clock settings9
Motivation of the NL calibration • 600e- ENC (equivalent noise charge) at ProtoDUNE
• Given 14 mV/fC (preamp) and 0.3 mV/ADC conversion
• 600 e- ≈ 0.1 fC ≈ 1.4 mV ≈ 4.5 ADCs
• Would like to control the NL below 4 ADC for ADCtrue-ADCmeasure in the useful range
By Hucheng10
Difficulty from a bench test to ProtoDUNE
• Bench test
11
WIRE SIGNAL
CALIBRATION SIGNAL(KNOWN VOLTAGE)
• ProtoDUNE
No direct voltage input!
Also, NL is sensitive to clock settings• (bench test) clock is tuned for
each ADC• (protoDUNE) one clock shared by
four ADC curcuits
Idea of the NL calibration setup
12
• Similar setup as in MicroBooNE• 6 bit pulser, i.e. 64 programmable amplitudes (
Effective sampling rate
• 0.5 μs sampling (2 MHz)
• shift t0 => effectively higher sampling rate
13
Direct measurement of non-linearity?
• Given a precise prediction of the preamp response
a direct measurement
• However, low temperature change the response significantly
14
ADCmeasureADCtrue
A MC simulatoin
A(t)
t
… 𝜂𝐺: 64*4
A(t)
t
× 1/ 𝜂𝐺
with NL
Naïve idea of the impact from NL
• Assuming pulse voltage and the preamp gain do NOT change the shape of response
• NL distorts the shape differently for high ADC and low ADC
15
V(t)
t
…
𝜂𝐺: 64*4pulse voltage& preamp gain
V(t)
t
× 1/ 𝜂𝐺
w/o NL
Sanity check with a MC simulation
w/o NL
with NL
All waveforms match perfectly
16
ADCmeasureADCtrue × 1/ 𝜂𝐺
Input NL in MC
Calibration strategy
• By assuming a function of non-linearity• a piecewise function• or a polynomial function
• Minimize the variance in A(t)/𝜂G• i.e. the effective response function
• ~O(10k) data points & ~O(10) unknowns
should be a solvable problem
• A channel by channel calibration plan
17
NL varies among channels
AD
Cm
easu
re
Proof of principle with MC simulation
ΔV
Pluse input
C (~185fF)pin62
Chn_N
CSA
SHAPER
Gain: 4.7, 7.8, 14, 25 mV/fC
VDAC: 0 ~ 1.2V63 steps
18
Amp output saturation
Amp input saturation
Pulse voltage
Pre
amp o
utp
ut
volt
age
9900 points10 MHz effective sample rate
• By ignoring some saturations in preamp, a 10k data set is possible
ADCmeasure / (VDAC × Gamp)
ADCtrue
AD
Cm
easu
re
𝜒2(𝛼) =
𝑖
𝐴𝑖 + 𝑓𝛼 𝐴𝑖 − 𝑅
𝛼−1 𝑡𝑘 𝐺𝑖2
𝜒2 minimization
19
i-th data point
NL correction function(To be fitted out)
index of the 𝛼-th iteration𝐺𝑖 = pulse voltage × preamp gain (A normalization of charge input)
Time tick for 𝐴𝑖
𝑅 𝛼−1 (𝑡𝑘) =1
𝑁σ
𝐴𝑖+𝑓(𝛼−1)(𝐴𝑖)
𝐺𝑖is the
effective response function(Calculated with the NL function from best fit of previous iteration)
(𝐴𝑖, 𝐺𝑖, 𝑡𝑘)
χ2 minimization (cont’)
𝑓 𝐴𝑖 =
𝑦0 +𝑦1 − 𝑦01000
𝐴𝑖 − 0 , 𝐴𝑖 ∈ [0,1000)
𝑦1 +𝑦2 − 𝑦11000
𝐴𝑖 − 1000 , 𝐴𝑖 ∈ [1000,2000)
𝑦2 +𝑦3 − 𝑦21000
𝐴𝑖 − 2000 , 𝐴𝑖 ∈ [2000,3000)
𝑦3 +𝑦4 − 𝑦31000
𝐴𝑖 − 3000 , 𝐴𝑖 ∈ [3000,4000)
= 𝑏0𝑦0 + 𝑏1𝑦1 + 𝑏2𝑦2 + 𝑏3𝑦3 + 𝑏4𝑦4
=
𝑏0 = 1 −𝐴𝑖
1000, 𝑏1 =
𝐴𝑖
1000, 𝐴𝑖 ∈ [0,1000)
𝑏1 = 1 −𝐴𝑖−1000
1000, 𝑏2 =
𝐴𝑖−1000
1000, 𝐴𝑖 ∈ [1000,2000)
𝑏2 = 1 −𝐴𝑖−2000
1000, 𝑏3 =
𝐴𝑖−2000
1000, 𝐴𝑖 ∈ [2000,3000)
𝑏3 = 1 −𝐴𝑖−3000
1000, 𝑏4 =
𝐴𝑖−3000
1000, 𝐴𝑖 ∈ [3000,4000) 20
For a piecewise function,the coefficients are calculated before the minimization
0 10
00
20
00
30
00
40
00
y1y2
y3y4 y5
𝐴𝑖
𝑓(𝐴𝑖)
bothers = 0
χ2 minimization (cont’)
• Given 𝑓 𝐴𝑖 from last iteration (𝛼-1 th) or initial guess (0-th), an effective response function 𝑅(𝑡𝑘) is obtained
e.g., 𝑓 𝐴𝑖 = 𝑏0𝑦0 + 𝑏1𝑦1 +⋯+ 𝑏4𝑦4 (five points)
𝜒2 = σ 𝐴𝑖 + 𝑏0𝑦0 +⋯+ 𝑏4𝑦4 − 𝑅(𝑡𝑘)𝐺𝑖2
=𝐴𝑖−𝑅𝐺𝑖…𝐴𝑚−𝑅𝐺𝑚
− −𝑏0𝑖
…−𝑏1
𝑖
…−𝑏2
𝑖
…−𝑏3
𝑖
…−𝑏4
𝑖
…
𝑦0𝑦1𝑦2𝑦3𝑦4
2
= 𝑀 − 𝑅 ⋅ 𝑆 2
⇒ By minimizing 𝜒2, {𝑦0, 𝑦1, 𝑦2, 𝑦3, 𝑦4} ≡ 𝑆 = 𝑅𝑇𝑅 −1𝑅𝑇𝑀
⇒ Iterate the minimization until 𝑓 𝐴𝑖 converges21
Evolution of the “best-fit” 𝑓(𝐴𝑖) and 𝑅(𝑡)
• Given initial value {𝑦𝑖} = {0, 0, 0, 0, 0}
• After several times of iterations, “best-fit” NL 𝑓(𝐴𝑖) and effective response 𝑅(𝑡) tends to be stable
• The spread in 𝑅(𝑡) significantly shrinks after minimization
22
True
Iter. #1Iter. #2𝑅
(𝑡)
True
InitialADC
tru
e–
AD
Cm
easu
re
ADCmeasure
Electronics response bias ≈ 9
NL bias?
For initial values {𝑦𝑖} = {𝑦true}
• Not surprising. Ture 𝑓(𝐴𝑖) and 𝑅(𝑡) are obtained given the initial values close to the true values
23
𝜒2= 5E-5 (iter# 5)
For initial values {𝑦𝑖} = {-10, -10,-10,-10,-10}
• The spread in 𝑅 𝑡𝑘 is barely seen after iterations of 𝜒2 minimization
• Smaller biases in both 𝑓 𝐴𝑖 and 𝑅(𝑡𝑘) than {𝑦𝑖} ={0, 0, 0, 0, 0}
• Will the bias be a problem? (next slide)
24
Δ=3.5
Initial
𝜒2= 0.0016 (iter# 5)
25
time
R(t
) -- “best fit” 1-- “best fit” 2-- true
Signal formation
𝐴𝑖 = 𝑅 ⋅ 𝐺𝑖 − 𝑓𝑖
Electronics response
Charge input
NL effect
Signal processing
𝐺𝑖 = 𝐴𝑖 + 𝑓𝑖 /𝑅
Signal measurement
NL correction
Electronics response
deconvolutionGiven a data set {𝐴𝑖, 𝐺𝑖}, and two “best-fits”
𝑓𝑖𝑅 = (𝐴𝑖 + 𝑓𝑖)/𝐺𝑖
𝑓𝑖′
𝑅′ = (𝐴𝑖 + 𝑓𝑖′)/𝐺𝑖
𝑅′𝐺𝑖 − 𝑓𝑖′𝑅𝐺𝑖 − 𝑓𝑖 ⇒ 𝑨𝒊 ⇐
Similarly, for a signal 𝐴𝑖, two effective NL and response lead to same charge results
For a charge 𝐺𝑖,
Two “best-fit” NL and responsesare equivalent for charge deconvolution!
MC validation of the degeneracy
• Given a same charge input, the waveform predictions are close (
Interim summary
• Principle of ADC nonlinearity (NL) calibration for protoDUNE was studied through a simplified Monte Carlo study (will improve it!)
• With a series of well controlled pulses to the charge preamplifier, an effective ADC NL and an effective electronics response function of the preamplifier can be obtained
• The ionization charge can be accurately extracted given these two effective response functions
27
Working plan
• Carlos Sarasty from Cincinnati University join us this summer
• Towards a more realistic MC• More realistic NL function (is minimization still available?)
• Induction plane waveform
• Pedestal
• Accuracy of preamplifier gain
• Impact of stuck bits
• Let’s work on real data!• Bench test data taken by Shanshan Gao (BNL)
• Verify the algorithm
28
Helpful discussion with DAQ group
• There are details to be worked out, but there is no show stopper
• Current difficulty in DAQ is that it takes 2 mins to change FE settings and switch to a new run
• Take 4 preamp gains, 64 pulser voltages, and 5 time-zero shift in calibration, it will take about 1.5 days in switching runs
• Two possible solutions:
a) Reduce the number of scan by studying the precision of calibration
b) Develop a new DAQ software module that allows FE changes during a run
29