CAE/CAD Tools

CAE/CAD ToolsCAE/CAD Tools

Technical University of SofiaFaculty of Electronics

ECAD Laboratory2008

Advanced level study Advanced level study programmeprogramme in inElectronics Design and Integration TechnologiesElectronics Design and Integration Technologies

28213-IC-1-2005-1-BE-ERASMUS-PROGUC-3 2006-2322 / 001-001 SO228213-IC-1-2005-1-BE-ERASMUS-PROGUC-3 2006-2322 / 001-001 SO2

Marin HristovMarin Hristov

CAE/CAD CAE/CAD ToolsTools

CADENCE Design CADENCE Design FrameworkFramework


Cadence Design Framework II is a common interface to the complete range of Cadence IC design tools. Using a common database and user interface, the framework allows easy cross checking between the various stages of the design flow, e.g. comparing the layout and the schematic.

The following describes the components of the Cadence Design Framework II which are used for digital design.


Cadence FLOWCadence FLOWDesignSpecifications

Schematic capture

Simulation

Layout and DRC

Extraction and LVS

Post-layout Simulation

DesignSpecifications

Schematic capture

Simulation

Layout and DRC

Extraction and LVS



Design SpecificationsDesign Specifications

Design Specification typically describe the expected functionality (Boolean operations) of the designed block, as well as the maximum allowable delay times, the silicon area and other properties such as power dissipation. Usually, the design specifications allow considerable freedom to the circuit designer on issues concerning the choice of a specific circuit topology, individual placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of the final design.

In a large-scale design, the initial design specifications may also evolve during the design process to accomodate other specs or limitations.


Design SpecificationsAs an example, the initial design specs of a one-bit binary full adder circuit are listed below:

Technology: 0.8 um twin-well CMOS Propagation delay of "sum" and "carry_out" signals < 1.2 ns

(worst case) Transition times of "sum" and "carry_out" signals <1.2 ns (worst

case) Circuit area < 1500 um^2 Dynamic power dissipation (at VDD=5 V and fmax=20 MHz) < 1

mW


Schematic CaptureSchematic Capture

The traditional method for capturing (i.e. describing) your transistor-level or gate-level design is via the schematic editor.

Schematic editors provide simple, intuitive means to draw, to place and to connect individual components that make up your design.

The resulting schematic drawing must accurately describe the main electrical properties of all components and their interconnections. Also included in the schematic are the power supply and ground connections, as well as all "pins" for the input and output signals of your circuit. This information is crucial for generating the corresponding netlist, which is used in later stages of the design. The generation of a complete circuit schematic is therefore the first important step of the design flow.


Schematic CaptureIn order to setup your environment to run CadenceCadence applications you need to open an xterm window and type. cdscdkthis script modifies your environment (sets PATH and exports variables). To see your current environment type the following at the prompt: set

Running the Cadence tools

Now you should be able to run the Cadence tools. Never run Cadence from your root directory, it creates many extra files that will clutter your root. Instead please create a directory (e.g. cadence) and start Cadence there by typing: mkdir cadencecd cadenceicfb &


Schematic CaptureThe command icfb & starts Cadence in the background and you should get a window with the icfb Command Interpreter Window (CIW) as below:

With the CIW you can launch other applications and you can also manage your files and libraries. For more information read here…


Schematic CaptureIn order to create new libraries go to File -> New -> Library from the File menu of the Library Manager. Then fill in the name of the new library (e.g. Tutorial) in the dialog window, and leave the Path empty. Click on Attach to existing tech library and choose AMI 060u C5N (#M, 2P, high-res) from all the options. Leave I/O Pad Type as Perimeter then click OK.


Schematic CaptureStart by clicking on the Tutorial library in the Library Manager window once, then go to File -> New -> Cell View and fill in with IVcurves as the cell name, schematic as the view name, and

Composer - Schematic as the tool, then press OK.

You should get the Virtuoso Schematic Editing window. You also have access to these commands (and others) from the menu. For more information read here…


Schematic CaptureOur first schematic will be used to plot IV curves. Click on the Instance button (which looks somewhat like an IC, or go to Add -> Instance), this will pop-up two small windows, one being a Component Browser window. In this window choose NCSU_Analog_Parts as the library, click on N_Transistors, then on nmos4 (an NMOS transistor with all 4 terminals, G, S, D, B):


Schematic CaptureIn Add Instance window you can place the 5 transistors by clicking on the left mouse button for the first transistor and then moving the mouse down and clicking again. Do that right now. If you make mistakes you can always go to Edit -> Undo and try again. You can press the ESC key on the keyboard to get out of the place instance mode or you can

keep placing other parts.


Schematic CaptureYou can also move, delete parts, please explore the different editing functions, you will only learn by making mistakes and then correcting them. Now we also need to add ports, wires and power supply. First let's add ground by clicking on Instance again and then choosing Supply-Nets and then gnd in the component browser window, then place one gnd below the 5 transistors.

For more How to Edit information read here…


Schematic CaptureThen add wires (narrow) to connect all transistor sources and bodies to the ground.

Now add 6 DC voltage sources, one for VDS and one for each VGS and then connect them with wires to the transistors. Unfortunately we also need to add 5 more "dummy" voltage sources (with a value of 0 V) so that we can plot the currents in the transistors. The DC voltage sources that we are going to use are in the Voltage_Sources directory with the name vdc.


Schematic CaptureFinally add the 5 dummy 0 V sources in series with the drains, and a voltage source vdc of 5 V for VDS. Press ESC to get out of the add instance mode. In case you made a mistake you can always go to Edit -> Undo, or you can correct your mistake by some form of edit.

For more information about Edit Properties, read here…


Schematic CaptureFor example, if you filled in the wrong value for the DC voltage for vdc you can always change that later by first selecting the instance (click on it in the schematic) and then go to Edit -> Properties -> Objects, then a pop-up window will appear where you can change what you want.



SIMULATIONAfter the description of a circuit is completed using the Schematic Editor, the electrical performance and the functionality of the circuit must be verified using a Simulation tool. The detailed transistor-level simulation of your design will be the first in-depth validation of its operation. Based on simulation results, the designer usually modifies some of the device properties in order to optimize the performance.

The initial simulation phase also serves to detect some of the design errors that may have been created during the schematic entry step. It is quite common to discover errors such as a missing connection or an unintended crossing of two signals in the schematic.


SimulationFor our first schema with 5 transistors in the Virtuoso Schematic window go to Tools -> Analog Environment. The design should be set to the right Library, Cell and View. First we need to choose the simulator , we will choose Spectre.

Go to Setup -> Simulator/Directory/Host, and choose Spectre in the pop-up window, then click OK.

For more information about Spectre, read here…


SimulationNow you need to choose the type of simulation, go to Analyses -> Choose... In this case we will choose a dc-sweep so click on the dc radio button, then on Component Parameter, then on Select Component (all of these in the Choosing Analyses dialog window) then on the VDS component in the schematic window and choose dc in the Select Component Parameter pop-up window and click OK.


SimulationAfter saving the file we can finally simulate! Click on the Netlist (more read here…) and Run button on the right or go to Simulation -> Netlist and Run. Click OK on the Welcome to Spectre window which should start the simulation:

For more detailed information, read here…


SimulationNext step is to go to Results -> Direct Plot -> DC which will pop-up your schematic window. Now you have to click on the signals you want to see. Since this is a dc-sweep we want to see the drain currents into the 5 transistors. In order to do this you have to click on the small red square at + terminal of each of the dummy power supplies in series with each drain.


SimulationMake sure you click on the red square (the pin) which means current, versus any other part which means net, or voltage. Click on all 5 power supplies. If you are pressing right on the pins a circle should appear around each chosen pin.


SimulationNow press on the ESC key (to finish choosing the signals) and you should get the desired simulation results, 5 IV curves as in the textbook.

For detailed information about Spectre, read here…


Hierarchical Schematic Hierarchical Schematic CaptureCaptureIf a certain circuit design consists of smaller hierarchical

components (or modules), it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. This step largely simplifies the schematic representation of the overall system.

A symbol view of the circuit is also required for some of the subsequent simulation steps, thus, the schematic capture of the circuit topology is usually followed by the creation of a symbol to represent the entire circuit. The shape of the icon to be used for the symbol may suggest the function of the module (e.g. logic gates - AND, OR, NAND, NOR), but the default symbol icon is a simple rectangular box with input and output pins. Note that this icon can now be used as the building block of another module, and so on, allowing the circuit designer to create a system-level design consisting of multiple hierarchy levels.


Hierarchical Schematic CaptureIn case you are going to use input, output and bidirectional ports (CMOS inverter), you can place these either by pressing the PIN button on the left or by going to Add -> Pin... First add one nmos4 transistor and one pmos4 transistor, a gnd and a vdd symbol (from the Supply_Nets directory in the NCSU_Analog_Parts library) and then an input port IN and and output port OUT.

For more information, read here…


Hierarchical Schematic CaptureNow connect everything with wires as an inverter and change the transistor properties such that the ratio of pmos to nmos is the "rule of thumb = 2", i.e. make the pmos 3um in width. Don't forget to connect the transistor bodies to the proper voltages (gnd for nmos and vdd for pmos). Your final schematic should look like this:


Hierarchical Schematic CaptureNow we can create a hierarchical schematic that uses the symbols that we just created. Go to the Library Manager and with the Tutorial library highlighted do File -> New -> Cell View and create a schematic view for a cell named InvRing. The Composer schematic editor window should open up. Let's create a schematic of a ring oscilator with 11 inverters. Click on instance and choose the symbol view of the cell inverter in the Tutorial library. We are going to place 6 inverters first and we can do that with just one command by filling the Array inputs, let's say Rows 1 and Columns 6 (all 6 inverters will be arranged horizontally).


Hierarchical Schematic CaptureNow click once to place the left most inverter, then move the mouse to the right and click again to place the remaining ones.


Hierarchical Schematic CaptureNow we only need to wire the 11 inverters into a ring and add a vdd and a gnd symbol from the NCSU_Analog_Parts -> Supply Nets library (leave them unconnected on the top).


Hierarchical Schematic CaptureMany times when you have a complex hierarchical schematic you may want to make modifications on different cells without having to close and open different windows. You can do that by traversing the hierarchy. You can traverse both up and down, for example you can go down from the InvRing schematic and make modifications in the inverter schematic, then go back up the hierarchy. To do that you have to click on the symbol that you want to descend to (in the Virtuoso Schematic window), then go to Design -> Hierarchy -> Descend Edit, then click OK on the pop-up dialog box.


Hierarchical Schematic CaptureNow we are going to create a hierarchical schematic at the logic (gate) level by using symbols for lower level schematics. When creating such a schematic it is sometimes necessary to use different gates with the same logic but with different transistor sizes (e.g. a "weak" inverter and a "strong" inverter). For these purposes it is good if the sizes of the transistors are parameterized. We will use the schematic and symbol for the inverter that we created earlier.


Hierarchical Schematic CaptureLet's copy the existing inverter cell to 4 other cells, let's call them: Invx1, Invx4, Invx16 and Loadx64, respectively. These will be a parameterized inverter with minimum size (x1), 4 times the minimum (x4), 16 times the minimum (x16) a fix load 64 times the minimum. In order to copy the cells first click on the library, then on the inverter cell, then go to Edit -> Copy, and fill the new name of the cell in the To unfilled part, and make sure that Copy All Views is checked. In this way you should get 4 more cells in the Tutorial library.


Hierarchical Schematic CaptureOpen the schematic view by double clicking on the schematic view in the Library Manager window. We now need to change the properties Width and Length for the transistors such that they are parameterized. Edit properties for the nmos and change Length to: Len and Width to: Wid, then pmos and change Length to: Len and Width to: a*Wid.


Hierarchical Schematic CaptureWhen we use this inverter in a hierarchical schematic we can now keep the default values or change the default values to go to a different technology (e.g. change Len to 0.25u for a 0.25u CMOS technology) or have different transistor strengths for different inverters.


Hierarchical Schematic CaptureNow change the sizes for Invx4, Invx16 and Loadx64. For all of them make the length Len, both for PMOS and NMOS. This is the standard practice for digital design where transistors are minimum length for high performance. Then make the widths:

a*b*Wid for PMOS, b*Wid for NMOS for Invx4 a*b*b*Wid for PMOS, b*b*Wid for NMOS for Invx16 a*c*Wid for PMOS, c*Wid for NMOS for Loadx64


Hierarchical Schematic CaptureWe should also edit the symbols of the 4 new cells to reflect their different characteristics. Let's do it though, go to the Library Manager and double click on the symbol view of the Invx1 cell. Go to Edit -> Properties -> Objects... and then clik on the text inv on the symbol itself. In the pop-up window fill Invx1 as the Label, then clik OK.


Hierarchical Schematic CaptureNow let's assign sizes to the 4 inverters. We are interested in the inverter delay for a fanout of 4 and assume that an inverter 4 times larger than the base size is equivalent to 4 base inverters. This means that we can keep the first inverter at the base size, make the second one 4 times larger, the 3rd one 16 times larger and the 4th one 32 times larger, simply by making the parameter b = 4.


Hierarchical Schematic CaptureThe last skill in the schematic entry will be to traverse hierarchy. For this go to Design -> Hierarchy -> Descend Edit and then click on the first inverter and then clik OK. You should get to the inverter schematic where you can verify that the sizes are actually as you would expect.


Simulation Hierarchical SchemaFor Simulation we use two inverters for delay such that we can take both tpLH and tpHL into account without having to do manual addition. In the Composer window go to Tools -> Analog Environment. The design should be set to the right Library, Cell and View.

We also need to set up inputs and power supply since we don't have explicit voltage sources. Go to Setup -> Stimuli.


Simulation Hierarchical SchemaWe need to setup both inputs (IN1) and the global sources (power supply). For IN1 use a pulse with amplitude 5 (Voltage 1=0, Voltage 2=5) with 0.4n rise and fall times and 1.6n pulse width and 4n period, make sure you enable it. Click on the Global Sources, you should have only one (vdd!). Click on Enabled, Function dc, Type Voltage, DC voltage 5, Source type dc, and click on Apply. Now you need to choose the type of simulation, go to Analyses -> Choose... In this case we will choose tran which is the default, 8n as the Stop time and moderate as the accuracy default. Save All.

The only other settings that we need are the variables a, b, c, Len and Wid, for now let's set a=2, b=4, c=64, Len=0.6u, Wid=1.5u.


Simulation Hierarchical SchemaThe variable a should now appear in the Design Variables list. Do the same for b, c, Wid, Len. All variables should now appear in the Design Variables list.


Simulation Hierarchical SchemaFor the simulation click on the Netlist and Run button on the right Click OK on the Welcome to Spectre window which should start the simulation. For simulation results go to Results -> Direct Plot -> Transient Signal which will pop-up your schematic window. Since this is a transient analysis we want to see a few voltages. In order to do this you have to click on the desired nets, then the ESC key. Click on OUT, IN1, IN2 and IN3.


Simulation Hierarchical SchemaNow we can measure tpLH, tpHL for the second and third inverters (signals IN2 and IN3). To do this accurately we are going to use the waveform calculator. Go to Tools -> Calculator in the Analog Environment window which should pop up the calculator.


Simulation Hierarchical SchemaNow do Analysis -> Start in the Parametric Analysis window. Once the simulations are over we can again plot the waveforms. Go to Results -> Direct Plot -> Transient Signal and then choose IN2 and OUT.


Simulation Hierarchical SchemaThe first observation that we can make is that the delays are quite close even if we changed the pmos/nmos ratio quite drastically (from 1 to 3), which should reinforce the idea that complementary static CMOS is non-ratioed. If we zoom on the HL transition you will discover that the fastest solution in this case is actually the a = 1 waveform where the pmos and nmos are equal (412ps vs. 468ps when a=2.8).


Simulation Hierarchical SchemaOn the other hand if you look at the LH transition you can see that the solution with a = 1 has a poor rise time while a = 1.4 or a = 1.6 have much better rise times and still have small delays. From this superficial analysis we can conclude that indeed a value around a = 1.5 (close to sqrt(2-3) = 1.41-1.73 as suggested in class) is close to optimal for delay and decent rise time.


Layout and DRC (Design Rule Checking)The creation of the mask layout is one of the most important steps

in the full-custom design flow, where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication, using a Layout Editor.

The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design. The designer must perform DRC (in a large design, DRC is usually performed frequently - before the entire design is completed), and make sure that all layout errors are eventually removed from the mask layout, before the final design is saved.


Layout and DRCNow we are going to create a layout for our inverter schematic. We are going to use the SCMOS_SUBM scalable CMOS design rules for submicron processes available from MOSIS. The AMI C5N process uses LAMBDA = 0.3u which seems to be in contradiction with the claim that it is a 0.5u process. LAMBDA = 0.3u is really chosen for satisfying the design rules for everything but transistor length which with extra step is done at MOSIS to reduce it from the drawn 0.6u to 0.5u. Change the width of the nmos to 5 lambda and of the pmos to 10 lambda.


Layout and DRCTwo windows should pop-up, the Virtuoso layout window screen and the LSW which is used for choosing the layers to be used:


Layout and DRCNow let's draw the gate. We'll draw another rectangle, 2 lambda wide, in the middle of the active region so that it overlaps the area by two lambda on each side. Click on poly in the LSW and then start from the point X: 1.65, Y: -3.90 to X: 2.25, Y: -1.20


Layout and DRCNow we need to add the two contacts, both 2 lambda on each side (0.60) and 2 lambda from poly and 1.5 lambda from the outside. Click on cc in the LSW and then draw the first rectangle from X: 0.45, Y: -2.85 to X: 1.05, Y: -2.25, then copy the rectangle to the position of the other contact by doing Edit -> Copy.


Layout and DRCWith this the active area for the nmos is done but we still need to put nselect around the active. Before we do that let's define the substrate contact area. Let's draw a pactive rectangle that is 5 lambda on each side adjacent to the nmos transistor, then copy a contact into the middle of this region.


Layout and DRCNow we need to surround the active area with select rectangles, nselect for the transistor and pselect for the substrate contact. These areas need to be 2 lambda larger than the active. Click on nselect first and draw a rectangle from X: 0.00 Y: -1.20 to X: 4.50 Y: -3.90


Layout and DRCThen draw a pselect rectangle around the substrate contact.


Layout and DRCNext is the pmos. The pmos is drawn in the same fashion except that nactive becomes pactive and viceversa and nselect becomes pselect and viceversa. Also the width is twice larger and we need two contacts on each side. Notice that we have drawn the nmos with the active area 6 lambda below the Y: 0.00 axis, draw the pmos 6 lambda above the Y: 0.00 axis.


Layout and DRCThere is just one more element needed for the transistors: the nwell for the pmos. Draw a rectangle that surrounds the pmos active area by 6 lambda (1.8 microns), you should get:


Layout and DRCWe also need to add metal 1 above the contacts that needs to overlap the contacts by 1 lambda.


Layout and DRCNow Run a preliminary DRC. Go to Verify -> DRC... then click on OK. Check your CIW window, you should have no errors, in case you have errors you need to go back and fix them.


Layout and DRCFirst let's route the output, click on metal 1 and then Create -> Path and draw a path from the drain of the pmos to the drain od the nmos (right side). The path is only 3 lambda wide so draw it aligned to the right most side. You have to double click to end the path.


Layout and DRCNow draw another path centered around the 0 axis to the end of the nwell.


Layout and DRCNow let's connect the input. Draw a poly path between the two gates. Observe that the default width of the poly line is correct: 2 lambda.


Layout and DRCNow start another poly line centered around the 0 axis going to the left and after you pass the 0,0 point and change to metal 1 by using the Change to Layer in the Create Path window. This should automatically insert a contact between poly and metal 1, click once to place the contact structure adjacent to the 0,0 point to the right. Double click when you reach the left-most edge of the nwell to end the path. In order to see all the layers in the contact "pcell" type Shift-F with the cursor in the layout window.


Layout and DRCThe only items left now are the vdd and gnd connections, we are going to use Create -> Polygon for those (we could also use rectangles or paths). Create the polygon using the points:

X: -1.35 Y: 4.65X: -1.35 Y: 5.55X: -3.30 Y: 5.55X: -3.30 Y: 7.35X: 5.70 Y: 7.35X: 5.70 Y: 5.55X: 1.35 Y: 5.55X: 1.35 Y: 4.65


Layout and DRCFor the ground we will simply copy this polygon, go to Edit -> Copy and then click on Upside Down in the Copy window. Now place the copied polygon at the bottom making conatct with the nmos source.


Extraction and LVS (Extraction and LVS (Layout Layout versus Schematic Check versus Schematic Check ))

Circuit extraction is performed after the mask layout design is completed, in order to create a detailed net-list (or circuit description) for the simulation tool. The circuit extractor is capable of identifying the individual transistors and their interconnections . The extracted net-list file and parameters are subsequently used in Layout-versus-Schematic comparison and in detailed transistor-level simulations (post-layout simulation).

After the mask layout design of the circuit is completed, the design should be checked against the schematic circuit description created earlier. The design called "Layout-versus-Schematic (LVS) Check" will compare the original network with the one extracted from the mask layout, and prove that the two networks are indeed equivalent. A successful LVS will not guarantee that the extracted circuit will actually satisfy the performance requirements. Any errors that may show up during LVS should be corrected in the mask layout - before proceeding to post-layout simulation.


Extraction and LVSFirst let's do some more "cleanup" of our existing layout. First observation is that we can move the metal 1 to poly contact such that we minimize the use of poly for routing. Go to Edit -> Stretch and move the contact "flush" with the poly.


Extraction and LVSGo to Edit -> Merge and then click on polygons and paths that can be merged (e.g. start with the output paths, then you can merge the vdd and gnd). Notice how they all become as if we had drawn polygons and there are no "lines" artificially separating the regions.


Extraction and LVSIn order to prepare for extraction and LVS we have to define the input and power supply pins in our layout as in the schematic. Go to Create -> Pin and enter IN as Name, input as I/O type and metal1 as Pin type.


Extraction and LVSPlace the pin on the leftmost side of the metal 1 shape used as an input. Simlarly place an output pin OUT on the right most end of the output metal 1 polygon and two inputOutput pins called vdd! and gnd! for power and ground on the respective metal shapes on the top and bottom of the layout. Notice the 4 squares that represent the pins in the layout.


Extraction and LVSGo to Verify -> Extract... Click on Set Switches in the pop-up window and then choose Extract_parasitic_caps.

Notice that here you could have generated pselect and nselect layers automatically, you may decide to do that in the future to save effort. Now click on OK


Extraction and LVSIn the icfb window make sure you have no errors. If there are no errors you can now open the newly created extracted view from the Library Manager by double clicking. Press Shift-F to see the symbols for the extracted transistors. Notice that the extracted view is a layout that also has an underlying schematic.


Extraction and LVSNow in the extracted window go to Verify -> LVS...

Press on Run and wait until the stop window pops up. This window simply signifies that LVS has terminated, not that the comparison was succesful. Click OK. In order to see that LVS verified the layout to correspond to the schematic click on Info in the LVS window.


Extraction and LVSThe thing left is to simulate the extracted view of the inverter with the associated parasitics. Since our cell layout is very small it is likely that the parasitics are so small that no significant simulation differences will be observed but in general the differences can be substantial for large complicated layouts.

First you need to create a symbol for your cell, with Design -> Create Cellview. Then create a new cell schematic that contains only your cell (as a symbol) with input and output ports and supply symbols (vdd and gnd). vdd and gnd need only be placed at the top level, no need to connect them to anything else.

Now let's start Analog Artist, in the newly created cell window go to Tools -> Analog Environment, then go to Setup -> Environment. This entry is an ordered list of cell views that contain information that can be simulated. The simulator will search until it finds one of these cellviews. The default entry does not contain an extracted cellview. We need to add an entry for extracted cellview in front of the schematic cellview. As a result of this modification, the simulator will use the extracted cell view of the cell, if one is available.


Extraction and LVSNow you can continue exactly as in the simulation tutorial and the only difference will be that you are simulating the extracted view (with the parasitics) and not the schematic view.


Post-layout SimulationPost-layout Simulation The electrical performance of a full-custom design can be best analyzed by performing a post-layout simulation on the extracted circuit net-list. At this point, the designer should have a complete mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with no violations.

If the results of post-layout simulation are not satisfactory, the designer should modify some of the transistor dimensions and/or the circuit topology, in order to achieve the desired circuit

performance under "realistic" conditions.


Post-layout SimulationIt is now time to run the program called Encounter for place and route.

The GUI will appear as in the following picture. To zoom in, draw a box with the right mouse button. To go back to full view, hit "f".


Post-layout SimulationEncounter uses configuration files to neatly organize the many pieces that make up a design. Go to "Design” and load in the file called "encounter.conf". Next we need to create a floorplan. Do "Floorplan -> Specify Floorplan". Set the Core Utilization to 0.5 and the space between the core and the boundary to 30um on all sides. A utilization of 50% leaves enough room for buffer insertion during optimization. Inside the 30um we will place supply rings.


Post-layout SimulationHit OK and floor plan will look as shown:


Post-layout SimulationNext we add supply rings. Do "Floorplan -> Power Planning -> Add Rings". Set the top and bottom layer to Metal3 and set the ring width to. Finally, make the ring centered in the channel. This will create 2 rings, for VDD and GND, around the core.


Post-layout SimulationGo to "Route -> Sroute" and press OK. The default values are okay. This will route all power tracks in Metal1 and will insert vias between the stripes, rings and tracks. Your layout will look as follows but with no vertical red lines.


Post-layout SimulationTo place the cells, go to "Place -> Place".


Post-layout SimulationClock Tree Insertion

The first step in timing optimization is to insert a clock tree. First we will have Encounter create a specification file. Do "Clock -> Create Clock Tree Spec" and put "buf" and "inv" as the footprints for the buffer and inverter. Encounter uses footprints to up- and down-size instances of the same functionality.


Post-layout SimulationTo create the clock tree do "Clock -> Synthesize Clock Tree" and accept the default values. Next we can run timing optimization based on the clock tree we inserted. Do "Timing -> Optimization" and check "PostCTS". Hit OK and the result can be seen in the command window.


Post-layout SimulationRouting

We use "Nanoroute" to perform global and detail routing. It is an extremely powerful router and replaces the older WRoute tool. To route the design, to "Route -> Nanoroute" and hit OK. To get actual layout on the screen in the gui window hit the layout button in view menu.


Now we can run post-route optimization. This allows Encounter to optimize the design based on actual wires. Any modified net will automatically be re-routed by Nanoroute. To start, do "Timing -> Optimization" and select "postRoute" mode. The result can be seen in the command window.



Post-layout SimulationThe final step is to add filler cells. These are empty cells that provide nwell continuity. Do "Place -> Filler -> Add Filler". Enter "FILL" as the cell name (in the IIT cell library this is the name of the filler cell). The value "FILLER" will be used as the prefix for the instance name of each filler cell added.


Post-layout SimulationAfter adding filler, hit "f" to redraw the window. It can be seen that the core area is completely covered with cell instances(your layout will be slightly different than following).


Post-layout SimulationThe last step is to export the design to GDS. This is the format used by Layout Editors (e.g. Cadence Virtuoso) and IC foundries. It requires a map file, to map layer names to layer numbers. In this case we use a map file that matches Mosis layer numbers. Do "Save -> GDS", choose any name for the resulting file and select the map file. Your GDS Structure name should be controller.


Post-layout SimulationFinally, go to "Design -> Save Design" to save the entire design to disk. Then next time you run Encounter, you can do "Design -> Restore Design".

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