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Rishi Chugh , Product Marketing , IPG
12/18/2019
Cadence
2 © 2019 Cadence Design Systems, Inc. All rights reserved.
Cadence Design Systems, Inc
Founded in 1988 by the merger of SDA Systems, Inc.
and ECAD, Inc.
Lip-Bu Tan, CEO
S&P 500
Nasdaq 100
Revenue
$2.3B*Employees
~8,000Countries
20
Exceedcustomer
expectations
Culture
Explorewhat’s
possible
Executewith quality
Elevate the team
Software and Programming
Industry
Source: Cadence Earnings Press Release, Q4 2019
https://www.cadence.com/en_US/home/company/newsroom/press-releases/pr-ir/2019/cadence-reports-third-quarter-2019-financial-results.html
• Estimated 2019 revenue
actual revenue may differ
3 © 2019 Cadence Design Systems, Inc. All rights reserved.
Cadence at a Glance
R&D INVESTMENT
$884MPATENTS WORLDWIDE
1600+
4,500+R&D ENGINEERS
1750+FIELD ENGINEERS
26 GLOBAL DEVELOPMENT CENTERSAll data as of end of Q4 2018
4 © 2019 Cadence Design Systems, Inc. All rights reserved.
Cadence Solution OfferingsS
ilicon
Digital Logic
Design
Digital Logic
Implementation
Analog and RF
IC Design
Analog and RF
IC Simulation
IC Package
Design
Processor and
Interface IP
SoC Functional
Verification
Firmware Verification
Syste
mIn
telli
gence
PCB Design
Advanced IC
Package Design
Electro-Magnetic
Analysis
Electro-Thermal
Analysis
Secure Embedded
Software
Functional SafetySoftware / SoC
Validation
FPGA
Prototyping
ML-Enabled PCB
and Packaging Flows
AI Edge
Compute IP
ML-Enabled Silicon
Design Tools
ML-Enabled Silicon
Design Flows
5 © 2019 Cadence Design Systems, Inc. All rights reserved.
IoT / IndustrialCloud / DatacenterMobile Automotive Aero / Defense Health
Cadence Intelligent System Design Strategy…Thinking Outside The Chip
Cloud Enabled — Partnerships with Ecosystem Leaders
System
Innovation
Pervasive
Intelligence
Design
Excellence
• Front-to-Back PCB Design
• Multi-Chip(let) Advanced Packaging
• System-Level Electrical/Thermal Modeling & Analysis
• Embedded Software and Security
• Analog and RF IC
• Full-Flow Digital IC
• Verification Suite
• Interface and Processor IP
• Machine Learning
• Artificial Intelligence
• Fully Automated Place and Route
6 © 2019 Cadence Design Systems, Inc. All rights reserved.
The Beginning of the “More Than Moore” Era
• For the past five decades, the electronic industry has thrived while enjoying the benefits of Moore’s Law. But things are changing…The economics of semiconductor logic scaling are gone
• Gordon Moore knew this day would come. He also predicted that ”It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected”.
• Heterogeneously integrated packaging (SiP) will be leveraged to design the next generation of electronic products
• SiP will replace SoC
• The generation of “More Than Moore” is here…
7 © 2019 Cadence Design Systems, Inc. All rights reserved.
Is Moore’s Law Already Dead?
• It’s more than the limitations of physics…
• Cost per transistor has steadily increased since 2012/3 (28nm)
• Designing chips at the latest nodes is hard and expensive
• Low-volume businesses can’t justify the NRE costs of designing an SoC at the latest node
• Requires huge teams of engineering specialists that aren’t always easy to find
• Systems and software companies now designing chips and challenging the status quo of SoC approach
• Todays SoC’s are reaching reticle limits…but big chips don’t yield anyways
• More Analog/RF content in today’s designs. • Analog/RF never have benefited from
Moore’s Law
8 © 2019 Cadence Design Systems, Inc. All rights reserved.
• Processor to memory latency reduction – Stack thinned memory chips with controller
– Place memory stacks very close to processor on silicon interposer (2.5D IC)
– Dramatic reduction in size
– Simplifies board-level design
– Drastic reduction in latency
– Reduction in power
– Thermal needs proper consideration
More Than Moore Example…
Board-level
implementation
Package-level
implementation
9 © 2019 Cadence Design Systems, Inc. All rights reserved.
SerDes
USB
PCIe
CCIX
DDR
VT Mon
ADC
DAC
PLL
AFE
System
PeriphCamera Secure
DSP
Memory
Ether Display NAND eMMC
GPU
Application
Processor
Special Sauce
(Custom Logic)Memory
• SiP becomes the new SoC?– Modular approach vs monolithic approach
– Not everything needs to be designed in the same process node
– Leveraging IP in the form of chiplets– IP that is physically realized working on a standard
communication interface (AIB, PCIe®, HBM, etc.)
Transitioning to “More than Moore”…Heterogeneous Integration
Physically realized and tested
IP with standard/common
communication interface;
primary component of
heterogeneous integration
Chiplet
The new modularized SoC (long-term vision)The new IP
10 © 2019 Cadence Design Systems, Inc. All rights reserved.
Multi-Chip Module
(MCM) RF Module
Heterogeneous Integration
Disaggregated SoC
1970 2005 Future
Evolution of Multi-Chip(let) Packaging…
2008
Silicon Interposers
2.5D IC
2018
FOWLP
3DIC
System in a Package
(SiP)
1998
11 © 2019 Cadence Design Systems, Inc. All rights reserved.
The Next Packaging Paradigm Change is Here…
Mechanical Design Tools PCB-Like Design Flows IC-Like Design FlowsHybrid Design Flows
Leadframe BGA/LGA 3D-IC2.5D-IC/FOWLP/
Embedded Bridges
12 © 2019 Cadence Design Systems, Inc. All rights reserved.
What Are We Announcing ?
Cadence® UltraLink™ D2D PHY IP
• High-performance, low-latency PHY IP for die-to-die connectivity– Fastest NRZ D2D PHY – 40Gbps
– Targets cloud HPC and networking applications – 1Tbps/mm beachfront bandwidth
– Supports MCMs on organic substrate. No silicon interposer required – 130um bump pitch
– 7nm process – The preferred node for the HPC market
• IP is proven in 7nm silicon
• Extends Cadence’s existing HPC IP portfolio
13 © 2019 Cadence Design Systems, Inc. All rights reserved.
Package Substrate
Chiplet Value Proposition
• Allow flexibility in choosing process node, core die and SerDes don’t need to be on the same process node
• Achieve better yield by reducing die size
• Shorten IC design cycle and simplify integration complexity by separating high-speed SerDes into chiplet
• Lower manufacturing cost by purchasing known good die
14 © 2019 Cadence Design Systems, Inc. All rights reserved.
Die-to-Die Interconnect Tradeoffs
Can we avoid using high-cost packaging? (e.g.silicon
interposer or InFO)
What are the most critical metrics?
There’s NO one size fits all solution for D2D connectivity
Is the system proprietary or we need an eco-system?
15 © 2019 Cadence Design Systems, Inc. All rights reserved.
Die-to-Die Interconnect Options
Parallel Interface
Ex: AIB, HBM, HBI
(2-4Gbps NRZ)
Required by advanced packaging – silicon interposer or InFo
Pros: Lowest power, low latency, must-have
for HBM
Cons: High wire count, high package cost, low yield, reliability issue
NRZ Serial Interface
Ex: 20-30Gbps NRZ
Pros: Support organic substrate, easy routing,
low latency
Cons: Higher power, design complexity
PAM4 Serial Interface
112G-PAM4
Pros: Industry standard (CIE-OIF-XSR112G)
Cons: Requires FEC for "error-free" links, higher latency, higher power
Fastest, higher bandwidth, low latency
Cadence® UltraLink™ D2D PHY IP
16 © 2019 Cadence Design Systems, Inc. All rights reserved.
Example: 51.2 Tbps Switch
• Organic substrate (MCM)
• Each chiplet provides 6.4T bandwidth
• Use 8 chiplet to support 51.2T total bandwidth
• D2D interface between I/O chiplets and cores
• D2D interface between two cores
UltraLink D2D PHY
17 © 2019 Cadence Design Systems, Inc. All rights reserved.
Example: AI/ML Accelerator
• 2.5D interposer for HBM
• 112G SerDes provides chip-to-chip connectivity
• D2D interface between I/O chip-lets and the core
UltraLink D2D PHY
18 © 2019 Cadence Design Systems, Inc. All rights reserved.
Under the Hood: UltraLink™ D2D PHY IPHigh-bandwidth, low-power, low-latency die-to-die interconnect
Package Substrate
½ SoC ½ SoC
Off
-Pa
ckag
e In
terc
onn
ect O
ff-Pa
ckag
e In
terc
onn
ect
Die-to-Die Interconnect
Ultra
Lin
k D
2D
RX
Ultra
Lin
k D
2D
TX
Ultra
Lin
k D
2D
TX
Ultra
Lin
k D
2D
RX
x12,
500Gbps
x12,
500Gbps
1 m
m
Fwd Clock
Fwd Clock
1.3mm
• Flexible line rate of 20-40Gbps NRZ
• ~500Gbps bidirectional bandwidth in 1mm of
beachfront (1Tbps/mm aggregate)
• Support 8dB insertion loss (20+mm trace)
• Low power and ultra-low latency
• Forwarded clock
• Raw BER of 1e-15, no FEC
• Sideband for link management
• Targets 130u bump pitch for MCM applications
• Also supports micro bump for silicon interposer
• Integrated Spacial encoding and lane-to-lane de-
skew logic
19 © 2019 Cadence Design Systems, Inc. All rights reserved.
Cadence® UltraLink™ D2D PHY IP Test Board
20 © 2019 Cadence Design Systems, Inc. All rights reserved.
UltraLink™ D2D PHY IP TX: 40Gb/s
21 © 2019 Cadence Design Systems, Inc. All rights reserved.
Bump Diagram Example240 Gbps Full Duplex (480Gb Aggregate) Bandwidth in 0.5 mm of die edge
• TX Group
7 TX, 2 Clk, 2 Sideband,
• RX Group
7 RX, 2 Clk, 2 Sideband,
• Group. [X: 260u, Y: 1300u]
• 1Tx and 1 RX groups shown above
– Line Rate 20-40Gbps
– Effective number of Lanes after coding overhead – 6 TX, 6 RX
– Bandwidth 240G RX + 240G TX Total Power for configuration 360mW @ 40G, 180mW @ 20G
– Die Edge 0.5 mm , Die Area 0.68 mm2
High Speed
Signals in 1st 4
rows
TCLKP TCLKN RCLKP RCLKN
VDD GND VDD GND
TX3 GND GND RX3
VDD GND VDD GND
TX2 TX6 RX6 RX2
VDD GND VDD GND
TX1 TX5 RX5 RX1
VDD GND VDD GND
TX0 TX4 RX4 RX0
520u
1300u
260u
22 © 2019 Cadence Design Systems, Inc. All rights reserved.
UltraLink 40G RX On Die Eye Plot
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65535 65535 65535 65535 65535 65535 0 0 0 0 0 0 1046 65535 65535 65535 65535
65535 65535 65535 65535 65535 29622 0 0 0 0 0 0 124 65535 65535 65535 65535
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65535 65535 65535 65535 65535 28 0 0 0 0 0 0 0 932 65535 65535 65535
65535 65535 65535 65535 65535 4 0 0 0 0 0 0 0 103 65535 65535 65535
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65535 65535 65535 65535 65535 0 0 0 0 0 0 0 0 16 65535 65535 65535
65535 65535 65535 65535 65535 0 0 0 0 0 0 0 0 102 65535 65535 65535
65535 65535 65535 65535 56158 0 0 0 0 0 0 0 0 395 65535 65535 65535
65535 65535 65535 65535 65535 0 0 0 0 0 0 0 0 2450 65535 65535 65535
65535 65535 65535 65535 65535 0 0 0 0 0 0 0 0 5439 65535 65535 65535
65535 65535 65535 65535 65535 12 0 0 0 0 0 0 0 12625 65535 65535 65535
65535 65535 65535 65535 65535 100 0 0 0 0 0 0 0 29636 65535 65535 65535
65535 65535 65535 65535 65535 348 0 0 0 0 0 0 3 52524 65535 65535 65535
65535 65535 65535 65535 65535 1387 0 0 0 0 0 0 9 65535 65535 65535 65535
65535 65535 65535 65535 65535 8364 0 0 0 0 0 0 64 65535 65535 65535 65535
65535 65535 65535 65535 65535 37275 0 0 0 0 0 0 231 65535 65535 65535 65535
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Long Channel
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65535 65535 65535 65535 65535 1682 13 0 0 0 2 38372 65535 65535 65535 65535 65535
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65535 65535 65535 65535 65535 47 0 0 0 0 0 559 65535 65535 65535 65535 65535
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65535 65535 65535 65535 42668 0 0 0 0 0 0 0 7949 65535 65535 65535 65535
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65535 65535 65535 65535 2893 0 0 0 0 0 0 0 348 65535 65535 65535 65535
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65535 65535 65535 65535 278 0 0 0 0 0 0 0 26 65535 65535 65535 65535
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65535 65535 65535 0 0 0 0 0 0 0 0 0 0 0 65535 65535 65535
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65535 65535 65535 1 0 0 0 0 0 0 0 0 0 0 53602 65535 65535
65535 65535 65535 0 0 0 0 0 0 0 0 0 0 0 65535 65535 65535
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65535 65535 65535 65535 26502 0 0 0 0 0 0 0 0 52 65535 65535 65535
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65535 65535 65535 65535 65535 61 0 0 0 0 0 0 0 334 65535 65535 65535
65535 65535 65535 65535 65535 667 0 0 0 0 0 0 0 760 65535 65535 65535
65535 65535 65535 65535 65535 5879 0 0 0 0 0 0 0 3401 65535 65535 65535
65535 65535 65535 65535 65535 27218 0 0 0 0 0 0 0 4653 65535 65535 65535
65535 65535 65535 65535 65535 65535 0 0 0 0 0 0 0 13658 65535 65535 65535
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65535 65535 65535 65535 65535 65535 294 0 0 0 0 0 0 51486 65535 65535 65535
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Short Channel
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