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Cu 1. D FF.

library ieee ;use ieee.std_logic_1164.all;use work.all;

------------------------------------------entity dff isport( data_in: in std_logic;

clock: in std_logic;data_out: out std_logic

);end dff;

------------------------------------------architecture behv of dff isbegin

process(data_in, clock)begin

-- clock rising edge

if (clock='1' and clock'event) thendata_out

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use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;

---------------------------------------------------

entity ALU is

port( A: in std_logic_vector(1 downto 0);B: in std_logic_vector(1 downto 0);Sel: in std_logic_vector(1 downto 0);Res: out std_logic_vector(1 downto 0)

);

end ALU;

---------------------------------------------------

architecture behv of ALU isbegin

process(A,B,Sel)begin

case Sel iswhen "00" => Res Res Res Res Res

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end process;

-- cocurrent process#2: combinational logiccomb_logic: process(current_state, a)begin

-- use case statement to show the-- state transistion

case current_state is

when S0 => x

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--}} End of automatically maintained section

architecture ktrachuoibit of ktrachuoibit istype state is(s0,s1,s2,s3);signal s:state;begin

next_state: process(rst,clk)begin

if rst='1' thens

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architecture behv1 of Mux isbegin

process(I3,I2,I1,I0,S)begin

case S iswhen "00" => O O O O O y y y y y y y y O O O O

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when others => O

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signal Pre_Q: std_logic_vector(n-1 downto 0);

begin

-- behavior describe the counter

process(clock, count, clear)begin

if clear = '1' thenPre_Q