C IEEE Statistical Power Estimation for IP-based Design

8/9/2019 C IEEE Statistical Power Estimation for IP-based Design

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The rest of this paper is organized as follows. In Section IIwe give the background of input parameters of ourmacromodel. In Section III, we discuss about ourmacromodel construction. Our macromodel is evaluated insection VI. Section V summarizes our work.

II. POWER MACROMODEL CHARACTERIZATION

Similar power macromodeling techniques were presentedin [13], [14], [15]. Our macromodel consist of a nonlinearfunction based on LUT approach. This model estimates theaverage power dissipation:

),,,( ininininavg T S D P f P = (1)

The function f is obtained by a given IP macro-block, thecomponents are simulated under different input samplestreams with Pin, Din, S in, T in. The input metrics of functionare the average input signal probability Pin, average inputtransition density Din, input spatial correlation S in and inputtemporal correlation T in. Given an IP macro-block with the

number of primary inputs r and the input binary stream

),...,...,,(),,...,,{(2222111211 r r

qqqqqqq= )},...,,( 21 sr s s qqq of length s, these metrics are defined as follows [11], [14],[16], [17], [18]:

sr

q P

s

j ij

r

i

in×

=∑∑ == 11

(2)

)1(

1

1 11

−×

⊕

=∑∑ −

= +=

sr

qq D

s

i jiij

r

j

in

(3)

)1(

111

−××

⊕

=∑∑∑ ===r r s

qqS

s

i ik ij

r

k

r

j

in

(4)

sr

q yT

t s

t j j

r

j

in×

⊗

=∑∑ +−

−=

1

11)(

(5)

The macromodel function f in (1) can be used to construct to

a set of functions A f , B f , C f and D f that maps the input

metrics of a macro-block to its output metrics Pout , Dout ,

S out , T out . The output metrics of functions are the averageoutput signal probability Pout , average output transitiondensity Dout , output spatial correlation S out and outputtemporal correlation T out .

( )inininin Aout T S D P f P ,,,= (6)

( )inininin Bout T S D P f D ,,,= (7)

( )ininininC out T S D P f S ,,,= (8)

( )inininin Dout T S D P f T ,,,= (9)

Genetic Algorithms (GAs) [21] have proved success insolving electronic design problems [22], [23] and haveshown a high degree of flexibility in handling powerconstraints [21]. They are more dynamic to combine powerof randomness and evolution to analyze large solution space.For this reason, they are more useful with large space relatedproblems, where an exact approach is not applicable.Therefore, GAs are good candidates for solving powerestimation problems. Once the I/O metrics are selected, theI/O sequences are computed by our genetic algorithm (GA)method [19], [20]. Monte Carlo zero delay simulationtechnique is performed and for the IP macro-blocks, thepower dissipation is predicted by our macromodel function.The interpolation scheme [11], [12] can be applied (toimprove the power sensitivity concept), if the input metricsdo not match on their characteristics. The flow of the RTLpower estimation is shown in “Fig. 1,”.

III. MACROMODEL CONSTRUCTION

Several approaches [13], [14], [15] have been proposed toconstruct power macromodel on ISCAS-85 benchmarkcircuits. We have observed that the same methodology worksas well for IP macro-blocks such as array multipliers,comparators in terms of the statistical knowledge of theirprimary inputs/outputs. By the following method of [11], we

Fig. 1. The flow of RTL power estimation.

Input Pattern

RTL Circuit

Power Simulator

Convergence ?No

Yes

Average Power

Estimation

Power

Libraries

Operation for

generating new

patterns

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found that a good choice of the Pavg in (1), for arraymultipliers and comparators circuits.

In our static power estimation procedure, the sequence ofan input stream is generated at the inputs and usingsimulation, the output stream sequence is extracted by theoutput waveforms. The power dissipation is predicted usingPavg. All this process we can divide into two steps. In firststep, the metrics of the I/O sequences are computed by our

GA method [19], [20] and the power dissipation is predictedusing Pavg in (1). The interpolation scheme [12], [13] can beapplied (to improve power sensitivity concept), if the inputmetrics do not match based on their characteristics. In secondstep, Monte Carlo zero delay simulation [8] is performedwith different sequences of their signal statistics and evaluatethe quality of Pavg. At end we get the power estimationresults.

IV. MODEL ACCURACY EVALUATION

In this section, we show the results of our LUT basedpower macromodeling approach. We have implemented thisapproach and built the power macromodel at RTL. The

accuracy of the proposed model is evaluated on IP macro-blocks. For those blocks, we generated random input vectorsfor different values of Pin, Din, S in, T in and the function f in(1) is used to construct to a set of functions

A f , B f , C f

and D f

that maps the input metrics of a macro-block to its output metrics Pout , Dout , S out , T out . The inputsequences we use are highly correlated generated by our newmethod. The power is estimated using Monte Carlo zerodelay simulation technique. The power values predicted byLUT are compared with those from simulations, and averageerror and maximum errors are computed.

Experimental results show that our generated sequencesare with accurate statistics and high convergence. For theinput metrics, Pin, Din, S in, T in we specify the range between[0.1, 0.9]. We generated 550 sequences with 8, 16, 32 bitswide. The sequence length is 2000 and 1000 vectors formacro-blocks.

A. Pattern Validation and Power Sensitivity

It is evident from the “Table I” that the function isaccurate for estimating the average power for arraymultiplier and comparator circuits. In “Table I” the firstcolumn shows the name of the circuits. Columns two andthree give the average and maximum relative error for theestimates obtained with our macromodel. Reference values

for the circuit’s power dissipation are obtained using timedelays from the Synopsys PowerCompiler. In ourexperiments, the average absolute error is 1.84%, and theaverage maximum error is 3.17%. The maximum worst-caseerror is no more than 11.31%.

The results show that the transition density is veryeffective for power dissipation and it is relatively linear tothe power. The correlation metrics do not effect significantly

power dissipation and less sensitive than transition density.We have observed that the number of inputs does notinfluence at the output metrics for comparator-blocks, whilefor the array multiplier-blocks results are vice versa. In “Fig.2,” we illustrate the combined scatter plot of intellectualproperty macro-block between our macromodel and thereference simulated power. Regression analysis is performedto fit the model’s coefficients. For different blocks, we

measured prediction correlation coefficient around 97%.

TABLE I

ACCURACY OF POWER ESTIMATION

Fig. 2. Power comparison between macromodel

and reference simulated power.

Circuits Average Error Max Error

Mult8x8-1 0.76% 2.36%

Mult8x8-2 1.53% 3.02%

Mult8x8-3 0.60% 2.99%

Mult4x4-1 0.65% 2.31%

Mult4x4-2 2.15% 3.00%

Mult4x4-3 2.92% 4.70%

Mult4x4-4 0.94% 2.44%

Mult4x4-5 10.07% 11.31%

Mult4x4-6 1.21% 2.83%

Comp-1 1.60% 2.96%

Comp-2 0.29% 1.10%

Comp-3 0.73% 1.57%

Comp-4 0.47% 0.66%

9 9.5 10 10.5

9.2

9.4

9.6

9.8

10

10.2

10.4

10.6

Power from Macromodel

P o w e r f r o m

S i m u l a t i o n

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100 200 300 400 500 600 700 800 900 10001.05

1.1

1.15

1.2

1.25

1.3

1.35

Interval Length (Clock Cycle)

P o w e

r ( m W

)

Steady State

200 400 600 80 0 1000 120 0 1 40 0 1 600 18 00 2 0008.5

9

9.5

10

10.5

11

11.5

12


P o w e r ( m W

)

Steady State

200 4 00 600 800 1000 1200 1400 1600 1800 200036

38

40

42

44

46

48

50

52


P o w e r ( m W

)

Steady State

Fig. 3. Power changes with respect to sequence lengthfor different IP blocks.

B. Convergence Analysis

The minimum simulations length can be determinedthrough convergence analysis. Converging on the averagepower figure help us to identify the minimum lengthnecessary for each simulation, by considering when thepower consumption gets close to a steady value. In ourimplementation, we start with the quadratic model. The

sequences generated by our GA have high convergence anduniformity. “Fig. 3,” plots the variation of the power valuewith the trial interval length. Figure shows the interval lengthis 2000 and 1000 for different IP blocks. The warm-up lengthis about 400, 600, and 800 while the vertical line representsthe steady state value at 600, 1200 and 1400 respectively.

V. CONCLUCIONS

We have presented a new power macromodelingtechnique for high-level power estimation. The experimentalresults show that our power estimation is faster than low-level. Our technique was applied on IP macro-blocks usingthe zero delay model for the given input sequence and has

demonstrated good accuracy. Our model showed averageerror of 1.84% and prediction correlation coefficient of 97%.We are currently evaluating our macromodel on sequentialcircuits. We are also exploring the accuracy of ourmacromodel when propagating estimated output statisticsthrough characterized blocks.

VI. REFERENCES

[1] X. Liu and M. Papaefthymiou, “A static powerestimation methodology for IP-based design,” in Proceedings IEEE Conference on Design, Automation,and Test in Europe, 2001.

[2] A. A. Ghose, S. Devdas, K. Keutzer and J. White,“Estimation of average switching activity incombinational and sequential circuits,” in Proceedingsof the 29

th Design Automation Conference , June 1992,

pp. 253-259.[3] F. N. Najm, R. Burch, P. Yang, and I. N. Hajj,

“Probabilistic simulation for reliability analysis ofCMOS circuits,” IEEE Transactions on Computer-

Aided Design of Integrated Circuits and Systems, April1990, 9(4):439-450.

[4] R.Marculescu, D. Marculescu, and M. Pedram, “Logiclevel power estimation considering spatiotemporalcorrelations,” in Proceedings of the IEEE InternationalConference on Computer Aided Design, Nov. 1994 pp.

224-228.[5] G.Y. Yacoub and W.H.Ku, “An accurate simulationtechnique for short-circuit power dissipation,” inProceedings of International Symposium on Circuitsand Systems, 1989, pp. 1157-1161.

[6] C. M. Huizer, "Power dissipation analysis of CMOSVLSI circuits by means of switch-level simulation,” in

IEEE European Solid State Circuits Conf., 1990, pp.61-64.

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[7] C. Deng. “Power analysis for CMOS/BiCMOS

circuits,” in Proceedings of 1994 International Workshop on Low Power Design, April 1994, pp. 3-8.

[8] R. Burch, F. N.Najm, P.Yang, and T.Trick, ”A MonteCarlo approach for power estimation,” in IEEE Transactions on VLSI Systems, March 1993, 1(1):63-71.

[9] C-S. Ding, C-T.Hsieh, Q. Wu and M. Pedram,

“Stratified random sampling for power estimation,” inProceedings Int’l Conf. on Computer Aided Design,Nov. 1996, pp. 577-582.

[10] S. Gupta and F.N. Najm, “Power macromodeling forhigh level power estimation,” in Proceedings 34

th

Design Automation Conference, June 1997.[11] S. Gupta and F.N. Najm. “Analytical model for high

level power modelling of combinational and sequentialcircuits,” in Proceeding IEEE Alessandro VoltaWorkshop on Low Power Design, March 1999.

[12] Z. Chen, K. Roy, and T. L. Chou, “Power sensitivity-anew method to estimate power dissipation consideringuncertain specifications of primary inputs,” inProceedings IEEE International Conference on

Computer Aided Design, Nov. 1997.[13] Z.Chen and K.Roy, “A power macromodeling

technique based on power sensitivity,“ in Proceedings35

th Design Automation Conference, June 1998.

[14] S. Gupta and F.N. Najm, “Power Macromodeling forHigh Level Power Estimation,” in Proceedings IEEETransactions on VLSI, 1999.

[15] X. Liu and M. C. Papaefthymiou, “Incorporation ofinput glitches into power macromodeling,” in Proceedings IEEE Inter. Symp. On Circuits and

Systems, May, 2002.[16] M. Barocci, L. Benini, A. Bogliolo, B. Ricco, and G.

De Micheli, “Lookup table power macro-models for

behavioural library components,” in Proceedings IEEE Alessandro Volta Workshop on Low Power Design,March 1999.

[17] G. Bernacchia and M.C. Papaefthymiou, “Analyticalmacromodeling for high-level power estimation ,” in Proceedings for IEEE International Conference onComputer Aided Design, Nov. 1999.

[18] X. Liu and M.C. Papaefthymiou, “HyPE: Hybrid powerestimation for IP-Based Systems-on-Chip”, inProceedings for IEEE Trans on CAD of integratedcircuits and systems, July 2005, Vol. 24, No.7, pp.1089-1103.

[19] Y. A. Durrani, T. Riesgo, F. Machado, “Powerestimation for register transfer level by genetic

algorithm”, in Proceedings for InternationalConference on Informatics in Control Automation and

Robotics, August 2006.[20] Y. A. Durrani, T. Riesgo, F. Machado “Statistical

power estimation for register transfer level,” InProceedings for International Conference for MixedDesign of Integrated Circuits and Systems, June 2006,pp. 522-527.

[21] L. Davis, “Handbook of Genetic Algorithm”, V. N.Reinhold, New York, 1991.

[22] M. J. O’Dare, T. Arslan, “Generating Test Patterns forVLSI Circuits Using a Genetic Algorithm”, InProceeding IEE Electronics Letters, May 1994, Vol.30, 10, pp. 778-779.

[23] T. Arslan, D. H. Horrocks, E. Ozdemir, “StructuralCell-Based VLSI Circuit Design Using a GeneticAlgorithm”, International Symposium on Circuits andSystems, Atlanta, USA, 1996.

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C IEEE Statistical Power Estimation for IP-based Design