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1
BROADBAND BALUN EMBEDDED MEASUREMENT FOR DIFFERENTIAL CIRCUITS
By
KOOHO JUNG
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2007
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© 2007 Kooho Jung
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To my family, friends, teachers, and the people of Cascade Microtech
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ACKNOWLEDGMENTS
My foremost honor goes to my family and friends for their incessant support. Among
them, I’m in forever debt to my dear parents, whose teachings through examples has enlightened
and strengthened my morals, patient, compassion, and logical thinking.
I am very grateful to have studied at the University of Florida. I thank my advisor, Dr.
William R. Eisenstadt, for his invaluable teachings and for his generous care for us students
during our difficulties, which I will try my best to follow through out my future career. I also
thank my co-adviser, Dr. Robert M. Fox, for showing the ways for theoretical approaches in
identifying the key problems, which became a central tool in my engineering strategies. I also
thank other members of my committee, Dr. Kenneth K. O and Dr. Oscar D. Crisalle, for their
critical feedback through out my research. I thank my colleagues, Jongshick Ahn, Sudeep
Puligundla for their help through numerous discussions and for their valuable friendship. I also
thank my seniors and friends at the Gainesville Korean Catholic Community, which became a
second family to me through many volunteered work, among which, Sanghoon Han, Jangsup
Yoon, and Hyeopgoo Yeo, who had always looked after for my well-being with the utmost
generosity.
I thank the past and present engineers of Cascade Microtech; Richard Campbell, Peter
Navratil, Mike Andrews, Leonard Hayden, and Thaine Allison, and its founders, K. Reed
Gleason and Eric W. Strid, for providing the internship opportunity and for their continuous
support, which became the essential driving force for this work. I also thank the Center for
Circuit and System Solutions (C2S2) of Focus Center Research Program (FCRP) for their
support and providing helpful networks to other leading research groups. Furthermore, I thank
the Ministry of Information and Communication, Republic of Korea, for the scholarship, and Dr.
Dong-Ho Lee of Hanyang University, Republic of Korea, for his recommendation.
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I give special acknowledgement to my advisors during my Master’s program at Hanyang
University, Republic of Korea - Dr. Jongin Shim and Dr. Yungseon Eo. Their passion for science
and the intellectual search for answers had influenced me in so many ways. It was my great
honor to have had learn from them which I will treasure for the rest of my life.
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TABLE OF CONTENTS page
ACKNOWLEDGMENTS ...............................................................................................................4
LIST OF TABLES...........................................................................................................................8
LIST OF FIGURES .........................................................................................................................9
ABSTRACT...................................................................................................................................13
CHAPTER
1 INTRODUCTION TO BALUN EMBEDDED MEASUREMENTS ....................................15
1.1 Advantages of Differential Circuits..................................................................................15
1.2 Conventional Measurements of Differential Circuits.......................................................16
1.3 Proposed Measurements of Differential Circuits Using Broadband Baluns ....................18
1.4 Applications Beyond Network-Analyzers........................................................................19
2 BACKGROUND THEORIES IN BALUNS AND MIXED-MODES S-PARAMETERS ...21
2.1 Introduction Mixed-Mode S-Parameters ..........................................................................21
2.2 Mixed-Mode S-parameter Calculation Using SPICE.......................................................25
2.2.1 Extraction Circuits for Mixed-Mode S-parameters ................................................25
2.2.2 Application Examples ............................................................................................29
2.3 Introduction to Balun and Relative-Bandwidth................................................................36
3 MARCHAND BALUN EMBEDDED PROBE .....................................................................39
3.1 Introduction to Marchand Balun Embedded Probe ..........................................................39
3.2 Coaxial Marchand Balun and the Migration to its Planar Type .......................................39
3.3 Analytical Derivation for Optimum Design .....................................................................45
3.3.1 General Quarter-Wavelength Coupled TL .............................................................45
3.3.2 Optimum Design for Planar Marchand Balun........................................................48
3.3.3 Common-Mode Matching ......................................................................................50
3.4 Structural Realization .......................................................................................................51
3.5 Measurement Results........................................................................................................55
4 CHARACTERIZATION AND CALIBRATION FOR 3-PORT ERROR NETWORK .......58
4.1 Introduction to 3-port Error-Box and its Characterization ...............................................58
4.2 Proposed ISS and Extraction Algorithm...........................................................................59
4.2.1 Proposed ISS ..........................................................................................................60
4.2.2 Required Measurements .........................................................................................61
4.2.3 Extracting S-parameters of the 3-port Error-Box...................................................62
4.2.4 Verification and its Comparison to the Use of 7 Dual-Load Patterns....................65
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4.3 Application to Marchand Balun Embedded Probe ...........................................................66
4.4 Calibration ........................................................................................................................66
5 EVALUATION OF ERRORS CAUSED BY COMMON- AND CROSS-MODES.............70
5.1 Measurement Errors Caused by Common-Modes and Cross-Modes...............................70
5.2 Common-Modes and Cross-Modes in Balun Embedded Measurements .........................70
5.3 Error Evaluation and the Used Approximations...............................................................71
5.4 Application to Fully-Differential Amplifier .....................................................................78
6 ACTIVE BALUN USING COMBINED CASCODE-CASCADE CONFIGURATION......83
6.1 Introduction to Various Active Baluns .............................................................................83
6.1.1 Distributed Amplifier Type ....................................................................................84
6.1.2 Differential Amplifier Type ...................................................................................85
6.1.3 Source-Drain Output Configuration .......................................................................85
6.1.4 Common-Source and Common-Gate Pair Configuration ......................................87
6.2 The Proposed Combined Cascode-Cascade Configuration..............................................88
6.3 Measurement Environment...............................................................................................94
6.4 Measurement Results........................................................................................................97
6.5 Low-Pass Bias-Feedback Network for Stable Bias Conditions .....................................101
6.6 Summary and Applications.............................................................................................105
7 CONCLUSION.....................................................................................................................106
LIST OF REFERENCES.............................................................................................................110
BIOGRAPHICAL SKETCH .......................................................................................................115
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LIST OF TABLES
Table page 3-1 Using double-coax vs. using PCB coupled-TL in realizing Marchand-coupling...................45
4-1 Used s-parameter values for simulation verification..............................................................66
4-2 RMS errors of the extracted s-parameter values ....................................................................66
6-1 C3-balun’s internal bias points and AC voltage swings at 5 dBm input................................90
6-2 Forward gains of C3-balun for the input power of -25 dBm ~ 5 dBm.................................100
6-3 Change of bias performances of the proposed C3-balun due to process variations .............105
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LIST OF FIGURES
Figure page 1-1 Circuits in their various types ............................................................................................15
1-2 Conventional method for measuring a differential circuit using a 2-port VNA................17
1-3 Balun embedded measurements.........................................................................................19
2-1 Nodal scattering-wave representation of three-port and four-port circuit .........................21
2-2 Mixed-mode scattering-wave representation of three-port and four-port circuit ..............22
2-3 Decomposing nodal voltages in terms of propagation direction .......................................26
2-4 Extraction circuit for [Δs]4’s first and third .......................................................................27
2-5 Extraction circuit for [Δs]4’s second and fourth column ...................................................28
2-6 Extraction circuit for [Δs]3 .................................................................................................29
2-7 Two-staged 5GHz CMOS fully-differential amplifier ......................................................31
2-8 SPICE-based extraction of [Δs]4 for the circuit shown in Figure 2-8................................32
2-9 Layout of a differential transformer with unbalanced coupling of a nearby loop .............33
2-10 Circuit model of a differential transformer shown in Figure 2-9.......................................33
2-11 SPICE-based magnitude extraction of [Δs]4 for the circuit shown in Figure 2-10 (4-port case)............................................................................................................................34
2-12 SPICE-based phase extraction of [Δs]4 for the circuit shown in Figure 2-10 (4-port case) ...................................................................................................................................34
2-13 SPICE-based magnitude extraction of [Δs]3 for the circuit shown in Figure 2-10 (3-port case)............................................................................................................................35
2-14 SPICE-based phase extraction of [Δs]3 for the circuit shown in Figure 2-10 (3-port case) ...................................................................................................................................35
2-15 Rat-race balun operating at 6 GHz.....................................................................................37
3-1 Cross-sectional view of a coaxial cable and its currents....................................................40
3-2 Coaxial Marchand balun ....................................................................................................40
3-3 Transmission-line model of Marchand balun ....................................................................42
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3-4 Equivalent circuit for the impedance seen at Marchand balun’s differential port .............42
3-5 Normalized frequency plot of the differential-mode impedance seen at Marchand balun’s differential port......................................................................................................43
3-6 Planar-type Marchand balun ..............................................................................................44
3-7 General λc/4 coupled transmission-line .............................................................................46
3-8 Impedances of planar Marchand balun with symmetric λc/4 coupled TL.........................48
3-9 Simulation results of an optimized planar Marchand balun operating at fc = 6 GHz ........49
3-10 Planar Marchand balun with common-mode matching .....................................................50
3-11 Cross-section of various coupled microstrip-TL structures...............................................51
3-12 Cross-section of the proposed coupled microstrip-TL structures ......................................52
3-13 PCB layout of the proposed Marchand balun ....................................................................53
3-14 Proposed balun embedded probes......................................................................................54
3-15 Measuring balun embedded probes using a dual-through connected to a dual-probe.......55
3-16 Measurement results of the proposed balun embedded probes .........................................56
4-1 Full Characterization of the 3-port error-box in the measurements using balun embedded probe .................................................................................................................59
4-2 Proposed impedance-standard-substrate (ISS) ..................................................................60
4-3 Required measurements for the proposed extraction algorithm ........................................61
4-4 Flowgraph of the ISS measurement through the error-box ...............................................63
4-5 Extracted s-parameters of a balun embedded probe using the proposed ISS and extraction algorithm and their comparison with the previous method of using a dual-though pattern connected to a dual-probe..........................................................................67
4-6 Full 2-port balun embedded measurement and their 2 x 2 differential-mode s-parameter matrices .............................................................................................................68
5-1 Mixed-mode flowgraph for differential measurement using baluns..................................71
5-2 Mixed-mode flowgraph for VNA’s non-calibrated s11 and s21 ..........................................72
5-3 Mixed-mode flowgraph for VNA’s non-calibrated s22 and s12 ..........................................74
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5-4 Measuring dual-reflections of the DUT.............................................................................77
5-5 Rat-race type balun; mismatches were randomly induced from the shown nominal values in order to achieve large CXM ...............................................................................78
5-6 Mixed-mode s-parameters of a Rat-race type balun shown in Figure 5-5.........................78
5-7 Fully-differential amplifier; 10% variations were randomly induced from the shown nominal values in order to achieve large CXM .................................................................79
5-8 Mixed-mode s-parameters of the fully-differential amplifier shown in Figure 5-7...........80
5-9 Differential-mode s-parameters of the DUT; original, measured, and calibrated s-parameters, with anticipated maximum and minimum, using 102, 103, and 104 samples...............................................................................................................................81
6-1 Comparing single-ended and mixed-mode s-parameters between passive balun and active balun ........................................................................................................................83
6-2 Distributed amplifier type active balun..............................................................................84
6-3 Differential amplifier type active balun.............................................................................85
6-4 Active balun using source-drain output configuration.......................................................86
6-5 Matched source-follower for maximum forward-gain at low frequencies ........................86
6-6 Simplified AC-equivalent circuit of the active balun using source-drain output configuration ......................................................................................................................87
6-7 Active balun using common-source and common-gate pair..............................................88
6-8 Proposed active balun using combined cascode-cascade configuration (C3-balun) .........89
6-9 Simulation results of the proposed C3-balun.....................................................................90
6-10 Chip layout of the proposed C3-blaun in IBM 8HP 130 nm BiCMOS process ................91
6-11 Chip photo of the proposed C3-blaun in IBM 8HP 130 nm BiCMOS process.................92
6-12 Layout for NMOS interconnect; M3 of the proposed C3-balun ........................................92
6-13 Layout for NMOS interconnect; zoom-in area of Figure 6-12 ..........................................93
6-14 Layout for NMOS interconnect; zoom-in area of Figure 6-13 ..........................................93
6-15 Three-pin DC-probe with embedded bypass capacitors ....................................................94
6-16 Using GSG’s “through” pattern for unknown-through measurements..............................95
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6-17 Full 3 x 3 s-parameter and y-parameter matrices of active balun with pads, pads only, and active balun without pads............................................................................................96
6-18 Measured magnitude of the single-ended s-parameters of the proposed C3-balun at the input power of -25 dBm...............................................................................................98
6-19 Measured phase of the single-ended s-parameters of the proposed C3-balun at the input power of -25 dBm.....................................................................................................98
6-20 Mixed-mode s-parameter measurement of the proposed C3-balun at -25 dBm input.......99
6-21 Mixed-mode s-parameter measurement of the proposed C3-balun at 5 dBm input ..........99
6-22 Noise measurement of the proposed C3-balun ................................................................100
6-23 C3-balun with network for stable biasing........................................................................102
6-24 Low frequency amplifier used for low-pass bias-feedback network in the proposed C3-balun...........................................................................................................................103
6-25 Threshold-referenced self-biasing network used in the proposed C3-balun and the attached low-pass bias-feedback network........................................................................103
6-26 Overall performances of the C3-balun the attached biasing network..............................104
7-1 Proposed balun embedded measurement for differential circuits....................................106
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
BROADBAND BALUN EMBEDDED MEASUREMENT
FOR DIFFERENTIAL CIRCUITS
By
Kooho Jung
December 2007 Chair: William R. Eisenstadt Cochair: Robert M. Fox Major: Electrical and Computer Engineering
Conventional 2-port vector-network-analyzers are used for measuring 4-port differential
circuits, where each port is embedded with a balun, either using external baluns, on-chip baluns,
or baluns integrated in on-wafer probes. The proposed strategy requires the development of
compact sized broadband baluns, an algorithm for calibrating the parasitic effects of the
embedded baluns, and an evaluation method for the measurement errors caused by the balun’s
imperfections. The proposed strategy can be applied to virtually all single-ended equipment,
which enables them to be free from post measurement processes for estimating virtual-
differential measurement results.
The baluns are realized using Marchand’s configuration given their large relative-
bandwidth and compact structure. The optimum values for the differential- and common-mode
characteristic impedances of the Marchand-coupling are analytically derived as 58.58 Ω and
85.36 Ω, respectively. In order to obtain such high coupling, a new coupling structure is
proposed using a double-sided single-layer printed-circuit-board surrounded by conductive
fixtures. The designed baluns are assembled to on-wafer probes, and the measurements results
show that the balun embedded probes have broad 3 dB-relative-bandwidths of 0.909.
14
For characterizing and calibrating the 3-port error-box in the balun embedded on-wafer
measurements, a new set of impedance-standard-substrate and an extraction algorithm are
proposed. This method fully extracts all 9 mixed-mode s-parameters of the 3-port error-box,
where 4 differential-modes are used for the calibration, and the remaining 5 common- and cross-
modes are used for evaluating their associated measurement errors. The proposed method uses
the pseudo-inverse of over-determined matrices, by which it becomes more tolerant to
measurement errors, when compared to a previous method of using a dual-through pattern
connected to a dual-probe.
Since the calibrations are for only the differential-modes, measurement errors occur due
to the undesired common- and cross-modes of the embedded baluns and device-under-test, even
under the most ideal calibration conditions. These errors are evaluated using a newly proposed
algorithm, which calculates the anticipated minimum and maximum of the s-parameters that can
result due to the common- and cross-modes.
In efforts to further increase the measurement bandwidth of the proposed measurement
strategy, active baluns are developed using a newly proposed combined-cascode-cascade
configuration, which is designed in the IBM 8HP 130 nm BiCMOS process. For input power as
high as 5 dBm, the bandwidth is shown to be DC - 17 GHz, where the imbalance of the
differential output is less than 1.8 dB in amplitude and less then 10 degrees in phase. With the
development of a calibration algorithm for unidirectional error-networks, active baluns become a
promising solution for the proposed balun-based measurements, due to their large bandwidth and
compact structure.
15
CHAPTER 1 INTRODUCTION TO BALUN EMBEDDED MEASUREMENTS
1.1 Advantages of Differential Circuits
Differential signals are defined as two signals with the same strength and opposite
polarities. Differential circuits are defined as networks which use differential signals for their
inputs and outputs. The key advantage of using differential circuits, compared to using single-
ended circuits (networks with single-ended signals as their inputs and outputs) is the fundamental
balanced characteristics by which one can minimize the flow of undesired energy transferring to
and from the system, such as electromagnetic interference/compatibility (EMI/ EMC) and
fluctuations of voltage-biases including ground (GND). Another advantage of using differential
circuits is the rejection of even harmonics caused by the circuits’ non-linearity of large-single
responses, because the even harmonics are in phase at each port of the differential output, from
which they are cancelled out when observing the difference between the two ports. These key
advantages of differential circuits enable them to be applied to a wide range of high-speed RF
applications, where recent advances are reported in areas such as power amplifiers [1.1],
frequency doublers [1.2], and distributed amplifiers [1.3].
A B C Figure 1-1. Circuits in their various types. A) Single-ended. B) Differential. C) GND-less
differential.
A further advantage of using differential circuits is in regards to the GND. In a signal-
ended circuit, as shown in Figure 1-1A, the circuit’s node-potentials are assumed to be
16
referenced to the underlying GND plane. However, such an assumption is only possible, when
the shortest wavelength of the signal traveling in the circuit is much longer than the dimensions
of the GND plane. Any distant two points on the GND plane, if the resulting electrical path is
comparable to the signal’s wavelength, cannot be modeled as the same node. Therefore, at high
frequencies, the various locations in the underlying GND plane cannot be treated as the actual
GND sharing the same node. Such uncertainty of the GND’s model can cause critical design
errors, which often create difficult modeling challenges. However, the problems caused by the
GND’s uncertainty are less severe for a differential circuit, as shown in Figure 1-1B. This is
because the balanced signals can make virtual-GND nodes (nodes that behave like GND for AC
signals) in local points inside the circuit, which are not influenced by the uncertainty of the
underlying GND plane. Furthermore, the problem caused by the GND’s uncertainty can be
solved completely by using GND-less differential circuit [1.4], as shown in Figure 1-1C, where
the two balanced signals are referenced to each other rather than to GND.
1.2 Conventional Measurements of Differential Circuits
In measuring a differential circuit, or a differential device-under-test (DUT), the most
convenient method is to use a 4-port vector-network-analyzer (VNA) with balanced differential
sources and receivers [1.5]. However, due to the high cost of new test equipment, a more
practical approach is sought utilizing 2-port VNAs, which are available in most laboratories for
RF circuits. The most common measurement method for utilizing the 2-port VNA is to terminate
(connect to a 50 Ω load) two of the four ports, and calibrate and measure the non-terminated
ports. As shown in Figure 1-2, six combinations of such 2-port calibration and measurement are
required, and the measurement results are mathematically combined to characterize the DUT’s
differential operations. However, this method requires long measurement cycles, and the
17
connecting and disconnecting of the ports between each measurement compromises the
measurement accuracy. The most critical problem occurs when measuring active differential
circuits, because their non-linear large-signal responses cannot be characterized by superposing
the six measurements.
Figure 1-2. Conventional method for measuring a differential circuit using a 2-port VNA.
Advanced solutions for the non-linear behavior are proposed in [1.6][1.7] using a pure-
mode VNA (PMVNA), where the 2-port VNA is connected to 3 dB hybrid-junctions that convert
the two single-ended signals to and from their difference (differential-mode) and their average
(common-mode). The 3 dB hybrid-junctions are further connected to switches for choosing
between differential-mode and common-mode, and phase-shifters for compensating any
mismatched delays in the interconnections between the connected parts. In the PMVNA, all of
the mentioned parts are connected to a PC through the GPIB (General Purpose Interface Bus) for
central controls. Although this method can provide a complete solution for measuring differential
circuits, the method requires sophisticated engineering expertise in the measurement setup and in
correctly interpreting the measurement results.
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1.3 Proposed Measurements of Differential Circuits Using Broadband Baluns
In efforts to efficiently measure differential circuits while avoiding the engineering
overhead mentioned in [1.6][1.7], a new method is proposed using baluns that focuses on
measuring the differential-mode. A balun is a 3-port network that converts between balanced
differential signals (“bal”) and unbalanced single-ended signals (“un”); the detail descriptions of
its basic operations are presented in Chapter 2. By using baluns operating over a wide frequency
range, the differential-mode of a differential circuit can be measured efficiently, as shown in
Figure 1-3; the baluns are embedded into the measurements, either using external baluns (Figure
1-3A for coaxial interfaced DUT and Figure 1-3B for on-wafer DUT) or using compacted sized
baluns embedded in the on-wafer probes (Figure 1-3C). Note, by embedding the baluns on the
probes, one can avoid the changes in the electrical lengths and contact resistances of the
connectors when maneuvering the probes between the calibration and the measurements. The
proposed measurement method requires the development of the items shown below, which are
the main topics of this work.
• Compact sized broadband baluns (for the case shown in Figure 1-3C) • An algorithm for calibrating the effects of the embedded baluns • Evaluation of measurements errors cause by the balun’s imperfections
The compact sized broadband balun is shown in Chapter 3, which is realized using
Marchand’s configuration [1.8]. The new algorithms for characterizing and calibrating the
effects of the baluns and evaluating the errors cause by balun’s imperfections are respectively
shown in Chapters 4 and 5. Active baluns are shown in Chapter 6, which are unidirectional
converters between differential and single-ended signals. Despite their inability to convert bi-
directionally, they are used because they can realize broad bandwidth in limited areas, which is
beyond what passive baluns can provide. With the development of a calibration algorithm for
19
unidirectional error-networks, this becomes a promising solution for the proposed strategy shown
in Figure 1-3C.
A
B
C
Figure 1-3. Balun embedded measurements. A) Using external baluns. B) Using external baluns connected to on-wafer probes. C) Using balun embedded probes.
1.4 Applications Beyond Network-Analyzers
The potential of the proposed measurement strategy need not be confined to VNAs. It can
be applied to virtually all single-ended equipment operating in the frequency domain (such as
signal generators and spectrum analyzers), so that they can be used for differential measurements.
This enables the measurements to be free from post measurement processes and mathematical
20
calculations for achieving virtual-differential measurement results. The broadband balun
components developed in this work can also be used for other embedded test applications, such
as on device-interface boards (DIB), IC-chips (for active baluns), and load boards for automated
test equipment (ATE). The compact size of the active baluns make them especially suitable for
Built-in Self Test (BIST) applications [1.9]-[1.11], as well as for general on-chip differential
circuits requiring compact sized broadband baluns.
21
CHAPTER 2 BACKGROUND THEORIES IN BALUNS AND MIXED-MODES S-PARAMETERS
2.1 Introduction Mixed-Mode S-Parameters
The s-parameter matrix ([s]) is generally used to represent multi-ported networks
operating in the RF/microwave range, as shown in Figure 2-1 for 4-port and 3-port circuits. The
scattering waves (or power waves) [2.1][2.2], labeled as a’s and b’s, are defined as the square-
root of the power of each ports (P1 ~ P4) propagating toward and away from the network,
respectively. The ratios of these power-waves define the single-ended s-parameter matrix, as
shown in Equation 2-1 for 4-port circuits and in Equation 2-2 for 3-port circuits. The elements of
the s-parameter matrix are used to define the network’s operation, such as the gain from P1 to P3,
s31, or the reflections at P2, s22.
A
B
Figure 2-1. Nodal scattering-wave representation of A) three-port circuit and B) four-port circuit.
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22
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differential ports ΔP1 (P1 and P2), ΔP2 (P3 and P4 of 4-port network), and ΣP2 (P3 of 3- port
network), mixed- mode (differential-mode and common-mode) scattering waves are used as
shown in Figure 2-2 and Equations 2-3 and 2-4 [2.3][2.4]. The subscripts d and c in the power-
waves and s-parameters represent the differential-mode and the common-mode. In Equations A-
3 and A-4, the differential-modes and common-mode s-parameters are grouped together, and the
ungrouped s-parameters are the cross-modes.
A
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Figure 2-2. Mixed-mode scattering-wave representation of A) three-port circuit and B) four-port circuit.
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23
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⎝
⎛=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
1
2
1
3
1
2
1
111211
212221
111211
1
2
1
c
s
d
c
s
d
cccscd
scsssd
dcdsdd
c
s
d
aaa
aaa
sssssssss
bbb
s (2-4)
Mixed-mode power-waves are defined with mixed-mode voltages and currents. Consider
ΔP1 (P1 and P2) shown in Figure 2-2 (and Figure 2-1). The mixed-mode voltages and currents
are defined in Equation 2-5, and their decomposition with respect to their propagation direction
is shown in Equation 2-6, which is in the same format as the single-ended representation shown
in Equation 2-7. The superscripts “ + ” and “ − ” correspond to waves propagating “towards” and
“away from” the network, respectively. Each decomposed term shown in Equation 2-6 also
follows the same definitions in Equation 2-5. The asymmetry with the factor of 1/2 in Equation
2-5 was chosen for power conservation [2.3][2.4], which results in the different characteristic
impedances for differential-mode and common-mode, as shown in Equations 2-8 through
Equation 2-10. Definitions presented in Equations 2-5 through 2-10 also apply for ΔP2 in the
same way. The mixed-mode voltages and currents define the mixed-mode scattering-waves as
shown in Equations 2-11 and 2-12, which is in the same format as the single-ended
representation shown in Equations 2-13 and 2-14. Finally, the ratios of these mixed-mode
scattering waves define the mixed-mode s-parameters matrix, [Δs], as introduced in Equations 2-
3 and 2-4. Note, for the 3-port case, the single-ended port is represented by “s”. Therefore, the
single-ended port ΣP2 is the same as P3, hence, vs2, is2 , as2
, and bs2 are respectively same as v3, i3,
a3, and b3.
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
2
1
2
1
1
1
1
1
11002/12/100
002/12/10011
iivv
iivv
c
d
c
d
(2-5)
differential-mode
common-mode
24
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
+
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
−
−
+
+
+
+
1
1
1
1
1
1
1
1
1
1
1
1
c
d
c
d
c
d
c
d
c
d
c
d
iivv
iivv
iivv
(2-6)
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
+
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
−
−
+
+
+
+
2
1
2
1
2
1
2
1
2
1
2
1
iivv
iivv
iivv
(2-7)
−−++−−++ −==−=≡ 222211110 //// ivivivivz (2-8)
011110 2// zivivz ddddd ⋅=−=≡ −−++ (2-9)
2/// 011110 zivivz ccccc =−=≡ −−++ (2-10)
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅
⋅
⋅
⋅
≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
+
+
+
+
+
+
+
+
++
++
++
++
cc
dd
cc
dd
cc
dd
cc
dd
cc
dd
cc
dd
c
d
c
d
zizizizi
zvzvzvzv
iviviviv
aaaa
02
02
01
01
02
02
01
01
22
22
11
11
2
2
1
1
////
(2-11)
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅
⋅
⋅
⋅
≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
−
−
−
−
−
−
−−
−−
−−
−−
cc
dd
cc
dd
cc
dd
cc
dd
cc
dd
cc
dd
c
d
c
d
zizizizi
zvzvzvzv
iviviviv
bbbb
02
02
01
01
02
02
01
01
22
22
11
11
2
2
1
1
////
(2-12)
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅
⋅
⋅
⋅
≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
+
+
+
+
+
+
+
+
++
++
++
++
04
03
02
01
04
03
02
01
54
33
22
11
4
3
2
1
////
zizizizi
zvzvzvzv
iviviviv
aaaa
(2-13)
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅
⋅
⋅
⋅
≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
−
−
−
−
−
−
−−
−−
−−
−−
04
03
02
01
04
03
02
01
54
33
22
11
4
3
2
1
////
zizizizi
zvzvzvzv
iviviviv
bbbb
(2-14)
25
2.2 Mixed-Mode S-parameter Calculation Using SPICE
In order to obtain simulations of [Δs], an IC designer would first obtain [s] via a
microwave-circuit simulator, and then convert it into [Δs], through linear matrix-operations [2.3].
The problem occurs when the circuits are entered in SPICE, where a circuit’s schematic cannot
be re-entered on a microwave-circuit simulator for fear of making fatal translation errors. Some
linking programs exist to transfer files between microwave design tools and IC CAD systems,
but these require technology support, additional installed software, and sophisticated user
capability. Another disadvantage is that the relationships between the extracted [s] and the
circuits operation (node-voltages and branch-currents) are not traceable. The linear matrix
operation in converting [s] into [Δs] further hides [Δs]’s relationship to the circuit’s operation.
Furthermore, transient simulations of the mixed-mode s-parameters for monitoring non-linearity
as well as the stability are not available using this conventional method. To overcome these
problems, a new way to directly extract mixed-mode s-parameters from SPICE for 4-port and 3-
port circuits is shown in this section, which is an extension from the previous work for single-
ended 2-port networks presented by [2.2] and [2.5].
2.2.1 Extraction Circuits for Mixed-Mode S-parameters
The analysis for building the attached extraction circuits starts with decomposing the
ports’ nodal voltages in terms of their propagation directions as shown in Figure 2-3A. This is a
2-port circuit, where the source of vA is applied to PS and the load is connected to PL, through
transmission-lines both matched with z0. The propagation-loss and phase-shifting effects of the
transmission lines are assumed to be calibrated out. For the source port, one-half of the applied
voltage propagates towards PS (vS+=vA/2) due to a voltage division occurring between the source-
impedance and the transmission-line’s characteristic impedance. The total nodal voltage vS must
26
A
B
Figure 2-3. Decomposing nodal voltages in terms of propagation direction. A) Transmission-line model. B) SPICE model.
equal the sum of vS+ and vS
-; hence, vS-= vS -vA/2. For the load port, where no waves are injected
towards PL (vL+=0), vL
- is equal to vL. Keeping in mind this decomposition, Figure 2-3A can be
converted into Figure 2-3B where the transmission lines are replaced by their Thevenin-
equivalent circuit seen at STh and LTh.
The extraction of [Δs]4’s 1st column starts from the definition stated in Equation 2-3,
where only the differential-mode wave is injected at ΔP1 while rest of the incident waves remain
zero. This is achieved by applying unit voltages with opposite polarity at ΔP1. Using the
Thevenin-equivalent circuits shown in Figure 2-3, this is modeled as Figure 2-4A. The equation
of [Δs]4’s 1st column is shown in Equation 2-15. Each element begins with its definition, which
is expressed in terms of v+1,2 and v-
1~4. These terms are replaced by v1~4, via the same
decomposition analysis shown in Figure 2-3. The final expression of Equation 2-15 can be
27
realized by the attached circuitry as shown in Figure 2-4A. Voltages v1~4, control the dependent
sources of the attached circuits, which are arranged in accordance with the final term of Equation
2-15 to generate the outputs sdd11, sdd21, scd11, and scd21, which are node voltages interpreted as
dimensionless quantities. By applying unit voltages with the same polarity, the elements of
[Δs]4’s third column can be extracted using a similar procedure. These results are shown in
Equation 2-16 and in Figure 2-4B.
A
B
Figure 2-4. Extraction circuit for [Δs]4. A) First column. B) Third column.
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
++−
−−
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
++−−
⋅−
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−−
−−
−−
−−
++
−
−
−
−
+
43
21
43
21
43
21
43
21
21
02
01
02
01
01
21
11
21
11 11
////
/1
vvvvvv
vv
vvvvvvvv
vv
zvzvzvzv
zvssss
cc
cc
dd
dd
dd
cd
cd
dd
dd
(2-15)
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
+−+
−−
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
−
−
+
43
21
43
21
02
01
02
01
01
21
11
21
11
1
////
/1
vvvv
vvvv
zvzvzvzv
zvssss
cc
cc
dd
dd
cc
cc
cc
dc
dc
(2-16)
The extraction circuits for elements of the [Δs]4’s 2nd and 4th columns can be achieved
by switching the two differential ports, ΔP1 (P1 and P2) and ΔP2 (P1 and P3), followed by the
28
same procedure, as shown in Equations 2-17 and 2-18. The final terms of these equations can be
realized in circuits as shown in Figure 2-5. The extraction circuits for extracting elements of
[Δs]3 are also done in the same way as that of [Δs]4. The derivation procedure for extracting
elements of [Δs]3 are shown in Equations 2-19 through 2-21, and the resulting extraction circuits
are shown in Figure 2-6.
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
++
−−−
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
−
−
+
43
21
43
21
02
01
02
01
02
22
12
22
12
1
////
/1
vvvv
vvvv
zvzvzvzv
zvssss
cc
cc
dd
dd
dd
cd
cd
dd
dd
(2-17)
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−++−−
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−
−
−
+
1////
/1
43
21
43
21
02
01
02
01
02
22
12
22
12
vvvvvvvv
zvzvzvzv
zvssss
cc
cc
dd
dd
cc
cc
cc
dc
dc
(2-18)
A
B
Figure 2-5. Extraction circuit for [Δs]4. A) Second column. C) Fourth column.
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
+⋅
−−=
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
⋅≡⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
−
−
−
+
21
3
21
01
03
01
0111
21
11
21
///
/1
vvv
vv
zvzvzv
zvsss
cc
dd
ddcd
sd
dd
(2-19)
29
( )
( )⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
+⋅−⋅−⋅
=⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
⋅≡⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
−
−
−
+
21
3
21
01
03
01
0312
22
12
212
2
///
/1
vvv
vv
zvzvzv
zvsss
cc
dd
cs
ss
ds
(2-20)
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
−+⋅
−=
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
⋅≡⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
−
−
−
+
12
///
/1
21
3
21
01
03
01
0111
21
11
vvvvv
zvzvzv
zvsss
cc
dd
cccc
sc
dc
(2-21)
A
B
C Figure 2-6. Extraction circuit for [Δs]3. A) First column. B) Second column. C) Third column.
2.2.2 Application Examples
The mixed-mode s-parameters are extracted with the proposed SPICE-based method and
they are compared with the results obtained from Agilent ADS, followed by linear matrix
operations shown in Equations 2-22 and 2-23 for 4-port and Equations 2-24 and 2-25 for 3-port,
which can be derived from definitions shown in Section 2.2.1. The extractions are done for a 5
30
GHz CMOS fully-differential amplifier, and also for a differential transformer (adapted from
[2.6]) with unbalanced coupling of a nearby conductive loop.
[ ] [ ]⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
−⋅⋅
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛−
−
⋅=Δ
1010101001010101
110000111100
0011
21
44 ss (2-22)
[ ]
⎟⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
++++++−+−−+−
++++++−+−−+−
−−+−−++−−+−−
−−+−−++−−+−−
=
2222
2222
2222
2222
44433433424132314443343342413231
24231413222112112423141322211211
44433433424132314443343342413231
24231413222112112423141322211211
4
ssssssssssssssss
ssssssssssssssss
ssssssssssssssss
ssssssssssssssssΔs
(2-23)
[ ] [ ]⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛−⋅⋅
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛ −⋅=Δ
020101101
011200
011
21
33 ss (2-24)
[ ]
⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
++++−+−
+−
−−+−+−−
=
222
22
222
22211211231322211211
323133
3231
22211211231322211211
3
ssssssssss
sss
ss
ssssssssss
Δs (2-25)
The circuit diagram of the fully-differential amplifier is shown in Figure 2-7. All of the
inductances (and the transformers) include a series resistance to account for a finite Q of 10, and
the current source is replaced by a CMOS current mirror. The first stage (MP1 and MP2) is a
differential common-source configuration with LC-resonator loads to achieve high drain
impedance, and hence, achieve high gain. The second stage (M1 and M2) also uses common-
source configuration with LC-resonators, where the LC-resonators also work as impedance
31
matching networks to achieve output resistances of 50 Ω. The input matching circuits attached in
P1 and P2 are designed using LC-networks. To achieve high common- and cross-modes, the
authors deliberately made the size and current carrying capabilities of the CMOS asymmetric via
the CMOS NFET model - Kp parameters (0.02 mA/V2 for MP1 and M1, and 0.022 mA/V2 for
MP2 and M2).
The magnitude of the extracted mixed-mode s-parameters are shown in Figure 2-8. The
solid lines are obtained via this new method (using SPICE), and the dotted lines are obtained by
microwave circuit simulation and the mixed-mode matrix conversion operation. Both results
show almost identical responses, with a slight difference due to the different MOS models (as
well as parasitic models) between SPICE and the microwave simulator. The other elements of
[Δs]4 which are not shown here, have magnitudes lower than -60 dB, and were unsuitable to
compare due to the noise of the numerical simulation errors.
Figure 2-7. Two-staged 5GHz CMOS fully-differential amplifier; CMOS NFET model Kp
parameters are 0.020 mA/V2 for MP1 and M1, and 0.020 mA/V2 for MP2 and M2; all L includes series resistance to achieve finite Q of 10.
32
Figure 2-8. SPICE-based extraction of [Δs]4 for the circuit shown in Figure 2-8.
The layout and the circuit diagram for the fully-differential transformer (4-port) and a
differential to single-ended transformer (3-port) are shown in Figures 2-9 and 2-10. Note, P4
remains open in the 4-port case, and P4 is shorted to ground for 3-port case. The inductance of
the metal path P1-to-P2 (black) and P3-to-P4 (gray) are respectively 0.5 nH and 0.3 nH, and the
coupling coefficient between these two inductances is 0.8. The transformer is unbalanced by the
asymmetrical coupling of a nearby inductance of 0.2 nH (white), where the coupling-coefficients
to the upper spiral structure (k) is 5 times larger than that of the lower spiral structure (k'). The
resistances associated with the inductance account for the finite Q of 10 at 5 GHz, and the
parasitic capacitances are omitted for simplicity.
As shown in Figures 2-11 through 2-14, the SPICE-based extractions are identical to
those obtained via ADS, both in magnitude and in phase, which prove that the proposed method
is accurate and free from any approximation or assumption. The elements of [Δs]4 and [Δs]3 that
33
are not shown in Figures 2-11 through 2-14 are the ones with the magnitudes smaller than -120
dB, where the simulation’s numerical errors became predominant.
Figure 2-9. Layout of a differential transformer with unbalanced coupling of a nearby loop.
Figure 2-10. Circuit model of a differential transformer shown in Figure 2-9.
34
Figure 2-11. SPICE-based magnitude extraction of [Δs]4 for the circuit shown in Figure 2-10 (4-
port case).
Figure 2-12. SPICE-based phase extraction of [Δs]4 for the circuit shown in Figure 2-10 (4-port
case).
35
Figure 2-13. SPICE-based magnitude extraction of [Δs]3 for the circuit shown in Figure 2-10 (3-
port case).
Figure 2-14. SPICE-based phase extraction of [Δs]3 for the circuit shown in Figure 2-10 (3-port
case).
36
2.3 Introduction to Balun and Relative-Bandwidth
A balun is 3-port network, as shown in Figure 2-1B, which converts between balanced
differential signals (“bal”) and unbalanced single-ended signals (“un”). As shown in Equation 2-
26, an ideal balun is defined as a 3-port network where s13 (= s31) and s23 (= s32) are both
1/sqrt(2) with opposite polarities (180º difference in phase), while all other single-ended s-
parameters are zero. Such a single-ended s-parameter matrix means that the single-ended signal
in P3 splits its power into (or combines its power from) P1 and P2 with opposite polarities, while
all ports do not reflect any powers and maintains perfect isolation between P1 and P2. The same
balun can be represented using a mixed-mode 3-port network, as shown in Figure 2-2B. As
shown in Equation 2-27, an ideal balun is defined as a 3-port network where sds12 (= ssd21) is 1,
while all other undesired mixed-mode s-parameters are zero. Such a mixed-mode s-parameter
matrix means that the single-ended signal in P3 completely transfers its power to (and receives
its power from) ΔP1 in its differential-mode, while all other transfers and reflections are zero.
o180 ; 022
200200
21
2
1
1
12
11
1
333231
232221
131211
=−
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
∠∠
∠
∠
=⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
−−
−
−
θθθθ
θθ
sssssssss
(2-26)
000001010
111211
212221
111211
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
cccscd
scsssd
dcdsdd
sssssssss
(2-27)
The frequency behavior of a balun is often characterized by using a figure of merit called
the relative-bandwidth. Its definition is shown using Figure 2-15, which is a frequency response
of an example balun (Rat-race balun [2.7]) operating with the center frequency of 6 GHz. At 6
GHz, the single-ended s-parameters (Figure 2-15A) show that it transmits with -3 dB loss
through s13 (= s31) and s23 (= s32) with opposite polarities of 180°, while the other undesired
37
single-ended s-parameters are very low. Figure 2-15B shows the same balun in mixed-mode s-
parameters, where at 6 GHz, the differential transmission of sds12 (= ssd21) is 0 dB, while the other
undesired mixed-mode s-parameters are very low. However, these undesired s-parameters
increase as the frequency approaches the sidebands, towards 3 GHz and 9 GHz, where the balun
no longer operates ideally.
A
B
Figure 2-15. Rat-race balun operating at 6 GHz. A) Single-ended. B) Mixed-mode.
As shown in Figure 2-15B, absolute-bandwidth (BW) of a balun can be defined using
“Δ”, which denotes the minimum required difference between sds12 (= ssd21) and all other
undesired s-parameters. In this work, absolute-bandwidth is defined by using Δ = -3 dB, and the
38
relative-bandwidth is defined by normalizing the absolute-bandwidth by its center frequency, as
shown in Equation 2-28. This figure of merit is often convenient when characterizing baluns that
are realized using passive components, such as coupled microstrip transmission-lines (TL) or
transformers using coiled ferrites, since this maintains its value regardless of the change of center
frequency via structural scaling; if the used materials’ electromagnetic performances are
maintained through the change of frequencies, the center frequency can be increased (or
decreased) by scaling down (or scaling up) the structural dimensions.
717.0GHz 6
GHz 85.3GHz 15.8frequencycenter
bandwidth-absolute bandwidth-relative ≅−
=≡ (2-28)
From various types of baluns, the planar-type Marchand balun [2.8][2.9] is chosen in this
work, for its area-efficient structure and its capability to produce large relative-bandwidths
compared to other balun types such as the lumped delay type [2.10] or the Rat-race type [2.7].
The detail operation of Marchand baluns and their applications to balun embedded measurements
are shown in the next chapter.
39
CHAPTER 3 MARCHAND BALUN EMBEDDED PROBE
3.1 Introduction to Marchand Balun Embedded Probe
Baluns are embedded into on-wafer probes in order to provide accurate differential
measurement capabilities for conventional single-ended two-port VNAs, as shown in Figure 1-
3C. From various types of baluns, the planar Marchand balun is chosen in this research, for its
area-efficient structure and its capability to produce large relative-bandwidths compared to other
balun types of passive baluns. The review of coaxial Marchand Balun [1.8] and its migration to
the planar type is shown in Section 3.2. The analytical derivation procedure for designing the
optimum planar-type Marchand balun and the newly proposed Marchand-coupling structures are
respectively presented in Sections 3.3 and 3.4. The final measurement results are discussed in
Section 3.5.
3.2 Coaxial Marchand Balun and the Migration to its Planar Type
A cross-sectional view of a general coaxial cable is shown in Figure 3-1. Although this
has only two conductors, it has three current components as annotated as I_center, I_outer, and
I_shield, where I_center is always equal to I_outer with opposite directions. Using coaxial
transmission-lines (TL), the original Marchand balun can be designed as shown in Figure 3-2,
along with its cross-sectional view. It uses double-coax structures, where the inner coaxes have
the characteristic impedances of za (at the left-hand side) and ze (at the right-hand side) and the
outer coaxes have the characteristic impedance of zb. The I_center and I_outer of the za-coax
share the same values but are in opposite directions. The goal is to couple these currents into the
two center conductors of the z0-coaxes located at the bottom. However, the problem is that in the
za-coax, the current in the outer conductor’s inner-part (I_outer) is connected to its outer-part
(I_shield) at any cut interfaces. Hence, this I_outer couples into I_center of the zb-coax. As
40
Figure 3-1. Cross-sectional view of a coaxial cable and its currents.
A
B
Figure 3-2. Coaxial Marchand balun. A) 3-D view. B) Cross-sectional view.
41
shown in the remainder of this section, the λc/4-length (where, λc is the wave-length of the center
frequency of fc) of the zb-coax and the series open-ended ze-coax enables these undesired
coupling to be cancelled out over a wide range of frequency.
Figure 3-3 is the TL model of the Marchand balun, where the conductive bodies, labeled
as A ~ Q, can be compared with labels shown in Figure 3-2. The TL model shows that signals at
P1 and P2 always have opposite polarity. Furthermore, since this is a passive-lossless network,
the matching of the differential port, P1 and P2, to 100 Ω enables the single-ended port, P3, to be
matched to 50 Ω. Therefore, the bandwidth of the impedance seen at the differential port can be
directly translated as the bandwidth in which the Marchand balun operates. Figure 3-4 shows the
equivalent circuit for calculating the differential-mode impedance seen at the differential port, zD,
which is 2 times the value of the displayed zodd, as shown in Equation 3-1. This factor of 2 is due
to the definitions of differential-mode currents and voltages, which is shown in the Equation 2-5.
The equivalent lumped elements zX, zY, and zZ, are the impedances of the shorted λc/4-stub of zb-
coax (Equation 3-2), 50 Ω terminated za-coax, and the opened λc/4-stub of ze-coax (Equation 3-
3), respectively, where θ is the normalized frequency as shown in Equation 3-4. By assuming za
= 50 Ω (hence, zY = 50 Ω), one can derive the matching condition of zD = 100 Ω, which is ze =
za2/(2zb). Note that the differential-mode impedance, zD, tends to maintain a constant value over
a wide range of θ, because the variation caused by the “tanθ ” term of the shorted λc/4-stub (zX)
and variation caused by the “cotθ ” term of the opened λc/4-stub (zZ) tends to cancel each other,
as shown in Figure 3-5. The flatness increases for higher zb. However, if zb is too large (beyond
200 Ω) the shorted λc/4-stub could no longer be modeled as Equation 3-2, because of the
increasing dimensions of the outer coax, where the propagation can no longer be treated as
purely transverse-electromagnetic (TEM) mode.
42
Figure 3-3. Transmission-line model of Marchand balun.
Figure 3-4. Equivalent circuit for the impedance seen at Marchand balun’s differential port.
( ) ( ) ||222 ZYXoddD zzzzz +⋅⋅=⋅= (3-1)
θtan⋅⋅= bX zjz (3-2)
θcot2
20 ⋅
⋅⋅−=
bZ z
zjz (3-3)
cc
c
velocity-phase ; 2 λπθ =⋅≡ f
ff (3-4)
43
A
B Figure 3-5. Normalized frequency plot of the differential-mode impedance seen at Marchand
balun’s differential port. A) Real value of zD. B) Imaginary value of zD.
Although the double-coax typed Marchand balun provides convenient theoretical designs,
there are critical challenges with respect to the actual manufacture and assembly process. So it is
often practical to realize the concept using planar TLs that can be created using printed-circuit-
board (PCB) or thin-film process. The basic circuit for such planar Marchand balun is shown in
Figure 3-6, where the single-ended port, P3, bi-directionally converts the signal transmitted to
and from the differential balanced ports, P1 and P2. At the center frequency of fc, the signal
entering the single-ended port, P3, goes into a coupled TL structure, and reaches plane “A” after
traveling λc/4, where the balanced signals can be achieved when given the correct amount of
44
coupling. However, in order to maintain the balance at the sidebands, zopen is connected in series
to P1 for phase compensation, which enables a broad 3 dB-relative-bandwidth of 1~1.3. Hence,
the Marchand-coupling consists of two λc /4 coupled TLs, where one is connected to the single-
ended port, P3, and the other one connected to an open-ended terminal. This Marchand-coupling
need not be symmetric where one λc /4 coupled TL is the exact mirror image of the other.
However, this work uses the symmetric type, because of the convenience in the manufacturing,
and also because it provides superior balance of the signals at P1 and P2, due to their symmetric
structure with respect to GND [3.1]-[3.3].
Figure 3-6. Planar-type Marchand balun.
For the planar-type Marchand balun, the manufacturing and assembly process are far
more convenient than that of the coaxial type, especially in high frequencies, where the
availability of the coaxial cables with the required characteristic impedances is limited. However,
the design and optimization aspect is more difficult compared to the coaxial type. This is
primarily because the design parameters of the previous double-coax, za and zb, which can be
chosen independently from each other, are now replaced by the coupled TL’s differential-mode
and common-mode characteristic impedances, z0d and z0, that are coupled to each other. The
comparative study between two approaches is listed in Table 3-1. To overcome these challenges
for designing planar Marchand baluns, a new optimization procedure is developed analytically as
shown in the next section.
45
Table 3-1. Using double-coax vs. using PCB coupled-TL in realizing Marchand-coupling Design Issues Double-Coax PCB Coupled-TL
characteristic impedances
za = va/ia zb = vb/ib
z0d = 2·(v1-v2)/ (i1-i2) z0c = 0.5·(v1+v2)/ (i1+i2)
analytical solutions
za,b = 59.9591·sqrt(μr/εr) x ln (radout/radin)
“none” need to use full-wave simulators
design standpoint
“convenient” za and zb are independent
“difficult” z0d and z0c are coupled
manufacture standpoint
“difficult” inconsistent dimensions medium
“convenient” custom PCB vendors
3.3 Analytical Derivation for Optimum Design
3.3.1 General Quarter-Wavelength Coupled TL
Designing a planar Marchand balun requires finding the optimum values for the
characteristic impedances of Marchand-coupled TL - z0d of the differential-mode and z0c of the
common-mode. This starts with characterizing a general λc/4 coupled TL, as shown in Figure 3-7,
where z2 ~ z3 are arbitrary terminal impedances. The goal here is to solve for the input impedance,
zin, at the center frequency, fc, which will be used as the central tool for finding the optimum
values of z0d and z0c.
As shown in Equation 3-5, the single-ended v’s in ports P1 and P3 can be written in terms
of differential-mode, vd0, and common-mode vc0, where they are split into their direction of
propagation (the superscript “+” denotes the component propagating towards P2 and P4, while
46
the superscript “–” denotes the component propagating towards P1 and P3). Similarly, Equation
3-6 shows the differential- and common-mode v’s at ports P2 and P4, where the terms ±j is to
account for the λc/4 propagation. From Equations 3-5 and 3-6, v1~4 can be written in terms of the
directional vd0’s and vc0’s as shown in Equation 3-7. The same can be is applied to the currents as
shown in Equations 3-8 through 3-10, where the characteristic impedances are defined in
Equation 3-11. Applying an AC 1V signal to the node v1, Kirchoff’s voltage-law gives the first
term of Equation 3-12. Its v1~4 and i1~4 can be replaced by the directional vd0’s and vc0’s, as
shown in the rest of Equation 3-12. From this equation, the directional vd0’s and vc0’s can be
solved using the inverse matrix of M. The results are inserted into Equation 3-7 and Equation 3-
10, by which the analytical form of v1~4 and i1~4 respectively obtained. Since the input is AC 1V,
the inverse of the current i1 becomes equal to input impedance as shown in Equation 3-13.
Figure 3-7. General λc/4 coupled transmission-line.
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛ −−
−
+
+
0
0
0
0
0
0
3
1
2/12/111
c
d
c
d
c
d
vv
vv
vv
vv
(3-5)
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛−=⎟⎟
⎠
⎞⎜⎜⎝
⎛⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛ −−
−
+
+
0
0
0
0
4
2
2/12/111
c
d
c
d
vv
jvv
jvv
(3-6)
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−−−−
−=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
+
−
+
0
0
0
0
4
3
2
1
2/2/112/12/1
2/2/112/12/1
c
c
d
d
vvvv
jjjj
jj-jj
vvvv
(3-7)
47
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛ −−
−
+
+
0
0
0
0
0
0
3
1
112/12/1
c
d
c
d
c
d
ii
ii
ii
ii
(3-8)
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛−=⎟⎟
⎠
⎞⎜⎜⎝
⎛⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛ −−
−
+
+
0
0
0
0
4
2
2/12/111
c
d
c
d
ii
jii
jii
(3-9)
( ) ( )( ) ( )( ) ( )( ) ( ) ⎟
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−−−−
−−
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−−−−
−=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
+
−
+
−
+
−
+
0
0
0
0
0000
0000
0000
0000
0
0
0
0
4
3
2
1
2/2///2/12/1/1/1
2/2///2/12/1/1/1
2/2/2/12/111
2/2/2/12/111
c
c
d
d
ccdd
ccdd
ccdd
ccdd
c
c
d
d
vvvv
zjzjzjzjzzzz
zjzjzjzjzzzz
iiii
jjjj
jj-jj
iiii
(3-10)
⎟⎟⎠
⎞⎜⎜⎝
⎛−=⎟⎟
⎠
⎞⎜⎜⎝
⎛≡⎟⎟
⎠
⎞⎜⎜⎝
⎛−−
−−
++
++
00
00
00
00
0
0
//
//
cc
dd
cc
dd
c
d
iviv
iviv
zz
(3-11)
⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛+−⎟⎟
⎠
⎞⎜⎜⎝
⎛−−⎟⎟
⎠
⎞⎜⎜⎝
⎛−
−++−−−
⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛+−⎟⎟
⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛+−
≡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⋅=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⇒
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−=−=−=
=
−
+
−
+
ccdd
ccdd
ccdd
c
c
d
d
zz
jzz
jzz
jzz
j
zz
zz
zz
zz
zz
jzz
jzz
jzz
j
vvvv
zivzivziv
v
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
0
0
0
444
333
222
1
21
21
21
21
21
21
21
21
21
21
21
21
1121
21
;
0001
0001
M
M
(3-12)
( )2
004
20
02423
20
023
20
0432
00
22
224
22
224
⎟⎠⎞
⎜⎝⎛ −+⎟
⎠⎞
⎜⎝⎛ ++
⎟⎠⎞
⎜⎝⎛ −+⎟
⎠⎞
⎜⎝⎛ ++
=d
cd
c
dc
dccd
inzzzzzzzzz
zzzzzzzzzzz (3-13)
48
3.3.2 Optimum Design for Planar Marchand Balun
The planar-type Marchand balun is shown again in Figure 3-8A, where the equivalent
impedances of the Marchand-coupling networks are defined as zeq1 and zeq2, as shown in the
equivalent circuit in Figure 3-8B. The impedances seen at various positions are labeled as zX, zY,
and zZ. For the balun to work ideally, the input signal at P3 must be delivered to a matched
impedance of zZ = 50 Ω. For balun to become lossless, half of this 50 Ω must be due to the
coupling to P1 and the other half must be due to the coupling to P2. Hence, the real part of zeq1
and zeq2 must both be equal to 25 Ω. However, Equation 3-13 indicates that zeq2 is purely real
(when assuming the z0d and z0c are also purely real). This also means zeq1 is purely real since zeq1
+ zeq2 must be equal to 50 Ω. Hence, zX = 25 Ω and zY = 75 Ω, where the additional 50 Ω in zY
comes from the source impedance at P3.
A
B Figure 3-8. Impedances of planar Marchand balun with symmetric λc/4 coupled TL. A) Original
circuit. B) Equivalent circuit using lumped impedances, zeq1 and zeq2.
49
Using Equation 3-13, zX and zY can be expressed in terms of z2~3, where the appropriate
values for z2~3 can be chosen by comparing the port numberings between Figure 3-7 and Figure
3-8A. The results are shown in Equations 3-14 and 3-15, from which the final the optimum
values for z0d and z0c are found, as shown in Equations 3-16. Note that in obtaining Equations 3-
16, the proper signs can be chosen using the physical fact that 2z0c is always greater than or equal
to z0d/2. Figure 3-9 shows the simulated s-parameters of the planar-type Marchand balun using
the optimum characteristic impedances shown in Equation 3-16.
( )( )
252/22/250
050 2
00
200
4
3
2
=+−
=⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
==
∞==
dc
dcinX zz
zz
zzz
zz (3-14)
( )( )
75252/250
4
05050
200
200
4
3
2
=++
=⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
===
=dc
cdinY zz
zz
zzz
zz (3-15)
( )( ) ⎟⎟
⎠
⎞⎜⎜⎝
⎛ΩΩ
≈⎟⎟⎠
⎞⎜⎜⎝
⎛
−+
=⎟⎟⎠
⎞⎜⎜⎝
⎛36.8558.58
2/11/252/11/100
0
0
c
d
zz
(3-16)
Figure 3-9. Simulation results of an optimized planar Marchand balun operating at fc = 6 GHz.
50
3.3.3 Common-Mode Matching
As shown in Figure 3-9, the Marchand balun offers a broadband matching at the
differential port, P1 and P2, for differential-mode, but it becomes an open circuit for common-
mode. This can be interpreted as poor isolation between P1 and P2. If the differential DUT has
any significant common- or cross-modes, any reflections of the unmatched common-modes of
the balun will result in measurement errors, even under the most accurate calibrated conditions.
Therefore, when the baluns are being used for testing differential DUTs, it is very
important for them to be matched in both the differential- and common-mode, in other words, P1
and P2 need to be well isolated. This is achieved by attaching 50 Ω resistors at P1 and P2 which
are looped with a 50 Ω half-wavelength TL [3.4], as shown in Figure 3-10. Due to the electrical
symmetry, the center point of the looped TL becomes a virtual-open for the common-mode and a
virtual-GND for the differential-mode, at the center frequency, fc. Therefore, when the signals
travel λc/4 towards the terminals of the attached resistors, they become virtual-GND for
common-mode and a virtual-open for differential-mode. As a result, the attached network
provides 50 Ω terminations at each port for the common-mode, while remaining transparent for
the differential-mode. Note that the same will not apply for the sidebands of the center frequency,
fc, resulting in a narrower 3 dB-relative-bandwidth, as will be shown in Section 3.5.
Figure 3-10. Planar Marchand balun with common-mode matching.
51
3.4 Structural Realization
The previous section showed that the optimized design for planar-type Marchand balun
required a very large coupling where z0d is low as 0.7 x z0c. This gives rise to new challenges in
the structural design of the coupled TL. The cross-sectional views of their various structures are
shown in Figure 3-11. Figure 3-11A is most commonly used [3.5], but its coupling is too small
where the z0d cannot be made as low as 0.7 x z0c. This can be solved by coupling on both sides
[3.6][3.7], as shown in Figure 3-11B. However, this requires bondwires, which degrades the
reproducibility with respect to manufacturing. Also, this makes it difficult to place and route the
Marchand-coupling while connecting the common-mode matching network. An alternative way
is to couple vertically [3.8], as shown in Figure 3-11C. This provides very large coupling where
there are virtually no limits to how small the z0d can be made with respect to z0c. However, a
critical problem is that the derived optimum z0d and z0c cannot be applied, because the two
coupled TL are asymmetric with respect to the GND.
A B C Figure 3-11. Cross-section of various coupled microstrip-TL structures.
In order to achieve large coupling between the two TL that are symmetric with respect to
the GND, a new coupled TL is proposed, where its cross-sectional view is shown in Figure 3-12.
It uses a double-sided single-layer PCB surrounded by conductive fixtures. Note that regardless
of the type of coupled TL, such conductive fixture is expected to inherently exist, for EMI
protection and for the structural robustness in preparation for the final assembly to the probe.
Large coupling can be easily achieved in this structure, because the majority of the
52
electromagnetic field propagates inside the PCB’s substrate of high dielectric constant (εr = 2 ~
4) for differential-mode, while that of the common-mode propagates in air (εr = 1). However,
since the phase-velocities of the differential and common-mode are no longer the same, as was
the case in Section 3.3.1, it requires further structural tuning from its nominal values that had
produced the characteristic-impedances presented in Equation 3-16.
In choosing the operating center frequency, fc, one must consider that it requires more
area for lower fc, due to the increased length of the Marchand-coupling and the common-mode
matching network, which are proportional to λc. Considering the limited available area in the
probe’s holder, this work was challenged to achieve an fc as low as 6 GHz, which fully occupies
the available area as shown in the next section. However, by allowing the balun to become
somewhat larger than the probe’s holder, fc can be anticipated to become as low as 3 GHz. Note,
there is less motivation to make Marchand baluns lower than fc = 3 GHz, because for such low
frequencies, compact sized ferrite-transformers can be used instead, which can operate from DC
to 1 ~ 2 GHz.
Figure 3-12. Cross-section of the proposed coupled microstrip-TL structures.
Using the proposed coupled TL structure, two types of Marchand baluns of fc = 6 GHz
are realized using an 8 mil-thick Rogers (RO4003) PCB, as shown in Figure 3-13. The top trace
and the bottom trace are not only used as coupled TLs for the Marchand-coupling, but also as
signal-path and GND for microstrip TLs before and after the Marchand-coupling; at the single-
53
A
B
Figure 3-13. PCB layout of the proposed Marchand balun. A) Type-A. B) Type-B.
54
ended port, P3, the bottom trace is the signal’s path while the top trace is the GND, and for the
differential ports, P1 and P2, as well as for the common-mode matching branch, the top trace is
the signal’s path while the bottom trace is the GND. Such a design provides convenient port-
interfaces to coaxial cables, and enables the structure to be free from vias and bond-wires, by
which one can achieve high cost-efficiency and high reproducibility in manufacturing.
Note that the common-mode matching branch for type-A uses a thinner trace than that of
type-B and any other 50 Ω traces. This is because of the finite length of the dual trace (along
with their undesired coupling effects) that exists between the Marchand-coupling and the chip
resistors’ terminals. This makes the optimum characteristic impedance of the common-mode
matching branch to be higher than its nominal 50 Ω, and this new thinner TL was chosen to be
optimum with respect to achieving the broadest relative-bandwidth.
A
B
Figure 3-14. Proposed balun embedded probes. A) Type-A. B) Type-B.
55
The designed planar type Marchand baluns are assembled with the conductive fixtures
and embedded onto the on-wafer probes as shown in Figure 3-14. The probe holder and probe’s
tips are ones used by the commercial “Dual Infinity Probe” series manufactured by Cascade
Microtech Inc.
3.5 Measurement Results
The balun embedded probes are measured using a dual-through pattern that is connected
to a dual-probe, as shown in Figure 3-15. The displayed ports, P1 ~ P3, are measured 2 ports at a
time using a 2-port VNA, while the 3rd port is terminated. This is followed by a post
measurement process that shifts the reference phase plane, as shown in the figure. Finally, the
full 9 mixed-mode s-parameters are calculated by combining all 3 combinations of such
measurements and using Equation 2-25.
Figure 3-15. Measuring balun embedded probes using a dual-through connected to a dual-probe.
The measured mixed-mode s-parameters are shown in Figure 3-16. It shows well-
balanced signals at the fc = 6 GHz, which gradually degrades as they approach towards the
sidebands, 3 GHz and 9 GHz. Although these imperfections become transparent through
calibration, the effects of these undesired reflections, as well as common- and cross-modes of the
differential DUT, can degrade the accuracy of the measurement, as presented in Chapter 4.
However, one can roughly estimate the measurement bandwidth by using 3 dB-relative-
bandwidth as introduced in Section 2.3. The sdd21 = sdd12 of type-A and type-B are shown to be
56
A
B
Figure 3-16. Measurement results of the proposed balun embedded probes. A) Type-A. B) Type-B.
57
3 dB larger than the other s-parameters at 3.25 GHz ~ 8.67 GHz and 3.43 GHz ~ 8.55 GHz,
respectively. Hence, their center frequencies are respectively 5.96 GHz and 5.99GHz, and the
resulting relative-bandwidths are respectively 0.909 and 0.855.
The measurement results showed that the proposed balun embedded probes can be used
in differential measurement for broad relative-bandwidths, as long as the effects of the baluns are
calibrated. The calibration procedure along with a new characterization method for the balun
embedded probes are presented in the following chapter.
58
CHAPTER 4 CHARACTERIZATION AND CALIBRATION FOR 3-PORT ERROR NETWORK
4.1 Introduction to 3-port Error-Box and its Characterization
In the proposed balun embedded measurement strategy, the error-network (or error-box),
from each port of the VNA to the DUT, is 3-port rather than the conventional 2-port. The
calibration of such error-boxes is shown in [4.1] and [1.7]. These methods can efficiently extract
the 4 mixed-mode s-parameters of interest (either the differential-mode or the common-mode,
depending on the type of the 3 dB-coupler used for the measurements), out of the 9 mixed-mode
s-parameters. However, it is also very important to extract the other remaining 5 mixed-mode s-
parameters describing the imperfection of the 3 dB-coupler, because they contribute to critical
measurement errors that can occur even under the most accurate calibrated conditions, as
discussed in Chapter 5.
Extracting the full 9 mixed-mode s-parameters of the error-box is shown in [4.2].
However, its application is limited to measuring the reflections of differential loads, and requires
the use of 3 dB hybrid-junctions that are capable of converting both differential-mode and
common-mode, simultaneously. The general method to characterize a 3-port error-box that
converts only to differential-mode or only to common-mode is to use a dual-through pattern
connected to a dual-probe. This is shown in Figure 4-1, for the case of balun embedded probes
(Figure 1-3C). The dual-through is a pattern available in the impedance-standard-substrate (ISS)
made for dual-probes, and the “Coaxial Cable” is the same coax that will be used during the
actual balun embedded measurement. The displayed ports, P1 ~ P3, are measured 2 ports at a
time using a 2-port VNA, while the 3rd port is terminated. This is followed by a post-
measurement process that shifts the reference plane, as shown in the figure. Finally, the full
mixed-mode s-parameters are calculated by combining all 3 combinations of such measurement
59
as shown in Equation 2-25. However, this method cannot account for the errors associated with
the imperfections of the dual-through pattern and dual-probe, and any errors that occur in the
VNA itself. It also requires connecting and disconnecting of ports between each measurement,
which compromises the accuracy.
Figure 4-1. Full Characterization of the 3-port error-box in the measurements using balun
embedded probe.
To overcome these problems, this work proposes a new set of Impedance-Standard-
Substrate (ISS) that can be used to efficiently characterize the full mixed-mode s-parameters of
the 3-port error-box, which will be presented and verified in Section 4.2. The proposed method
uses a pseudo-inverse of an over-determined matrix, by which the extracted results are tolerant to
errors that occur when measuring the impedance standards. Although the work focuses on balun
embedded measurements, the same method can be applied to general on-wafer measurements
using 3 dB-couplers. Furthermore, by a minor variation, the proposed method can be used to
efficiently extract the full mixed-mode s-parameters of the 3 dB-coupler embedded probe itself,
which becomes a valuable tool in the probe’s development stage. The application for a Marchand
balun embedded probe is shown in Section 4.3, and Section 4.4 shows the calibration procedure
using the 4 differential-mode s-parameters of the extracted 9 mixed-mode s-parameters.
4.2 Proposed ISS and Extraction Algorithm
The goal is to extract the full 9 mixed-mode s-parameter of the 3-port error-box, from the
VNA’s ports to the tip of the balun embedded probes. As shown in this section, this is done by
60
extracting the full 9 single-ended s-parameters using the proposed ISS, and than mathematically
converting them into the full 9 mixed-mode s-parameters, which is basically a variation of the
conventional method used for single-ended 2-port error-boxes [4.3].
4.2.1 Proposed ISS
The circuit-schematic of the proposed ISS is shown in Figure 4-2A. It consists of 9
patterns of dual-loads for P1 and P2, and 1 pattern of through (“thru”) which connects them. The
9 dual-load patterns are labeled with two lettered acronyms, where the first and second letter
respectively denote the load of P1 and P2, and the letters “S”, “O”, and “M”, respectively
represent “short”, “open”, and “matched”. It is assumed that the two ports are well isolated in
A
B Figure 4-2. Proposed impedance-standard-substrate (ISS). A) Circuit schematic. B) Locations
on the reflection plane.
61
the ISS (less then -32dB up to 10 MHz ~ 40 GHz), which can be achieved by placing a GND
strip between the two landing pads of P1 and P2. Figure 4-2B shows the locations of the 9 dual-
load patterns in a reflection plane where its axis X and Y are the reflection-coefficients at P1 and
P2, respectively. It shows that the 9 patterns are equally spaced among themselves, so that all of
the patterns produce well distinct dual-reflections at high frequencies. The proposed ISS is
designed to be applicable for 100 um ~ 150 um pitched GSSG (GND-Signal-Signal-GND) probe
tips, and its prototype is manufactured by Cascade Microtech Inc., which is a variation of their
commercial ISS (P/N 129-246) made for dual-probes.
4.2.2 Required Measurements
Two sets of measurements are required in using the proposed ISS, as shown Figure 4-3.
The first set, Figure 4-3A, characterizes the impedances of the patterns so that they become
“known” dual-loads. Hence, the patterns are measured using a dual-probe that is calibrated up to
“plane-a”. For 9 dual-load patterns, the measured s11 and s22 are respectively stored in variables
A
B
Figure 4-3. Required measurements for the proposed extraction algorithm. A) Measuring ISS only. B) Measuring ISS through error-box.
62
Xi and Yi,, where the index i = 1 ~ 9 corresponds to 9 dual-load patterns. For the “thru” pattern,
the measured s11, s22 and s21 (= s12) are respectively stored in X10, Y10, and Z10. Note, if this
proposed algorithm becomes systematically incorporated into the VNA, this first set of
measurements can be avoided by simply typing in the cal-coefficients of the dual patterns.
The second set of measurements, Figure 4-3B, characterizes the raw reflections of the
patterns through the 3-port error-box. Therefore, the measurements are done without calibration.
The measured reflections are stored in variables Ri, where i = 1 ~ 10 corresponds to the same
index used in the first set.
4.2.3 Extracting S-parameters of the 3-port Error-Box
The flowgraph of the single-ended s-parameter for the 3-port error-box and the ISS is
shown in Figure 4-4. The goal is to extract the unknown s-parameters of the 3-port error-box (the
e’s which are substituted by a ~ f and g for convenience), using the known s-parameters of the
ISS (Xi, Yi, and Zi) and the measured reflections (Ri). For the 9 dual-load patterns with Zi=1~9 = 0,
Ri=1~9 can be expressed using Mason’s Rule [4.4], as shown in Equation 4-1. By rearranging the
terms and writing for each of the i’s, this can be expressed in a matrix from, as shown in
Equation 4-2. Since M is a 9 x 7 over-determined matrix, its pseudo-inverse (M+) is used to
solve for X = M+·R, which is the unique solution that makes the error of ||R-M·X||2 minimum
[4.5]. For the “thru” pattern with Zi=10 ≠ 0, R10 can be expressed using Mason’s Rule, as shown in
Equation 4-3, which is rearranged in Equation 4-4 to achieve separate expressions for gf and c.
From the solved X from Equation 4-2 and the expression of gf and c shown in Equation
4-4, the unknown a ~ f and g can be extracted by the following procedure. First, a, b, and d are
obtained from the first 3 elements of X. These are then used in the next 3 elements X, from
which, g2, f2, and c2 are obtained. To extract their sign information, the obtained a, b, d, g2, f2,
and c2 are used in 7th elements of X to solve for gfc. Finally, by inserting the obtained a, b, d, g2,
63
Figure 4-4. Flowgraph of the ISS measurement through the error-box.
f2, c2, and gfc, into Equation 4-4, the signs of gf and c can be determined. Although, Equation 4-4
solves for the complete gf and c, only the sign information is being utilized. This is because the
previously obtained g2, f2, and c2 are expected to be more accurate due to their superior tolerance
to measurement errors that occur while measuring the ISS. This is discussed in detail in the
following section.
The sign of gf only offers the relative signs between g and f. Even with measuring more
Ri’s of known patterns, it is fundamentally impossible to extract the individual signs of g and f,
because the reflection path will always consists of g2, f2, or gf. While the relative sign of g and f
is sufficient to characterize the error-box’s mixed-mode s-parameters, there remains an
uncertainty of 180 x N degree (N = any integer) phase-shift in the error-box’s ssd21 (= sds12) and
ssc21 (= scs12). However, the procedure presented in this section is only shown for the 3-port error-
64
box leading to VNA’s port1. Therefore, at this point, it becomes only applicable for calibrating
and measuring a dual-reflection at VNA’s port1, where the effects of 180 x N degree phase-shift
cancel out.
This 180 x N degree uncertainty only becomes a problem for a full 4-port case, when
measuring the DUT’s mixed-mode forward and reverse transmission. In such case, 180 x N
degree uncertainty does not always cancel out because the N in the error-box attached to VNA’s
port1 may not necessary be the same as that of VNA’s port2. The same problem also exists in the
conventional single-ended 2-port calibration, and it is solved by measuring both error-boxes
back-to-back via a known through pattern [4.3]. The same algorithm can be applied for this
work by using dual-through patterns, which are available in ISS’s made for general dual-probes,
such as Cascade Microtech ISS P/N 129-246.
( )( ) iiii
iiiii YXcabYbXa
YXbfaggfcYgXfdR⋅−+⋅−⋅−
⋅−−+⋅+⋅+= 2
2222
12 (4-1)
⎟⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
+−−−−−−=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=
⋅=
abddcbfaggfcabcadfbdg
dba
R
RR
YXRYXXYRYRX
YXRYXXYRYRXYXRYXXYRYRX
222
2
2
2
9
2
1
99999999999
22222222222
11111111111
2
, ;
1
11
;
XR
M
XMR
M
MMMMMMM
(4-2)
( ) ( )( ) ( )2
1010102
101010
2101010
221010
210
2
10 2122
ZYXcabZfYbXaZYXbfaggfcZgfYgXfdR
−⋅−+⋅−⋅−⋅−−⋅−−+⋅+⋅+⋅
+= (4-3)
65
( )( )
( ) ( )( ) ( )( )( ) ( )( ) ( )2
10101022
102
102
10102
1010
1010
2
2210
2
2
ZYXgfcbfagdRcab
YgdRbXfdRadR
ZgfcdRc
fgdRgfc
cgf
−⋅−++−⋅−+
⋅+−⋅−⋅+−⋅−−
⋅⎟⎟⎠
⎞⎜⎜⎝
⎛
+−⋅+−⋅
⋅
=⎟⎟⎠
⎞⎜⎜⎝
⎛ (4-4)
4.2.4 Verification and its Comparison to the Use of 7 Dual-Load Patterns
Using the MATLAB program, the proposed algorithm is put into test for a set of known
s-parameters, and compared with an alternative approach of using minimum number of
measurements of the dual-load patterns, which is 7 corresponding to the 7 unknown elements in
the vector X. The resulting 7 x 7 matrix is shown in Equation 4-5 and its matrix equation is
shown in Equation 4-6, from which the solution becomes X = M′-1·R′. Note that i = 1 ~ 7 can
represent any of the 9 dual-load patterns.
1
11
77777777777
22222222222
11111111111
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=′
YXRYXXYRYRX
YXRYXXYRYRXYXRYXXYRYRX
MMMMMMMM (4-5)
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
=′⋅′=′
7
2
1
;
R
RR
MRXMR (4-6)
The s-parameters used for this verification are shown in Table 4-1. For the proposed
approach of using 9 dual-load patterns, the patterns SO, MO, OO, SM, MM, OM, SS, MS, and
OS, are assigned sequentially to i = 1 ~ 9. For the alternative approach of using 7 dual-load
patterns, the patterns SO, MO, SM, MM, OM, MS, and OS, are assigned sequentially to i = 1 ~ 7.
In order to emulate measurement errors, the Ri’s were added with a random variable that ranges
of -0.005 ~ 0.005 with uniform probability distribution. The root-mean-square (RMS) of the
errors of the extracted a ~ f and g are obtained by running the program 104 times, and the results
66
are shown in Table 4-2. It shows that the proposed approach of using 9 dual-load patterns is less
susceptible to measurements errors, compared to alternative approach of using the minimum 7
dual-load pattern. For one element, b (e22 in Figure 4-4), the proposed method of using 9 patterns,
showed approximately 5 times lower magnitude of RMS error compared to that of using the
minimum 7 patterns.
Table 4-1. Used s-parameter values for simulation verification Variables for s-parameters a b c d f g Used values 0.11 0.12 0.16 0.15 0.93 0.14
Table 4-2. RMS errors of the extracted s-parameter values Variables for s-parameters a b c d f g Extraction using 9 patterns 0.0024 0.0368 0.0089 0.0017 0.0009 0.0072 Extraction using 7 patterns 0.0040 0.1815 0.0314 0.0029 0.0012 0.0092
4.3 Application to Marchand Balun Embedded Probe
With minor variation, the proposed method can be used to extract the full mixed-mode s-
parameters of the 3 dB-coupler embedded probes, which becomes a valuable tool in their
development stage. This is done by calibrating up to “plane-b” for the second set of
measurements shown in Figure 4-3B. This is applied to a Marchand balun embedded probe
shown in Figure 3-14B, where the extracted results are shown in Figure 4-5. In order to check
reproducibility, the extraction procedure is repeated 9 times, which are shown by the overlapping
multiples lines. The results show that the extracted s-parameters using the proposed method are
in good agreement with that of previous method (symbol “o”) of using a dual-through pattern
connected to a dual-probe.
4.4 Calibration
From the extracted 9 mixed-mode s-parameters, the 4 differential-mode s-parameters are
used for calibration, which is shown in this section. The measurement setup for a full 4-port
67
A B C
D E F
G H I Figure 4-5. Extracted s-parameters of a balun embedded probe (Figure 3-14B) using the
proposed ISS and extraction algorithm (lines) and their comparison with the previous approach of using a dual-though pattern connected to a dual-probe (symbol “o”); the multiple conjoining lines represent the repeated sets of measurements (total of 9 sets). A) sdd11. B) sds12. C) sdc11. D) ssd21. E) sss22. F) ssc21. G) scd11. H) scs12. I) scc11.
balun embedded measurement is shown in Figure 4-6, where [s] is the differential-mode
elements of [Δs]4 of the DUT, and [e1] and [e2] are differential-mode elements of [Δs]3 of the
error-boxes. Along with VNA’s non-calibrated measurement, [m], these are all 2 x 2 s-parameter
matrices, which is the case for the de-embedding procedure of the conventional single-ended 2-
port calibration.
The de-embedding procedure begins with swapping the ports of error-box leading VNA’s
port1, as shown in Equation 4-7. This new [e1]′ is in cascaded connection to [s] and eventually
68
to [e2], which calls for the use of t-parameters [4.6] as defined in Equation 4-8 and the
conversion equations shown in Equation 4-9, where a’s and b’s are power-waves propagating to
and from the 2-port network, respectively. Using the t-parameters, the measurement network can
be described as Equation 4-10, where [s]t, [m]t, [e1]′t, and [e2]t are the t-parameters of [s], [m],
[e1]′, and [e2]. This equation is rearranged into Equation 4-11, from which the error-boxes are be
de-embedded. Finally, the de-embedded [s] can be achieved by the reverse conversion equation
shown in Equation 4-9.
Figure 4-6. Full 2-port balun embedded measurement and their 2 x 2 differential-mode s-
parameter matrices; [m] is a 2 x 2 single-ended s-parameter matrix which is measured using a non-calibrated VNA.
1111
1 1111
1112
2122
2221
1211⎟⎟⎠
⎞⎜⎜⎝
⎛=′⇒⎟⎟
⎠
⎞⎜⎜⎝
⎛=
eeee
eeee
][e[e1] (4-7)
2
2
2221
1211
1
1⎟⎟⎠
⎞⎜⎜⎝
⎛⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛=⎟⎟
⎠
⎞⎜⎜⎝
⎛ab
tttt
ba
(4-8)
( )
( )
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
−=
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
−
−
=
11
12
11
1111
21
2121
11
21
22
211
det
& det
1
tt
t
ttt
sss
ss
st
[s]s[t] (4-9)
69
tttt [e2][s]][e1[m] ⋅⋅′= (4-10)
11 −− ⋅⋅′= tttt [e2][m]][e1[s] (4-11)
Form the extracted 9 mixed-mode s-parameters, the other 5 s-parameters that are not used
in the calibration are common-mode and cross-mode s-parameters. These can cause critical
measurement errors, even under the most accurate calibration of the differential-modes. The
evaluation of these errors in relation to extracted common-mode and cross-mode s-parameters of
the 3-port error-boxes are presented in the following chapter.
70
CHAPTER 5 EVALUATION OF ERRORS CAUSED BY COMMON- AND CROSS-MODES
5.1 Measurement Errors Caused by Common-Modes and Cross-Modes
In the proposed balun embedded measurement strategy and the calibration algorithm
shown in the previous chapters, measurement errors will still exist even under the most accurate
extraction and calibration of the 3-port error-box. These are due to the undesired common-mode
and cross-modes (the conversion between the differential-mode and common-modes) of the
embedded balun and the differential DUT. This chapter proposes a new algorithm that evaluates
these errors, by which the users can conveniently be informed of the measurement’s accuracy.
Although it focuses on differential measurements where the errors are due to common-mode and
cross-modes (CXM), the same procedure can also be applied to common-mode measurements
using embedded power-splitters, where the errors are due to the differential-mode and cross-
modes. The differential measurement setup and their common-mode and cross-modes errors are
shown in Section 5.2. In Section 5.3, the proposed algorithm for evaluating these CXM errors is
presented, along with the employed approximations. Finally, the verification of the proposed
algorithm using a fully-differential amplifier measured via Rat-race baluns [2.7] is shown in
Section 5.4.
5.2 Common-Modes and Cross-Modes in Balun Embedded Measurements
The mixed-mode s-parameter flowgraph of the proposed measurement setup (Figure 4-6)
is shown in Figure 5-1, where s, e1, and e2 are the mixed-mode s-parameters of the DUT, error-
box-1, and error-box-2 respectively. These are represented by letters a ~ z, in order to provide
convenient notation in the next section. The dark lines are the differential-modes and the light-
gray lines are common- and cross-modes. In the ideal case, only the dark lines exist where the
error-boxes can be calibrated out to give the accurate characterization of the DUT’s 2 x 2
71
differential-mode s-parameters. However, in practice, the light-gray lines co-exist providing
additional paths. Hence, the extracted mixed-mode s-parameters of the DUT will be distorted
with these errors cause by CXM, even under the most accurate characterization and calibration
of the error-boxes’ differential-modes.
Figure 5-1. Mixed-mode flowgraph for differential measurement using baluns.
5.3 Error Evaluation and the Used Approximations
The goal is to evaluate the error of the calibrated 2 x 2 differential-mode s-parameters of
the DUT caused by the CXM. This starts with developing an approximate solution to the VNA’s
non-calibrated 2 x 2 s-parameters that includes the effects of the CXM of the error-box and the
DUT. The first approximation is that the two error-boxes are identical, by which the primes (') of
error-box-2 are dropped. Figure 5-2 shows the mixed-mode flowgraph of the VNA’s non-
calibrated s11 and s21. Although the differential-modes (black lines) are split from the CXM
(light- gray lines), the flowgraph is essentially the same as Figure 5-1, because the nodes (N1~4
and the input node) and the errors (e1~4, e11, and e21) are interlinked. The nodes of the flowgraph
can be expressed as Equation 5-1, where there associated terms are shown in Equations 5-2
through 5-5, and [I] is a 6x6 identity matrix. The matrix [M1] is obtained by observing only the
black lines, and the error terms in Equations 5-3 through 5-5 are obtained by applying Mason’s
72
Rule [4.4] on the light-gray lines. Finally, Equations 5-6 is obtained by inserting Equations 5-3
into Equations 5-1, where its first and last elements are respectively s11 and s21. The same
procedure is applied for VNA’s non-calibrated s22 and s12, as shown in Figure 5-3. It starts with
the Equation 5-7, where the associated terms shown in Equations 5-8 through 5-10. The final
Equations 5-11 is obtained by inserting Equations 5-9 into Equations 5-7, where its first and last
elements are respectively s22 and s12.
Figure 5-2. Mixed-mode flowgraph for VNA’s non-calibrated s11 and s21.
[ ]
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
+
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
⋅+
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
21
4
3
2
1
11
21
4
3
2
1
11
1
21
4
3
2
1
11
0000
eeeeee
SNNNNS
fd
SNNNNS
M (5-1)
73
[ ]
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
=
0000000000000000000000000000
fa
jhki
af
1M (5-2)
( )( )( )
( ) [ ]
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
⋅⋅Δ
+
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
+−+−+−+−
⋅Δ
=
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
21
4
3
2
1
11
2
22
21
4
3
2
1
11
11
111
1
SNNNNS
ygycg
ybgqwbtgxybgbtgnyzbcgbtcgryzbgbtrg
eeeeee
EEE1M (5-3)
( )( ) yzbbrbtE211 −−−=Δ (5-4)
[ ]( ) ( ) ( )
( ) ( ) ( )
( )( ) ( ) ( )
( )( )
( )( ) ( ) ( )
( )( )
( ) ( ) ( )
( ) ( ) ( )⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
⎭⎬⎫
⎩⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−⎭⎬⎫
⎩⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎪⎪
⎭
⎪⎪
⎬
⎫
⎪⎪
⎩
⎪⎪
⎨
⎧
+
+
−+
−
⎭⎬⎫
⎩⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎪⎪
⎭
⎪⎪
⎬
⎫
⎪⎪
⎩
⎪⎪
⎨
⎧
+
+
−+
−
⎪⎪
⎭
⎪⎪
⎬
⎫
⎪⎪
⎩
⎪⎪
⎨
⎧
+
+
−+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−
⎪⎪
⎭
⎪⎪
⎬
⎫
⎪⎪
⎩
⎪⎪
⎨
⎧
+
+
−+
−⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−
=
0
1
1
10
0
1
1
10
0
1
1
1
1
1
1
0
0
1
1
1
1
1 1
0
0
1
1
1
0
0
1
1
10
2
22
2
2
2
2
2
2
2
2
22
2
vybgbrgp
yzbcgbrcgt
ycgybgm
ubrgvybc
brcp
yzbcbrtc
ycybcm
ubrcwzpb
vyqbbrbpq
vwbtb
wzbcbrcq
ybcq
wbtc
uwzb
ymqb
ubrbq
wbtbmznpb
vxyb
xbrbp
vbtbn
zbcn
xbrcxybc
btcn
uznb
xymb
uxbrbbtbmn
zbcp
vbtczc
yzbcbtrc
uzbcbtcm
zbgp
vbtgzcg
yzbcgbtcgr
uzbgbtgm
E1M
(5-5)
74
[ ] [ ] [ ]
( )( )( )
( )
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
+−+−+−+−
⋅Δ
+
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
×⎟⎟⎠
⎞⎜⎜⎝
⎛⋅
Δ−−=
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
−
ygycg
ybgqwbtgxybgbtgnyzbcgbtcgryzbgbtrg
fd
SNNNNS
EE
2
22
1
1
21
4
3
2
1
11
1111
1
00001
E1MMI (5-6)
Figure 5-3. Mixed-mode flowgraph for VNA’s non-calibrated s22 and s12.
[ ]
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
+
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
⋅+
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
=
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
12
4
3
2
1
22
12
4
3
2
1
22
2
12
4
3
2
1
22
0000
eeeeee
SNNNNS
fd
SNNNNS
M (5-7)
75
[ ]
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
=
0000000000000000000000000000
2
fa
ikhj
af
M (5-8)
( )( )( )
( ) [ ]
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
⋅⋅Δ
+
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
+−+−+−+−
⋅Δ
=
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
12
4
3
2
1
22
2
22
12
4
3
2
1
22
11
111
1
SNNNNS
zgzcg
zbgnxbrgwzbgbrgqyzbcgbrcgtyzbgbrtg
eeeeee
EEE2M (5-9)
[ ]
( ) ( ) ( )
( ) ( ) ( )
( )( ) ( ) ( )
( )( )
( )( ) ( ) ( )
( )( )
( ) ( ) ( )
( ) ( ) ( )⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
⎭⎬⎫
⎩⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−⎭⎬⎫
⎩⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎪⎪
⎭
⎪⎪
⎬
⎫
⎪⎪
⎩
⎪⎪
⎨
⎧
+
+
−+
−
⎭⎬⎫
⎩⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎪⎪
⎭
⎪⎪
⎬
⎫
⎪⎪
⎩
⎪⎪
⎨
⎧
+
+
−+
−
⎪⎪
⎭
⎪⎪
⎬
⎫
⎪⎪
⎩
⎪⎪
⎨
⎧
+
+
−+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−
⎪⎪
⎭
⎪⎪
⎬
⎫
⎪⎪
⎩
⎪⎪
⎨
⎧
+
+
−+
−⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−
⎭⎬⎫
⎩⎨⎧
+
−
=
0
1
1
10
0
1
1
10
0
1
1
1
1
1
1
0
0
1
1
1
1
1 1
0
0
1
1
1
0
0
1
1
10
2
22
2
2
2
2
2
2
2
2
22
2
uzbgbtgm
yzbcgbtcgr
zcgzbgp
vbtguzbc
btcm
yzbcbtrc
zczbcp
vbtcxymb
uznbbtbmn
uxbrb
xybcbtcn
zbcn
xbrc
vxyb
zpnb
vbtbn
xbrbpymqb
uwzb
wbtbm
ubrbq
ybcq
wbtcwzbc
brcq
vyqb
wzpb
vwbtbbrbpq
ybcm
ubrcyc
yzbcbrtc
vybcbrcp
ybgm
ubrgycg
yzbcgbrcgt
vybgbrgp
E2M
(5-10)
76
[ ] [ ] [ ]
( )( )( )
( )
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
+−+−+−+−
⋅Δ
+
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
×⎟⎟⎠
⎞⎜⎜⎝
⎛⋅
Δ−−=
⎟⎟⎟⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜⎜⎜⎜
⎝
⎛
−
zgzcg
zbgnxbrgwzbgbrgqyzbcgbrcgtyzbgbrtg
fd
SNNNNS
EE
2
22
1
22
12
4
3
2
1
22
1111
1
00001
EMMI (5-11)
Note that the same solution for the VNA’s non-calibrated 2 x 2 s-parameters can be
achieved by directly extracting the nodes’ matrix equation from the mixed-mode flowgraph in
Figure 5-1. This will result in an 11 x 11 matrix in correspondence to the 12 nodes less the input
node. For the proposed method to be applicable to VNA’s post measurement processes, fast
calculation speed is essential. However, calculating the inverse of an 11 x 11 matrix can become
too much overhead for the system to process at each point of the swept frequency. Therefore, it
becomes more beneficial to use Equations 5-6 and 5-11, since they only require calculating the
inverse of a 6 x 6 matrix. The calculation time of the proposed post measurement processes is
discussed in detail in the following section.
The mixed-mode s-parameters (a ~ z) for solving Equations 5-6 and 5-11 are obtained as
follows. The error-boxes’ a ~ f and g can be are obtained by using the characterization method
proposed in [4.2] for hybrid-junctioned measurements or by using the method proposed in
Chapter 3 for on-wafer balun embedded measurements. The dual-loads of the 4-port DUT (m, n,
i, j, p, q, r, and t) can be obtained using 2-port measurements as shown in Figure 5-4, which can
be done fairly easily for both coaxial-interfaced and on-wafer measurements. As a second
approximation, the DUT’s forward and reverse differential gains (h and k) are substituted with
their results obtained through the balun embedded measurements, where the 3-port error-boxes
are calibrated out using the method presented in Chapter 3. As the third and final approximation,
the other unknown CXM (u ~ z) of the DUT are each substituted by complex random variables,
77
where their amplitudes range from -0.3162 ~ 0.3162 (where, 0.3162 = -10 dB) and -0.1 ~ 0.1
(where, 0.1 = -20 dB) for forward gains (u, w, and y) and the reserve gains (v, x, and z),
respectively, all with uniform probability distribution. The random phases range from -π ~ π,
also with uniform probability distribution. This third approximation is assuming that the forward
and reverse CXM gains are respectively less then -10 dB and -20 dB. However, the user can
change these numbers when given more information on the DUT’s CXM, where the
measurements’ accuracy will increase if the DUT is guaranteed to have lower CXM gains.
A
B Figure 5-4. Measuring dual-reflections of the DUT.
Using these mixed-mode s-parameters as inputs, the VNA’s non-calibrated 2 x 2 s-
parameters are calculated using Equations 5-6 and 5-11. The results are then calibrated using the
procedure presented in Chapter 4, which represent a 2 x 2 differential s-parameter of a DUT for
randomly generated complex variables for u ~ z. In order to find out how much u ~ z can
contribute to the measurement, this process is repeated at least 100 times (each time using
different random values for generated for u ~ z), from which the maximum and the minimum
amplitude of each 2 x 2 differential s-parameter are chosen. As shown in the next section, these
anticipated maximum and minimum provide the quantitative information of the CXM’s effects to
the measurements, from which their accuracies can be efficiently evaluated.
78
5.4 Application to Fully-Differential Amplifier
Using circuit simulations, the proposed method is put into test for a fully-differential
amplifier that is being measured using a Rat-race type balun. The Rat-race type balun is shown
in Figure 5-5. It is designed to have the center frequency, fc (= phase-velocity x λc) of 6 GHz. In
order to achieve large CXM, the delay paths’ electrical length and their characteristic
impedances were purposely skewed from the displayed nominal values, where the resulting
mixed-mode s-parameters are shown in Figure 5-6. The same is done for the fully-differential
Figure 5-5. Rat-race type balun; mismatches were randomly induced from the shown nominal
values in order to achieve large CXM.
Figure 5-6. Mixed-mode s-parameters of a Rat-race type balun shown in Figure 5-5.
79
amplifier which is shown in Figure 5-7. Each component is randomly designated to either be
increased or decreased by 10 % from its nominal values shown in the figure. The resulting
mixed-mode s-parameters of the fully differential amplifier are shown in Figure 5-8.
As shown in Figure 5-9, the 2 x 2 differential s-parameters of the fully-differential
amplifier are measured using the rat-race balun, and the effects of the rat-race balun are
calibrated out. The non-calibrated s-parameters (including the baluns) are shown in dashed-black
lines and the calibrated s-parameters (where the differential-mode networks of the baluns are
calibrated out) are shown in solid-black lines. This is still off from the original s-parameters
(solid-light-gray lines) due to the errors cause by the CXM of the balun and the DUT.
Figure 5-7. Fully-differential amplifier; 10% variations were randomly induced from the shown
nominal values in order to achieve large CXM.
Since the original s-parameters are not available in the actual measurement environment,
the user cannot be informed of the amount of errors that are associated with the measured results
(solid-black lines). However, the user can be informed of the anticipated maximum and
minimum s-parameters, where their variations are caused by CXM. From this, the users are
80
efficiently informed of the measurement accuracy along with their measurement results. This is
done by the proposed method of using Equations 5-6 and 5-11 along with random complex
variables for the unknown CXM of the DUT, as shown in Figure 5-9. The anticipated maximum
and minimum are respectively shown in symbols “∇” and “Δ”. The filled colors of the symbols,
A
B Figure 5-8. Mixed-mode s-parameters of the fully-differential amplifier shown in Figure 5-7.
A) Elements larger than -25 dBm. B) Elements lower than -24 dBm.
81
A B
C D
Figure 5-9. Differential-mode s-parameters of the DUT; the lines represent the original (solid-light-gray), measured (dashed-black), and calibrated (solid-black) s-parameters; symbols represent the anticipated maximum (“∇”) and minimum (“Δ”), using 102 (white), 103 (gray) and 104 (black) samples. A) sdd11. B) sdd12. C) sdd21. D) sdd22.
“∇” and “Δ”, represent the number of random complex samples used, from which the maximum
and minimum s-parameters were chosen. The colors white, gray, and black, respectively
correspond to using 102, 103, and 104 random complex samples, where the CPU’s calculation
times were respectively 3.8, 38.3, and 390.9 seconds, when using Intel’s 1.4 GHz Celeron
Mobile Processor.
The results show that the original and the calibrated s-parameters are all well within the
anticipated maximum and minimum s-parameters. Note that the dB-ranges between the
82
anticipated maximum and minimum s-parameters become larger as the frequency approaches the
sidebands of 6 GHz. This is due to the limited bandwidth of the rat-race type balun, where its
CXM is minimal at the fc = 6 GHz, but gradually increases as it approaches the sidebands. As
mentioned in the previously section, the dB-ranges between the anticipated maximum and
minimum s-parameters can be decreased if the DUT was respectively guaranteed with lesser
forward and reverse CXM gains than -10 dB and -20 dB.
So far, passive baluns were used for the proposed balun embedded measurement.
Although, the Marchand balun can provide broad 3 dB-relative-bandwidth, it is difficult to make
this larger than 1, due to in the increase of CXM and their associated measurement errors.
Therefore, in efforts to further increase the bandwidth of the proposed measurement strategy,
active baluns are developed using a newly proposed combined cascode and cascade pair, as
shown in the next chapter.
83
CHAPTER 6 ACTIVE BALUN USING COMBINED CASCODE-CASCADE CONFIGURATION
6.1 Introduction to Various Active Baluns
Active baluns are unidirectional converters between differential and single-ended signals,
as shown in Figure 6-1, where the single-ended and mixed-mode s-parameters are compared with
that of a passive balun. In spite of their inability for bi-directional conversion, as for the case of
passive baluns, they are used for their large bandwidth, which is beyond what passive baluns can
provide. The bandwidth’s upper-end frequency of an active balun depends on the technology’s
Figure 6-1. Comparing single-ended and mixed-mode s-parameters between passive balun and
active balun, where θ1 - θ2 = 180°.
84
speed, while the lower-end frequency can potentially extend to DC, when not considering the
effects of the DC-decoupling capacitors in the ports. Such unbounded lower-end frequency
enables active baluns to be realized in limited chip-areas, which makes them the most suitable
for Built-in Self Test (BIST) applications [1.9]-[1.11], as well as general differential circuits
requiring compact sized broadband baluns.
6.1.1 Distributed Amplifier Type
The distributed amplifier based balun is shown in Figure 6-2. Similar to a conventional
distributed amplifier, the input in P3 travels through a virtual transmission-line realized by the
cascaded lumped LC-network (C is the parasitic gate capacitance) where it’s characteristic
impedance 1/(2π x sqrt(LC)) is equal to 50 Ω, and finally reaches P1. While the signals travel
through the virtual transmission-line, each transistor generates an output signal at the drain,
which is combined through another virtual transmission-line realized by the cascaded lumped
LC-network attached to the drain (C is the parasitic drain capacitance). The gain in each path can
be designed to be -3 dB by making the L’s lossy and controlling the gain of each transistor. In a
given CMOS or Bipolar process, the distributed amplifier configuration produces the largest
bandwidth [6.1]. However, it occupies a fairly large area of at least 1 mm x 2 mm. Due to such
large area overhead, it is seldom used in embedded test applications.
Figure 6-2. Distributed amplifier type active balun.
85
6.1.2 Differential Amplifier Type
A suitable approach in limited chip-areas is the differential amplifier configuration [6.2],
as shown ion Figure 6-3, which is most commonly used due to its large common-mode rejection.
However at high frequencies, the two outputs become unbalanced because two signals travel
through different number of stages from the common input - one stage (common-source of M2)
for the inverting path and two stages (common-drain of M2 followed by common-gate of M1) for
the non-inverting path. A series LC-network can be used to compensate for the mismatched
phase [6.3][6.4], but this sacrifices the bandwidth’s lower-end frequency.
Figure 6-3. Differential amplifier type active balun.
6.1.3 Source-Drain Output Configuration
Matching the number of stages of can be achieved by using a source-drain output
configuration [6.5][6.6], as shown in Figure 6-4. The unbalanced input at P3 is converted into
balanced output to P1 (non-inverting source-output) and P2 (inverting drain-output). This type of
active balun is superior with regards to using a single transistor (M1), by which it becomes free
from the magnitude imbalance caused by the mismatches among multiple transistors in other
configurations of active baluns. However, other than its low dynamic range due to the required
Vdsat of M1, it has some inherent critical problems, such as the requirement of a second gain stage
and phase mismatch at high frequencies.
86
Figure 6-4. Active balun using source-drain output configuration.
The requirement of a second stage is investigated in Figure 6-5, which is a source-
follower with matched input and output (I/O). The maximum gain can be achieved by assuming
that the current-source is ideal. For Zs = 1/(gm·(1+η)) to be matched to 50 Ω, gm must be equal to
1/(50·(1+η)). Using this, along with v1+ = 0 and vi
- = 0 of matched case, the maximum s13 of the
source-drain output type balun can be expressed as Equation 6-1, which is shown to be always
less than 1/2, and hence, less than the required gain of 1/sqrt(2) for baluns.
Figure 6-5. Matched source-follower for maximum forward-gain at low frequencies.
( )21
11
2150||
50/50/ 11
13 <+
⋅=⋅===+
−
ηsmii
zgvv
vvs (6-1)
The more critical problem is the imbalanced phase of the differential output at high
frequencies. Figure 6-6 shows the simplified AC-equivalent circuit of the source-drain output
configuration, where its forward gains to the source and the drain are respectively solved in
87
Equations 6-2 and 6-3. Practical values of the parameters in Equation 6-3 will make the enclosed
first order term of s of the numerator to become positive. Using this sign information along with
the fact that the last term its numerator is negative, one can see that Equation 6-3 has one
positive and one negative zero. Therefore, Equation 6-3 has an additional pole and a negative
zero when compared to Equation 6-2, where each produces an additional 45o / Dec decrease in
the phase, compared to that of Equation 6-2.
Figure 6-6. Simplified AC-equivalent circuit of the active balun using source-drain output
configuration.
( )η−++
+=
111
ms
gs
mgs
i gR
sC
gsCvv (6-2)
( )
( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛+⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛−++
−⎟⎟⎠
⎞⎜⎜⎝
⎛−⎟⎟
⎠
⎞⎜⎜⎝
⎛−++
=
dgdm
sgs
s
mmgsm
sgdgsgd
i
RsCg
RsC
RggCg
RCsCCs
vv
111
112
2
η
ηη (6-3)
6.1.4 Common-Source and Common-Gate Pair Configuration
The more promising method for achieving balanced phase at high frequencies is to use
common-source and common-gate pair [6.7][6.8], as shown in Figure 6-7. Using this
configuration, the relative phase can maintain 180o at high frequencies beyond the first few poles.
88
However, a new challenge exists for matching the input, due to its high parasitic capacitance at
the two transistors (M1 and M2) which are accompanied by a third transistor from a current-
source for biasing M1.
Figure 6-7. Active balun using common-source and common-gate pair.
To overcome these problems, this paper proposes a new configuration of cascode and
cascade pair using a shared input transistor, hence the name, combined cascode-cascade balun
(C3-balun). This new configuration will be presented in detail in Section 6.2, and the
measurement environment and the measurement results are respectively shown in Section 6.3
and 6.4. Furthermore, an attached low frequency feedback network is proposed in Section 6.5,
which can improve the stability of the proposed circuit’s bias condition in future designs.
6.2 The Proposed Combined Cascode-Cascade Configuration
The proposed C3-blaun is shown in Figure 6-8, where the transistors’ transconductance
are annotated in parenthesis. The cascaded non-inverting path for s13 is combined with a
cascoded inverting path for s23, using a common input stage transistor M3. Compared to the
previous common-source and common-gate pair configuration, the proposed C3-balun enables
higher reverse-isolation and a broader frequency range for input matching due to the reduced
parasitic capacitance at P3. The broadband input matching is further enhanced by dividing the
89
input’s 50 Ω resistance into 22.6 Ω and 27.0 Ω, where the remaining 0.3 Ω is from the parasitic
resistance of the 0.2nH inductor, which is there to achieve inductive peaking to maximize the
bandwidth’s upper-end frequency. The dividing of the 50 Ω resistance reduces the input signal,
thus requires the increases of the size of M3. Although this increases the gate-capacitance, a
broader input matching can be achieved due to the separated 22.6 Ω, which is free from being
shunted by the increased gate-capacitance.
Figure 6-8. Proposed active balun using combined cascode-cascade configuration (C3-balun).
The circuit contains no DC-decoupling capacitors, other than the ones at the ports’
terminals. This is to best extend the balun’s bandwidth on its lower-end frequency as close to DC
as possible. However, from the design and optimization standpoint, this also means that the
selection of bias-points is not as convenient. The biggest challenge is deciding on the bias point
90
for v3, since it influences all three transistors, simultaneously. For this reason, 4.7 Ω is introduced
to enable additional design freedom, so that bias point of M2’s source, v′3, can be chosen to be
different from that of M3’s drain and M1’s gate, v3. The bias-points are optimally chosen for the
circuit to operate up to 5 dBm of the input power, while maintaining all transistors to operate in
the saturation-mode and remain safe from gate-drain and gate-source oxide breakdown. The
designed bias-points and the simulated AC voltage swings (peak values) are shown in Table 6-1.
Note such optimization has resulted in large biases for VDD’s as high as 4.2 V. However, these
values can be reduced if the design is aimed for less operational power.
The simulation result of the proposed C3-balun is shown in Figure 6-9. It shows that the
two forward gains maintain -3 dB with opposite polarities up to 30 GHz. All other undesired s-
parameters, such as reflections and isolations, are all shown to be less then -10dB up to 30 GHz.
Table 6-1. C3-balun’s internal bias points and AC voltage swings at 5 dBm input Nodes DC bias points AC voltage swings (peak) Result voltage swings vs - 0.56 V - vi 1.00 V 0.31 V 0.69 ~ 1.31 V v3 1.05 V 0.31 V 0.74 ~ 1.36 V v′3 1.16 V 0.25 V 0.91 ~ 1.41 V v2 2.36 V 0.40 V 1.96 ~ 2.76 V v1 1.39 V 0.40 V 0.99 ~ 1.79 V
A B C
Figure 6-9. Simulation results of the proposed C3-balun. A) Magnitude of s13 and s23. B) Phase of s13 and s23. C) Other undesired s-parameters.
91
The proposed C3-balun is manufactured using the IBM 8HP 130 nm BiCMOS process.
The layout is shown in Figure 6-10 and the manufactured chip is shown in Figure 6-11. The
“dummy pads” are placed for calibrating out the pads’ effects, as it will be presented in the next
section. As shown in the figure, by replacing the 0.2 nH line-inductor into an “Ω”-shaped
inductor, one can anticipate that the compacted version of the layout can be as small as 0.2 mm x
0.2 mm (without including the pads), which makes the proposed active balun to become suitable
for BIST applications, as well as general differential circuits requiring compact sized broadband
baluns. The interconnect and routing of the fingers of the NMOS is shown in Figures 6-12
through 6-14, where M#, MQ, AM are the metal layers and G, S, D respectively denotes that the
routing is to the gate, source, drain.
Figure 6-10. Chip layout of the proposed C3-blaun in IBM 8HP 130 nm BiCMOS process.
92
Figure 6-11. Chip photo of the proposed C3-blaun in IBM 8HP 130 nm BiCMOS process.
Figure 6-12. Layout for NMOS interconnect; M3 of the proposed C3-balun. “Sub_Con” denotes
substrate contact.
93
Figure 6-13. Layout for NMOS interconnect; zoom-in area of Figure 6-12.
Figure 6-14. Layout for NMOS interconnect; zoom-in area of Figure 6-13.
94
6.3 Measurement Environment
The proposed C3-balun is measured with Rohde & Schwarz’s ZVA40 which is a true-
differential 4-port vector network analyzer (VNA) using phase controlled balanced differential
sources and receivers [1.5][6.9]. The on-wafer RF probing and calibrations are done using
Cascade Microtech’s Infinity Probe Series (GSG for P3 and GSSG for P1 and P2, where “G”
stands for ground and “S” stands for RF signal), and their Impedance-Standard-Substrate (ISS)
P/N’s 005-016 (for GSG) and 129-246 (for GSSG). The DC biasing is done using GGB’s DC
probes with bypass chip capacitors embedded at the tip and the rear to provide stable biases
through out the frequency range of 10 MHz ~ 40 GHz, as shown in Figure 6-15. These
capacitors are embedded because the on-chip capacitors cannot be made large enough to bypass
the frequency components less than 1 GHz.
Figure 6-15. Three-pin DC-probe with embedded bypass capacitors.
In calibrating for a 3-port measurement, a new challenge emerges in the “through”
measurements between the GSG and the GSSG. This is because no grounds (G’s) should be left
floating during the “through” measurements, in order to achieve accurate calibrations up to tens
of GHz. This is solved by using “unknown through” - “open” - “short” - “match” (UOSM)
95
algorithm [4.3][6.10]. By tilted GSG through pattern of the ISS P/N 005-016, as shown in Figure
6-16, one can measure the “unknown through” between GSG (P3) and the GSSG (P1 or P2).
A
B
Figure 6-16. Using GSG’s “through” pattern for unknown-through measurements. A) Unknown through between P3 and P1. B) Unknown through between P3 and P2.
Another challenge is the post measurement process of calibrating out the pads’ effects, as
shown in Figure 6-17. The measured s-parameters of the active balun with pads ([s]D) and those
of the pads obtained by measuring the dummy pads shown in Figure 6-10 ([s]P), are respectively
converted into y-parameters of [y]D and [y]P. From this, the y-parameters of active balun
(without pads) can be obtained by [y]A = [y]D - [y]P, which can be converted back to its s-
parameters, [s]A. The conversion between the s-parameters and y-parameters of a 3-port network,
can be derived from their definitions as shown in Equations 6-4 and 6-5. The relationship
between the s-parameters’ power-waves, and the y-parameters’ v’s and i’s (where it is defined to
direct inwards to the network) are shown in Equations 6-6 and 6-7. By inserting Equation 6-6
into Equation 6-4 and inserting Equation 6-7 into Equation 6-5, the conversion equations
between the two parameters can be derived as Equations 6-8 and 6-9.
96
A B C Figure 6-17. Full 3 x 3 s-parameter and y-parameter matrices of A) active balun with pads, B)
pads only, and C) active balun without pads.
[ ]
3
2
1
3
2
1
333231
232221
131211
3
2
1
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛⋅≡
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛⋅
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
aaa
aaa
sssssssss
bbb
s (6-4)
[ ]⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛⋅≡
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛⋅
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛=
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
3
2
1
3
2
1
333231
232221
131211
3
2
1
vvv
vvv
yyyyyyyyy
iii
y (6-5)
⎟⎟⎠
⎞⎜⎜⎝
⎛⋅
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
−
=⎟⎟⎠
⎞⎜⎜⎝
⎛
= k
k
kk
k
iv
zz
zz
ba
221
221
0
0
0
0
3~1
(6-6)
⎟⎟⎠
⎞⎜⎜⎝
⎛⋅
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
−=⎟⎟⎠
⎞⎜⎜⎝
⎛
= k
k
kk
k
ba
zz
zz
iv
00
00
3~1
11 (6-7)
[ ] [ ] [ ][ ] [ ] [ ][ ]sIsIy −⋅+⋅= −1
0
1z
(6-8)
[ ] [ ] [ ][ ] [ ] [ ][ ]yIyIs ⋅−⋅⋅+= −0
10 zz (6-9)
97
6.4 Measurement Results
The single-ended measurement of the proposed C3-blaun is shown in Figure 6-18. The
forward gains are 1 dB ~ 1.5 dB higher than that of the simulation. These are most possibly due
to increased load resistances caused by the parasitic routing resistance, which can be amended in
future designs by post layout simulations. The phase of the forward gains are shown in Figure 6-
19, where their relative phase maintains 180º (± 10º) up to 30 GHz. This is well beyond the point
in which the gain starts to decrease, which cannot be achieved using the previous source-drain
output type active baluns, as presented in Section 6.1.3. The other undesired s-parameters such as
the reflections and the isolations are all less then -10 dB up to 30 GHz.
The measured mixed-mode s-parameters are shown in Figure 6-20 and Figure 6-21 for
the input power of -25 dBm and 5 dBm, respectively. The forward differential gains in the two
graphs show virtually the same results, which proves that the proposed C3-blaun maintains its
linearity for the input as high as 5 dBm.
The other undesired s-parameters such as reflections and isolations are all under -10 dB
up to 30 GHz, except for sdd11 during the frequency range 0.4 GHz ~ 1 GHz and 20 GHz ~ 30
GHz, where it becomes as high as -6.1 dB. This is due to the constructive interference of the
single-ended reflections shown in Figure 6-18, which was neglected during the simulation-level
design stage of monitoring only the single ended s-parameters. This can be solved in the future
designs by monitoring the mixed-mode s-parameters as well, during the simulation-level design
stage.
Table 6-2 shows the accuracies of the forward gains for various bandwidths. This shows
that the proposed C3-balun can be used directly with high accuracy up to 10 GHz, and with
moderate accuracy up to 17 GHz. However, if the errors caused by the balun’s imperfections can
be calibrated out, the proposed C3-balun can be used up to 30 GHz. However, as discussed in
98
Figure 6-18. Measured magnitude of the single-ended s-parameters of the proposed C3-balun at the input power of -25 dBm.
Figure 6-19. Measured phase of the single-ended s-parameters of the proposed C3-balun at the input power of -25 dBm.
99
Figure 6-20. Mixed-mode s-parameter measurement of the proposed C3-balun at -25 dBm input.
Figure 6-21. Mixed-mode s-parameter measurement of the proposed C3-balun at 5 dBm input.
100
Table 6-2. Forward gains of C3-balun for the input power of -25 dBm ~ 5 dBm Bandwidth | dB(s23) - dB(s13) | [dB] �(s23) - �(s13) [deg] dB(sds12) [dB] DC ~ 10 GHz < 1.1 173 ~ 184 -1.5 ~ 1.8 DC ~ 17 GHz < 1.8 170 ~ 184 -2.7 ~ 1.9 DC ~ 30 GHz < 9.4 170 ~ 188 -6.8 ~ 1.9
Chapter 4, applications beyond 30 GHz are not recommended due to the increase in the common
and cross-mode errors of the balun, where they can cause critical measurement errors, even
under the most accurate calibration conditions.
For the noise measurements, it is important to note that baluns must be characterized with
differential noise rather then the conventional single-ended noise, in order to well describe
circuit’s performances accordance to its applications. Unfortunately, this cannot be obtained by
mathematically combining the noise performances at each port, because their randomness cannot
account for the relative phase and magnitude of the differential-port. However, ZVA40 offers a
Figure 6-22. Noise measurement of the proposed C3-balun; symbols “Δ” and “O” represent
differential-mode and common- mode, respectively, where the filled symbols are the measured noise and the unfilled symbols are the VNA system’s background noise.
101
spectrum analyzer mode, by which a true-differential output powers can be measured as shown
in Figure 6-22. Each frequency point is plotted with the average value obtained from repeated
noise measurements of 26 times. Symbols “Δ” and “O” filled in gray respectively represent the
output power’s differential-mode and common-mode, at zero input (terminated with 50 Ω). This
is compared with the unfilled symbols, which represent the system’s background noise of the
ZVA40. This comparison shows that the measured noises (the filled symbols) are only valid
roughly in frequency range of 0.2 GHz ~ 20 GHz. Within this valid frequency range the
proposed C3-balun showed low differential noise of less than -95 dBm. Note that in certain
frequency range clusters, the differential-mode is shown to be at least 10 dB higher than that of
the common-mode, which cannot be obtained by mathematically combining single-needed noise
measurements.
6.5 Low-Pass Bias-Feedback Network for Stable Bias Conditions
The internal bias points of the proposed C3-balun have significant affects to the circuits
overall performances, especially on the gain and the dynamic range. However, minor process
variations of the transistors will result in alternate bias points, which can significantly change the
transmission gains of the circuits. Therefore, developing a low-pass bias-feedback mechanism by
which the circuit can maintain stable bias conditions regardless of the process variations is one of
the most important tasks for the proposed C3-balun’s future design.
The low-pass bias-feedback network is shown in Figure 6-23, where the drain currents of
ID1 (for M1) and ID2 (for M2 and M3) are matched to 17.12 mA. Despite the process variations
of the transistors, the matching of the drain currents are achieved by the attached low-pass
feedback network; the lower-end terminals of the two 62.9 Ω resistors are connected to vip and vin,
where their DC values tends to match each other (vip @ DC = vin @ DC) due to the large low-
102
Figure 6-23. C3-balun with network for stable biasing.
frequency gain of the loop formed by attached low-frequency amplifier (18 dB loop gain from vip
vout source-follower of M2 common-source of M1 back to vip). The circuit diagram
for the low-frequency amplifier is shown in Figure 6-24. The matching of the drain currents
enables the matching of the transconductances of M3 and M1, which results in the matching of s13
and s23.
The low-pass bias-feedback network only controls the matching of s13 and s23 and not
their values, which need to be maintained at -3 dB each. Since the values of the matched s13 and
s23 depends on the matched bias currents of ID1 and ID2, these bias currents need to be well
controlled. This is done by IREF of the attached self-biasing circuit, as shown in Figure 6-25,
which delivers VREF to the proposed C3-balun. The self-biased IREF is independent of VDD as
shown in Equation 6-10, where VTH10 is the threshold of M10 and B10 is from the large signal
equations for a short-channel NMOS transistor operating in saturation, IREF = B10(VREF - VTH10).
103
Figure 6-24. Low frequency amplifier used for low-pass bias-feedback network in the proposed
C3-balun.
Figure 6-25. Threshold-referenced self-biasing network used in the proposed C3-balun and the attached low-pass bias-feedback network.
( ) 1 9410
10
−Ω⋅=
BV
I THREF (6-10)
104
Note that in Figure 6-23, the used C3-balun is slightly modified from its previous version.
The modification is done to use constant VDD (3.58 V) and also to accommodate for the
increased parasitic capacitance associated with the attached self-biasing circuit and the low
frequency amplifier. This modified C3-balun is designed using no inductors and operates in the
frequency range from 10 MHz up to 10 GHz with the maximum input power of 0 dBm. However,
the upper-end frequency is expected to increase at least up to 17 GHz (as shown in the
measurements of the previous design), by using on-chip inductors (connected in series with the
94 Ω in the self-biasing circuit shown in Figure 6-24), and also by lowering the maximum input
power to be less than 0 dBm. Further increase in the upper-end frequency can be achieved by
sacrificing the lower-end frequency, allowing one to use internal DC-blocking capacitors by
which the transistors’ operational bias-points can be chosen independently from each other.
The overall performances of the C3-balun with the attached biasing network are shown in
Figure 6-26, where the -3 dB bandwidth is up to 10 GHz. This figure also presents the stability
response for the feedback branch “I-Probe” shown in Figure 6-23, where the DC loop gain is 18
dB and the phase margin is 60 degrees. The large DC loop gain enables the two bias points at vip
A B C
Figure 6-26. Overall performances of the C3-balun the attached biasing network. A) Magnitude of the s-parameters. B) Phase of the s13 and s23. C) Stability response.
105
and vin to be matched, which results in the matched s13 and s23, as shown in Table 6-3. The
results show that despite the ±2 % process variations in M1 and M2, the ID1 and ID2 maintains
their values with in 0.35 %, which results in the small change in the transmission gain of less
than 0.36 dB.
Table 6-3. Change of performances of the proposed C3-balun due to process variations Operation 2% decrease
in M1 2% increase
in M1 2% decrease
in M2 2% increase
in M2 ID1 [mA] 17.13 mA 17.11 mA 17.09 mA 17.15 mA s13 @ 0.1 GHz -3.12 dB -2.87 dB -2.81 dB -3.17 dB ID2 [mA] 17.15 mA 17.09 mA 17.12 mA 17.12 mA s23 @ 0.1 GHz -2.99 dB -3.02 dB -3.03 dB -2.98 dB ∠s23-∠s13 @ 10 GHz 187.60° 187.81° 187.76° 187.77°
6.6 Summary and Applications
In efforts to further increase the measurement bandwidth of the proposed measurement
strategy, a new active balun is proposed which operates with the input power as high as 5 dBm,
and the bandwidth up to 17 GHz, where the imbalance of the differential output was less than 1.8
dB in amplitude and less then 10 degrees in phase. The solution for stable biasing is also
proposed by attaching a low-pass bias-feedback network. With the development of a calibration
algorithm for unidirectional error-networks, the proposed active balun is anticipated to become a
promising solution for the proposed measurement strategy, due to their large bandwidth and
compact size (as small as 0.2 mm x 0.2 mm), which are far beyond what passive baluns can
provide. Such characteristics also make the proposed active balun to become most suitable for
BIST applications as well as general circuits requiring compact sized broadband baluns.
106
CHAPTER 7 CONCLUSION
The conventional 2-port VNAs were used for measuring 4-port differential circuits,
where each port was embedded with a balun, either using external baluns, on-chip baluns, or
baluns integrated in on-wafer probes, as shown in Figure 7-1. The potential of this proposed
measurement strategy need not be confined to VNAs. It can be applied to virtually all single-
ended equipments operating in the frequency domain (such as, signal generators and spectrum
analyzers) to be used for measuring differential circuits, which enables them to be free from post
measurement processes of mathematical calculations for achieving virtual-differential
measurement results. Three major topics for the development of the proposed measurement
strategy are listed below Figure 7-1.
Figure 7-1. Proposed balun embedded measurement for differential circuits.
• Compact sized broadband baluns • Algorithm for calibrating the effects of the embedded baluns • Evaluation of the measurements errors cause by the balun’s imperfections
Mixed-mode s-parameters, as reviewed in Chapter 2, were used throughout the design
and the characterization in this work. The SPICE-based extraction of the mixed-mode s-
parameters [7.1][7.2] were especially useful, because it allowed one to examine the relationship
107
between the extracted results and the circuit’s operation. Furthermore, the transient response of
the SPICE-based extraction enabled the simulation to account for the circuits’ non-linear effects
[7.1][7.2].
The developed compact sized broadband baluns were shown in Chapter 3, which were
realized using planar-type Marchand’s configuration [7.3]. Such configuration was chosen for its
large relative-bandwidth and compact structure. To achieve high performances, the optimum
values for the differential- and common-mode characteristic impedances of the Marchand
coupling were analytically derived using general transmission-line theories. For the case of
symmetric Marchand baluns, these values were shown to be 58.58 Ω for differential-mode and
85.36 Ω for common-mode. In order to achieve such large coupling, a new coupling structure
was proposed using a double-sided single-layer PCB surrounded by conductive fixtures. Large
coupling was easily achieved in this structure, because the majority of the electromagnetic field
propagates inside the PCB’s substrate of high dielectric constant (εr = 3.38) for differential-mode,
while that of the common-mode propagates in air (εr = 1). Two planar-type Marchand baluns
were designed using alternative layout arrangements. Both designs were integrated with
common-mode matching branch in order to minimize the errors associated with the common-
and cross-modes. Finally, the designed baluns were assembled onto the on-wafer probes. Using a
dual-through pattern connected to a dual-probe, the measurement results showed large 3 dB-
relative-bandwidths of 0.909 and 0.855.
In Chapter 4, a new set of ISS and an extraction method were proposed for characterizing
the 3-port error-box in 3 dB-coupled (including baluns) on-wafer measurements [7.4]. The
proposed method fully extracted all 9 mixed-mode s-parameters of the 3-port error-box, where in
the differential-mode measurements, the 4 differential-modes were used for calibration, and the
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remaining 5 common- and cross-modes were used for evaluating the measurement errors. This
method required less work compared to the previous method of using a dual-through pattern
connected to a dual-probe, and it is anticipated to be more accurate because it avoids the
reconnections of the coaxes leading to the VNA and avoids the errors associated with the
imperfection of the dual-through pattern, dual-probe, and VNA itself. The proposed method was
also shown to be more tolerant to measurement errors that occur when measuring the ISS,
because it used the pseudo-inverses of over-determined matrices. The proposed ISS was
manufactured by Cascade Microtech Inc., and it was put into test for a Marchand balun
embedded probe, where the extracted results showed good agreement with that of the previous
approach.
A new evaluation method for the measurement errors cause by the balun’s common- and
cross-modes (CXM) [7.5] was shown in Chapter 5. The proposed evaluation method used
random variables to account for the unknown parameters of the differential DUT, and displayed
the anticipated minimum and maximum of the s-parameters that can result under the pseudo-
worst conditions of the measurement errors caused by CXM. It was shown that the proposed
method can be used in post measurement processes, by which the users can be conveniently
informed of the measurement’s accuracy. The verification of the proposed algorithm was done
for a fully-differential amplifier that was being measured through the Rat-race type baluns. The
results showed that the DUT’s original and the calibrated 2x2 differential s-parameters were all
well within the anticipated minimum and maximum s-parameters provided by the proposed
method.
In efforts to further increase the bandwidth of the proposed measurement strategy, active
balun were developed operating up to tens of GHz in limited chip-areas, as shown in Chapter 6
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[7.6]. With the development of a calibration algorithm for unidirectional error-networks, this is
anticipated to become a promising solution for the proposed strategy, due to their large
bandwidth and compact size, which are far beyond what passive baluns can provide. The newly
proposed active balun used a cascode and cascade pair with a shared input transistor, hence, was
named as the combined cascode-cascade balun (C3-balun). The circuit contained no internal DC-
decoupling capacitors, so that the bandwidth’s lower-end frequency was only limited by the DC-
decoupling capacitors at the ports’ interfaces. The proposed C3-balun was designed in the IBM
8HP 130 nm BiCMOS process, where the layout’s compacted version was expected to fit in
limited chip-areas as small as 0.2 mm x 0.2 mm, which makes them well suitable for BIST
applications as well as general circuits requiring compact sized broadband baluns. For the input
power as high as 5 dBm, the measurement results (with the pads calibrated out) showed a large
bandwidth up to 17 GHz, where the imbalance of the differential output was less than 1.8 dB in
amplitude and less then 10 degrees in phase.
110
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BIOGRAPHICAL SKETCH
Kooho Jung received the BS and MS degrees in electrical engineering from Hanyang
University, Republic of Korea, in 1997 and 2001, respectively, where he had majored in device
physics for semiconductor optical-device under the supervision of Dr. Jongin Shim. He received
the Ph. D. degree in electrical engineering from the University of Florida, majoring in passive
and active broadband Baluns and RF calibration/measurement theories.
In 2001-2002, he was an associate engineer at Giga Electronic System Lab (National
Lab), Republic of Korea, where he worked on RF-to-Optic Link and circuit modeling for optical
devices. Concurrently, he had lectured in electromagnetics, electronic circuits, and engineering
mathematics at Kyungmin College. In 1999-2000, he served as the S4 NCOIC during his
mandatory military tour at the 102nd Military Intelligence, 8th US Army, stationed in Republic
of Korea, where he received 4 medals/awards from the Republic of Korea Army and the United
States Army.
Dr. Jung’s research interests also include RF CMOS power-amplifiers and
electromagnetics/circuit-modeling for passive devices. He received the Telecommunication
National Scholarship in 2002-2006, from the Ministry of Information and Communication,
Republic of Korea, and was awarded Fellowship from Texas Instruments in 2004.
![REFERENCES - INFLIBNETshodhganga.inflibnet.ac.in/bitstream/10603/20484/16/16_references.pdf[54] Brian Edward and Daniel Rees,” A broadband printed dipole with integrated balun”,](https://img.dokumen.tips/doc/110x75/5e98f191611cac583d2db71d/references-54-brian-edward-and-daniel-reesa-a-broadband-printed-dipole-with.jpg)
