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More Energy

Delivered to

the Battery

in the Same

Time

0 2000 4000 6000 8000 10000 11000

Time (sec)VBAT_CTO VBAT_Traditional IBAT_CTO IBAT_Traditional

3

2.5

2

1.5

1

0.5

0

ChargeCurrent(A)/Efficienc

y

Voltage(V)

4.4

4.2

4

3.8

3.6

3.4

3.2

3

2.8

2.6

2.4

Charge Cycle 4000mAh Battery 2A Charge Rate

`

`

SW

SYS

BAT

TS

VDRV

PGND

SDA

SCL

INT

BOOT

HOST

V I/O

IN

SystemLoad

TEMPPACK+

PACK-

D+

D-

VBUS

D+

D-

GND

bq24260

CD

PMID

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

bq24260bq24261,bq24262

SLUSBU4B DECEMBER 2013REVISED MARCH 2014

b q 2 4 2 6 x 3 A , 3 0 V , H o s t- C o n tr o l l e d S in g le -In p u t , S in g le C e l l S w itc h m o d e L i- Io n B a tt e r yC h a r g e r w ith P o w er P a t h M a n a g e m en t a n d U S B -O T G S u p p o r t

1 Features 2 Applications

1 Charge Time Optimizer (Enhanced CC/CV Smartphone and Tablets

Transition) for Faster Charging Handheld Products

Integrated FETs for Up to 3A Charge Rate at 5% Power Banks and External Battery PacksAccuracy and 93% Peak Efficiency Small Power Tools

Boost Capability to Supply 5V at 1A at IN for USB Portable Media Players and GamingOTG Supply

Integrated 17mPower Path MOSFET and 3 Descriptionoptional BGATE control to Maximize Battery Life The bq24260/bq24261/bq24262 are highly integratedand Instantly Startup From a Deeply Discharged single cell Li-Ion battery charger and system powerBattery or No Battery path management devices that supports operation

from either a USB port or wall adapter supply. The 30V Input Rating with Over-Voltage Protectionpower path feature allows the bq2426x to power theSupports 5V USB2.0/3.0 and 12V USB Powersystem from a high efficiency DC to DC converterDelivery (bq24261)while simultaneously and independently charging the Small Solution Size In a 2.4mm x 2.4mm 36-ball battery. The power path also permits the battery to

WCSP or 4mm x 4mm QFN-24 Package supplement the system current requirements whenthe adapter cannot. Many features are programmable Total Charging Solution Can be 50mm2 or lessusing the I2C interface. To support USB OTGwith WCSPapplications, the bq2426x is configurable to boost the Safe and Accurate Battery Managementbattery voltage to 5V and supply up to 1A at the

Functions Programmed Using I2C Interfaceinput. The battery is charged with three phases:

Charge Voltage, Current, Termination precharge, constant current and constant voltage.Threshold, Input Current Limit, VIN_DPM Thermal regulation prevents the die temperature from

exceeding 125C. Additionally, a JEITA compatibleThresholdbattery pack thermistor monitoring input (TS) is Voltage-based, JEITA Compatible NTCincluded to prevent the battery from charging outsideMonitoring Inputof its safe temperature range.

Thermal Regulation Protection for InputCurrent Control Device Information

Thermal Shutdown and Protection ORDER NUMBER PACKAGE BODY SIZE

bq24260/1/2YFF DSBGA (36) 2,4mm 2,4mm

bq24260/1/2RGE QFN (24) 4mm 4mm

4 Application Schematic

Charge Time Optimizer Effect

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents

8.5 Programming...........................................................261 Feat ures .................................................................. 18.6 Register Descriptions..............................................292 Appl icat ions ........................................................... 1

9 Applications and Implementation ...................... 353 Des cript ion ............................................................. 19.1 Application Information............................................354 Application Schematic .......................................... 19.2 Typical Applications ................................................35

5 Revision History..................................................... 2 10 Power Supply Recommendations .....................396 Terminal Configuration and Functions................ 310.1 Requirements for SYS Output ..............................39

7 Specifications......................................................... 510.2 Requirements for Charging...................................39

7.1 Absolute Maximum Ratings .....................................511 Layout................................................................... 40

7.2 Handling Ratings.......................................................511.1 Layout Guidelines .................................................40

7.3 Recommended Operating Conditions.......................511.2 Layout Example ....................................................40

7.4 Thermal Information .................................................612 Device and Documentation Support .................427.5 Electrical Characteristics...........................................6

12.1 Documentation Support .......................................427.6 Switching Characteristics........................................ 1012.2 Related Links ........................................................427.7 Typical Characteristics............................................1112.3 Trademarks...........................................................428 Detailed Description ............................................ 1212.4 Electrostatic Discharge Caution............................42

8.1 Overview ................................................................. 1212.5 Glossary ................................................................ 42

8.2 Functional Block Diagram .......................................1313 Mechanical, Packaging, and Orderable8.3 Feature Description................................................. 15

Information ........................................................... 438.4 Device Functional Modes........................................15

5 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (January 2014) to Revision B Page

Changed global format to new data sheet schema................................................................................................................ 1

Changed device number from "bq24262A" to "bq24262" throughout .................................................................................... 1

Changed VBATREGaccuracy for 0-125C, added 0-85C, and added mV specific numbers to Elec Charateristics table. .......7

Added D+/D- DETECTION specs to Electrical Characteristics table ..................................................................................... 8

AddedSwitching Characteristics ......................................................................................................................................... 10

AddedPower Supply Recommendations ............................................................................................................................ 39

AddedDevice and Documentation Support ........................................................................................................................ 42

Changed location of Ordering Information toMechanical, Packaging, and Orderable Information .................................... 43

Changes from Original (December 2013) to Revision A Page

Added specifications to Electrical Characteristics table pertaining to RGE package............................................................. 6

Added separate lines for IINLIM current for YFF and RGE packages. ..................................................................................... 8

Changed VDO_DRVspec MAX voltage from "500 mV" to "450 mV"......................................................................................... 8

Changed the wording of the Safety Timer description for clarification. ............................................................................... 21

Changed text in the F/S Mode Protocol section from "...to either transmit data to the slave (R/W bit 1) or receivedata from the slave (R/W bit 0" to "...to either transmit data to the slave (R/W bit 0) or receive data from the slave

(R/W bit 1" for clarification. ................................................................................................................................................... 27

2 Submit Documentation Feedback Copyright 20132014, Texas Instruments Incorporated

Product Folder Links: bq24260bq24261 bq24262
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Terminal Functio ns

TERMINALTERMINALNUMBERNUMBERTERMINAL

I/O DESCRIPTIONbq24260 bq24261/2NAME

YFF RGE YFF RGE

AGND F1 12, 20 F1 12, 20 Analog Ground. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.

BAT Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with at

F3-F6 8, 9 F3-F6 8, 9 I/O least 1F of ceramic capacitance. See Application section for additional details.

BGATE External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFETto provide a very low resistance discharge path. Connect BGATE to the gate of the external

F2 11 F2 11 OMOSFET. BGATE is low during high impedance mode or when no input is connected. If noexternal FET is required, leave BGATE disconnected. Do not connect BGATE to GND.

BOOT High Side MOSFET Gate Driver Supply. Connect 0.033F of ceramic capacitance (voltageC6 2 C6 2 I

rating > 10V) from BOOT to SW to supply the gate drive for the high side MOSFET.

CD IC Hardware Disable Input. Drive CD high to place the bq24260 in high-z mode. Drive CD lowC5 4 C5 4 I

for normal operation. CD is pulled low internally with 100k

D+ D4 14 I D+ and D Connections for USB Input Adapter Detection. When a source is initially connectedto the input during DEFAULT mode, and a short is detected between D+ and D, the input

D D3 15 I current limit is set to 1.5A. If a short is not detected, the USB100 mode is selected.

DRV Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. BypassDRV to PGND with at least 1F of ceramic capacitance. DRV may be used to drive external

D6 3 D6 3 Oloads up to 10mA. DRV is active whenever the input is connected and V IN> VUVLO and VIN>(VBAT+ VSLP).

IN DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port).C1-C4 19 C1-C4 19 I

Bypass IN to PGND with at least a 4.7F of ceramic capacitance.

INT Status Output. INT is an open-drain output that signals charging status and fault interrupts. INTpulls low during charging. INT is high impedance when charging is complete, disabled or the

E2 10 E2 10 O charger is in high impedance mode. When a fault occurs, a 128s pulse is sent out as aninterrupt for the host. INT is enabled /disabled using the EN_STAT bit in the control register.Connect INT to a logic rail through a 100k resistor to communicate with the host processor.

PGND A1-A6 21,22 A1-A6 21,22 Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.

PMID High Side Bypass Connection. Connect at least 1F of ceramic capacitance from PMID toB1 1 B1 1 I

PGND as close to the PMID and PGND terminals as possible.

PSEL Hardware Input Current Limit. In DEFAULT mode, PSEL selects the input current limit. Drive D4 14 I PSEL high to select USB100 (bq24261) or USB500 (bq24262) mode, drive PSEL low to select

1.5A mode.

SCL D2 16 D2 16 I I2C Interface Clock. Connect SCL to the logic rail through a 10k resistor. Do not leave floating.

SDA D1 17 D1 17 I/O I2C Interface Data. Connect SDA to the logic rail through a 10kresistor.

STAT Status Output. STAT is an open-drain output that signals charging status and fault interrupts.STAT pulls low during charging. STAT is high impedance when charging is complete, disabledor the charger is high impedance mode. When a fault occurs, a 128s pulse is sent out as an

E1 13 E1 13 Ointerrupt for the host. STAT is enabled /disabled using the EN_STAT bit in the control register.Connect STAT to a logic rail using an LED for visual indication or through a 100k resistor tocommunicate with the host processor.

SW Inductor Connection. Connect to the switched side of the external inductor. The inductanceB2-B6 23, 24 B2-B6 23, 24 O

must be between 1.5H and 2.2H.

SYS System Voltage Sense and Charger FET Connection. Connect SYS to the system output at theoutput bulk capacitors. Bypass SYS locally with at least 10F of ceramic capacitance. The SYS

E3-E6 6, 7 E3-E6 6, 7 Irail must have at least 20F of total capacitance for stable operation. See Application section foradditional details.

TS Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND.The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA

D5 5 D5 5 I compatibility. TS faults are reported by the I2C interface. Pull TS high to VDRV to disable the TSfunction if unused. See the NTC Monitorsection for more details on operation and selecting theresistor values.

Thermal There is an internal electrical connection between the exposed thermal pad and the PGNDPAD terminal of the device. The thermal pad must be connected to the same potential as the PGND

terminal on the printed circuit board. Do not use the thermal pad as the primary ground input forthe device. PGND terminal must be connected to ground at all times.



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www.ti.com SLUSBU4B DECEMBER 2013 REVISED MARCH 2014

7 Specifications

7.1 Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)

VALUEUNIT

MIN MAX

IN 1.3 30

BOOT, PMID 0.3 30Terminal Voltage Range (with

VSW 0.7 20respect to PGND)

BAT, BGATE, CD, D+, D-, DRV, INT, PSEL, SDA, SCL, STAT, 0.3 5SYS, TS

BOOT to SW 0.3 5 V

SW 4.5Output Current (Continuous) A

SYS, BAT (charging/ discharging) 3.5

Input Current (Continuous) 2.75 A

Output Sink Current STAT, INT 10 mA

Operating free-air temperature range 40 85C

Junction temperature, TJ

40 125

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltagevalues are with respect to the network ground terminal unless otherwise noted.

7.2 Handling RatingsMIN MAX UNIT

TSTG Storage temperature 300 C

HBM(2) 2 kVESD(1)

CDM(3) 500 V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges into the device.

(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allowssafe manufacturing with a standard ESD control process.(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

IN voltage range 4.2 28 (1)

IN operating voltage range (bq24260) 4.2 10VIN V

IN operating voltage range (bq24261) 4.2 13.2

IN operating voltage range (bq24262) 4.2 6.0

IIN Input current, IN input 2.5 A

ISW Output Current from SW, DC 3 A

IBAT, ISYS Charging 3A

Discharging, using internal battery FET 3

TJ Operating junction temperature range 0 125 C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW terminals. Atight layout minimizes switching noise.

Copyright 20132014, Texas Instruments Incorporated Submit Documentation Feedback 5


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7.4 Thermal Informationbq2426x

THERMAL METRIC(1) UNITYFF RGE(36 TERMINALS) (24 TERMINALS)

JA Junction-to-ambient thermal resistance 55.8 32.6

JCtop Junction-to-case (top) thermal resistance 0.5 30.5

JB Junction-to-board thermal resistance 10 3.3C/W

JT Junction-to-top characterization parameter 2.6 0.4

JB Junction-to-board characterization parameter 9.9 9.3

JCbot Junction-to-case (bottom) thermal resistance N/A 2.6

(1) For more information about traditional and new thermal metrics, see theIC Package Thermal Metrics application report,SPRA953.

7.5 Electrical Characteristics

Circuit ofFigure 7, VUVLO< VIN < VOVPAND VIN > VBAT+ VSLP, TJ= 40C to 125C and TJ= 25C for typical values (unless

otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CURRENTS

VUVLO < VIN < VOVPand VIN>VBAT+VSLP

15PWM switching

YFF Package: VUVLO< VIN < VOVPand VIN>VBAT+VSLP 6.5 mAPWM NOT switchingIIN Supply current for control

RGE Package: VUVLO < VIN < VOVPand VIN>VBAT+VSLP 6.65PWM NOT switching

0C< TJ< 85C, VIN = 5V, High-Z Mode 250 A

0C< TJ< 85C, VBAT= 4.2 V, VIN= 5V, 15SCL, SDA = 0V or 1.8V, High-Z Mode

Battery discharge current inYFF Package: 0C< TJ< 85C, VBAT= 4.2 V, VIN = 0V,IBAT_HIZ High Impedance mode, (BAT, 77 ASCL, SDA = 0V or 1.8V

SW, SYS)

RGE Package: 0C< TJ< 85C, VBAT= 4.2 V, VIN = 0V, 80SCL, SDA = 0V or 1.8V

POWER-PATH MANAGEMENT

VMINSYS VMINSYS VMINSYS

VSYSREG(LO) System Regulation Voltage VBAT< VMINSYS V+ 80 mV + 1 00mV + 1 20 mV

Battery FET turned off, no charging, VBATREG VBATREG VBATREGVSYSREG(HI) System Regulation Voltage VVBAT> 3.5V +2.2% +2.5% +2.77%

Minimum System VoltageVMINSYS VBAT+ VDO(SYS_BAT)< 3.5V 3.44 3.5 3.55 VRegulation Threshold

Deglitch time, VMINSYStDGL(MINSYS_CMP) 8 mscomparator rising

Enter supplement mode VBATVBSUP1 VBAT> VBUVLO Vthreshold 20mV

Exit supplement mode VBATVBSUP2 VBAT> VBUVLO Vthreshold 5mV

Current Limit, Discharge orILIM(DISCH) VLIM(BGATE)= VBAT VSYS 4 6 ASupplement Mode

Deglitch Time, OUT ShorttDGL(SC1) Circuit during Discharge or Measured from IBAT= 7A to FET off 250 s

Supplement Mode

Recovery time, OUT ShorttREC(SC1) Circuit during Discharge or 2 s

Supplement Mode

Battery Range for BGATE2.5 4.5 V

Operation


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bq24260bq24261,bq24262


Electrical Characteristics (continued)


otherwise noted)


BATTERY CHARGER

YFF 17 25Measured from BAT to SYS,Internal battery charger

RON(BAT-SYS) mMOSFET on-resistance VBAT= 4.2V, High-Z mode RGE 32 47

Charge Voltage Operating in voltage regulation, Programmable Range 3.5 4.44 V

RGE Package VoltageTJ= 0C to 50C -0.5% 0.5%Regulation Accuracy

RGE Package VoltageTJ= 0C to 85C -0.7% 0.7%Regulation Accuracy

YFF Package VoltageTJ= 0C to 85C -0.75% 0.75%Regulation Accuracy

VBATREG RGE and YFF PackageTJ= 0C to 125C -1.0% 1.0%Voltage Regulation Accuracy

YFF Package VoltageTJ= 25C -29.2 28.1Regulation Accuracy

YFF Package VoltageTJ= 0C to 85C -32.0 29.3 mVRegulation Accuracy

YFF Package VoltageTJ= 0C to 125C -40.2 29.3Regulation Accuracy

Fast Charge Current Range VBATSHRT VBAT< VBAT(REG) 500 3000 mA

ICHARGE 500 mA ICHARGE 1A 10% 10%Fast Charge CurrentAccuracy ICHARGE> 1000 mA 5% 5%

VBATSHRT Battery short circuit threshold 1.9 2 2.1 V

VBATSHRT_HYS Hysteresis for VBATSHRT Battery voltage falling 100 mV

Deglitch time for battery shortVBATrising or falling 1 msto fastcharge transition

Battery short circuit chargeIBATSHRT VBAT< VBATSHRT 33.5 50 66.5 mAcurrent

ITERM 50 mA 30% 30%

ITERM Termination charge current 50 mA < ITERM < 200 mA 15% 15%

ITERM 200 mA 15% 10%

Both rising and falling, 2-mV over-drive,Deglitch time for chargetDGL(TERM) 32 mstermination tRISE, tFALL=100ns

VRCH Recharge threshold voltage Below VBATREG 100 120 150 mV

tDGL(RCH) Deglitch time VBATfalling below VRCH, tFALL=100ns 32 ms

Battery detection voltagethresholdVDET(SRC1) During current source (Turn IBATSHRT off) VRCH V

(TE = 1)

VRCHVDET(SRC2) During current source (Turn IBATSHRT on) V 200mV

VDET(SNK) During current sink VBATSHRT V

Battery detection currentIDETECT before charge done (sink Termination enabled (TE = 1) 7 mA

current)

Battery detection timetDETECT(SRC) Termination enabled (TE = 1) 2 s(sourcing current)

Battery detection time (sinkingtDETECT(SNK) Termination enabled (TE = 1) 250 mscurrent)



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otherwise noted)


INPUT CURRENT LIMITING

IINLIM=USB100 90 95 100

IINLIM=USB500 450 475 500

IINLIM=USB150 125 140 150

IINLIM=USB900 800 850 900

IINLIM=1.5A 1425 1500 1575

USB charge mode, VIN= 5V, Current IINLIM=2A, YFFIINLIM Input current limiting threshold mA1850 2000 2150pulled from SW Package

IINLIM=2A, RGE 1850 2000 2200Package

IINLIM=2.5A, YFF 2300 2500 2700Package

IINLIM=2.5A, RGE 2225 2500 2825Package

Input based DPM thresholdVIN_DPM 4.2 11.6 VCharge mode, programmable via I

2Crange

VIN_DPMthreshold Accuracy 3% 3%

VDRVBIAS REGULATOR

VDRV Internal bias regulator voltage VIN>5V 4.3 4.8 5.3 V

IDRV DRV Output Current 0 10 mA

DRV Dropout VoltageVDO_DRV IIN= 1A, VIN = 4.2V, IDRV= 10mA 450 mV(VIN VDRV)

STATUS OUTPUT (STAT, INT)

Low-level output saturationVOL IO= 10 mA, sink current 0.4 Vvoltage

IIH High-level leakage current V STAT= VINT= 5V 1 A

INPUT PINS (CD, PSEL)

VIL Input low threshold 0.4 V

VIH Input high threshold 1.4 V

RPULLDOWN CD pull-down resistance CD Only 100 k

Deglitch for CD and PSEL CD or PSEL rising/falling 100 s

D+/D- DETECTION

VD+_SRC D+ Voltage Source 0.5 0.6 0.7 V

ID+_SRC D+ Current Source 7 14 A

ID-_SINK D- Sink Current 50 100 150 A

D-, Switch Open -1 1 AID_LKG Leakage Current into D+/D-

D+, Switch Open -1 1 A

VD+_LOW D+ Comparator Threshold 0.85 0.9 0.95 V

VD-_LOW D- Comparator Threshold 250 325 400 mV

RD-_DWN D- Pull-Down Resistance 14.25 24.8 k



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otherwise noted)


PROTECTION

VUVLO IC active threshold voltage VINrising 3.2 3.3 3.4 V

VUVLO_HYS IC active hysteresis VIN falling from above VUVLO 300 mV

Battery Undervoltage LockoutVBATUVLO VBATfalling, 100mV Hysteresis 2.4 2.6 Vthreshold

Sleep-mode entry threshold,VSLP 2.0 V < VBAT< VBATREG, VIN falling 0 40 120 mVVIN-VBAT

Deglitch time, BAT abovetDGL(BAT) VBATUVLObefore SYS starts to 1.2 ms

rise

VSLP_HYS Sleep-mode exit hysteresis VINrising above VSLP 40 100 190 mV

Deglitch time for supply risingtDGL(VSLP) Rising voltage, 2-mV over drive, tRISE=100ns 30 msabove VSLP+VSLP_HYS

bq24260 10.1 10.5 10.9Input supply OVP threshold

VOVP IN rising, 100mV hysteresis bq24261 13.6 14 14.4 Vvoltagebq24262 6.25 6.5 6.75

Good Battery MonitorVBATGD VINRising 3.51 3.7 3.89 VThreshold (BQ24260/1 only)

Deglitch time, VIN OVP intDGL(BUCK_OVP) IN falling below VOVP 30 msBuck Mode

1.03 1.05 1.07 VBOVP Battery OVP threshold voltage VBATthreshold over VOREG to turn off charger during charge VVBATREG VBATREG VBATREG

% ofVBOVP_HYS VBOVP hysteresis Lower limit for VBATfalling from above VBOVP 1 VBATREG

tDGL(BOVP) BOVP Deglitch Battery entering/exiting BOVP 8 ms

ICbCLIMIT Cycle-by-cycle current limit VSYSshorted 4.1 4.5 4.9 A

TSHTDWN Thermal trip 150 C

Thermal hysteresis 10 C

TREG Thermal regulation threshold Input current begins to cut off 125 C

Safety Timer Accuracy 20% 20%

PWM

YFF Package: Measured from IN to SW 75 120 mInternal top MOSFET on-RDSON_Q1 resistance RGE Package: Measured from IN to SW 80 135 m

YFF Package: Measured from SW to PGND 75 115 mInternal bottom N-channelRDSON_Q2 MOSFET on-resistance RGE Package: Measured from SW to PGND 80 135 m

fOSC Oscillator frequency 1.35 1.5 1.65 MHz

DMAX Maximum duty cycle 95%

DMIN Minimum duty cycle 0

BATTERY-PACK NTC MONITOR (1)

VHOT High temperature threshold VTSfalling, 2% VDRVHysteresis 27.3 30 32.6 %VDRV

VWARM Warm temperature threshold VTS falling, 2% VDRVHysteresis 36.0 38.3 41.2 %VDRV

VCOOL Cool temperature threshold VTSrising, 2% VDRVHysteresis 54.7 56.4 58.1 %VDRV

VCOLD Low temperature threshold VTSrising, 2% VDRVHysteresis 58.2 60 61.8 %VDRVTSOFF TS Disable threshold VTSrising, 4% VDRVHysteresis 80 85 %VDRV

tDGL(TS) Deglitch time on TS change Applies to VHOT, VWARM, VCOOLand VCOLD 50 ms

I2C COMPATIBLE INTERFACE

VIH Input low threshold level VPULL-UP=1.8V, SDA and SCL 1.3 V

VIL Input low threshold level VPULL-UP=1.8V, SDA and SCL 0.4 V

VOL Output low threshold level IL=5mA, sink current 0.4 V

IBIAS High-Level leakage current VPULL-UP=1.8V, SDA and SCL 1 A

tWATCHDOG 30 50 s

tI2CRESET 700 ms



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otherwise noted)


OTG BOOST SUPPLY

Quiescent current duringIQBAT_ BOOST 3.3V

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0 2 4 6 8 10 12 14 1 6

Input Voltage - V

--2

0

2

4

6

8

10

12

14

16

Input

urrent-mA

Input Current ( A)

-100

0

100

200

300

400

500

600

700

InputCurrent(

A)

3 5 7 9 11 13 15

Input Voltage (V)

TA=25C

TA=60C

TA=0C

-0.5

-1.0

0.0

-2.0

-3.0

-1.5

-2.5

VBATAccuracy(%)

IBAT (A)

10.5 21.50

40

50

60

70

80

90

100

2 2.5 3 3.5 4 4.5

Efficiency(%)

VBAT (V)

VIN=5V

VIN=7V

VIN=10V

VIN=12V

90

85

80

75

70

95

Load Current (A)

0.5 1 1.5 2 2.5 30

Efficiency(%)

-10

-8

-6

-4

-2

0

2

4

6

8

10

2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5

VBAT (V)

ChargeCurrentAccuracy(%)

TA=25C

TA=0C

TA=85C

TA=60C

bq24260bq24261,bq24262


7.7 Typical Characteristics

Figure 1. Charge Current vs Battery VoltageFigure 2. Efficiency vs Output Current

Figure 3. Efficiency vs Battery VoltageFigure 4. VBAT Accuracy vs IBAT 4.2V Setting

Figure 6. Input IQ with Hi-Z EnabledFigure 5. Input IQ - No Battery, No System



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8 Detailed Description

8.1 Overview

The bq24260/bq24261/bq24262 are highly integrated single cell Li-Ion battery charger and system power pathmanagement devices targeted for space-limited, portable applications with high capacity batteries. The single cellcharger has a single input that supports operation from either a USB port or wall adapter supply for a versatilesolution.

The power path management feature allows the bq2426x to power the system from a high efficiency DC to DCconverter while simultaneously and independently charging the battery. The charger monitors the battery currentat all times and reduces the charge current when the system load requires current above the input current limit orthe adapter cannot support the required load, causing the adapter voltage to fall (V IN_DPM). This allows for propercharge termination and timer operation. The system voltage is regulated to the battery voltage but will not dropbelow 3.5V (VMINSYS). This minimum system voltage support enables the system to run with a defective or absentbattery pack and enables instant system turn-on even with a totally discharged battery or no battery. The power-path management architecture also permits the battery to supplement the system current requirements when theadapter cannot deliver the peak system currents. The power-path feature coupled with VIN-DPM, enables the useof many adapters with no hardware change. The charge parameters are programmable using the I2C interface.To Support USB OTG applications, the bq2426x is configurable to boost the battery voltage to 5V at the input. Inthis mode, the bq2426x supplies up to 1A and operates with battery voltages down to 3.3V.

The battery is charged using a standard Li-Ion charge profile with three phases: precharge, constant current andconstant voltage. In all charge phases, an internal control loop monitors the IC junction temperature and reducesthe input current to prevent the junction temperature from rising above 125C. Additionally, a voltage-based,JEITA compatible battery pack thermistor monitoring input (TS) is included that monitors battery temperature andautomatically changes charge parameters to prevent the battery from charging outside of its safe temperaturerange.



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IN

SW

+

+

BOOT

DRV

SYS

BAT

VMINSYS

BGATE

STAT

+

SDA

SCL

+

+

VDRV

TS

TS COLD

TS HOT

TS WARM

TS COOL

1C/

0.5C

DISABLE

VSYSREGComparator

+

DC-DC CONVERTER PWM LOGIC,

COMPENSATION AND BATTERY

FET CONTROL

VBATREG 0.14V

+VIN

4.8V

Reference

VBATSHRT

+

VBATSCComparator

VBAT

Termination

Comparator

CHARGE

CONTROLLER

w/ Timers

+

VSUPPLY

Termination

Reference

VBATREG 0.12V+

Recharge Comparator

VBAT

VSYSEnable LinearCharge

PGND

D-

Q3

Q2

Q1

ICbCLimit

D+ USBAdapter

Detection

Circuitry

1.5A /

USB100

I2C

Interface

References

Enable

IBATSHRT

+

Supplement COMPARATOR

VBATVBSUP

VSYS

Hi-Impedance Mode

PSEL

bq24261/2

bq24260

Sleep

Comparator

VBAT+VSLP

Enable HiZ in

DEFAULT mode

+

IINLIM

VINDPM

VSYS(REG)

IBAT(REG)

VBAT(REG)

DIE Temp

Regulation

IBAT

VBATGD

Start Recharge

Cycle

DISABLE

+VIN

OVP

Comparator

VINOVP

VBATOVP

+

VBOVPComparator

VBAT

CD Hi-Z

Mode

PMID

INT

bq24260bq24261,bq24262


8.2 Functional Block Diagram

Figure 7. Block Diagram in Charging Mode



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IN

SW

BOOT

DRV

VDRV

SYS

STAT

DC-DCCONVERTERPWM LOGIC

ANDCOMPENSATION

4.8-V

Reference

Digital Control

+

VBIASBattery Short

Circuit

PGND

Q3

Q1

Low Side CurrentLimit Comparator

INT

+

V AmpBOOST

SDA

SCL

IBLIMITI

VBAT

+

Burst Mode ExitComparator

VIN_BOOST

Battery SC Comparator

+

ILIM(DISCH)

+

VBOOSTOVP Comparator

VBOOSTOVP

+

Burst Mode EnterComparator

VBURST_ENT

+

Boost Short CircuitComparator

VBOOSTSHRT

BGATE

TS

CD

PMID

I C

interface

2

VBURST_EXT Q2

BATHi-Z

Mode


Functional Block Diagram (continued)

Figure 8. Block Diagram in Boost Mode



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bq24260bq24261,bq24262


8.3 Feature Description

The bq24260/bq24261/bq24262 are highly integrated single cell Li-Ion battery charger and system power pathmanagement devices that supports operation from either a USB port or wall adapter supply. The power pathfeature allows the bq2426x to power the system from a high efficiency DC to DC converter while simultaneouslyand independently charging the battery. The power path also permits the battery to supplement the systemcurrent requirements when the adapter cannot. Many features are programmable using the I2C interface. To

support USB OTG applications, the bq2426x is configurable to boost the battery voltage to 5V and supply up to1A at the input. The battery is charged with three phases: precharge, constant current and constant voltage.Thermal regulation prevents the die temperature from exceeding 125C. Additionally, a JEITA compatible batterypack thermistor monitoring input (TS) is included to prevent the battery from charging outside of its safetemperature range

The Device Functional Modes section explains these features in detail.

8.4 Device Functional Modes

8.4.1 High Impedance Mode

High Impedance mode (Hi-Z mode) is the low quiescent current state for the bq2426x. During Hi-Z mode, thebuck converter is off, and the battery FET and BGATE are on. SYS is powered by BAT. The bq2426x is inHi-Z mode when VIN < VUVLO, the HZ_MODE bit in the I

2C is '1' or the CD terminal is driven high. Hi-Z mode

resets the safety timer.

The bq2426x contains a CD input that is used to disable the IC and place the bq2426x into high-impedancemode. Drive CD low to enable the bq2426x and enter normal operation. Drive CD high to disable chargeand place the bq2426x into high-impedance mode. CD is internally pulled down to PGND with a 100kresistor. When exiting Hi-Z mode, charging resumes in approximately 110ms.

8.4.2 Battery Only Connected

When the battery is connected with no input source, the battery FET is turned on. After the battery risesabove VBATUVLO and the deglitch time, tDGL(BAT), the SYS output starts to rise. In this mode, the current is notregulated; however, there is a short circuit current limit. If the short circuit limit (ILIM(DISCHG)) is reached for thedeglitch time (tDGL(SC)), the battery FET is turned off for the recovery time (tREC(SC)). After the recovery time,the battery FET is turned on to test and see if the short has been removed. If it has not, the FET turns offand the process repeats until the short is removed. This process protects the internal FET from over

current. If an external FET is used for discharge, the body diode prevents the load on SYS from beingdisconnected from the battery and tDGL(BAT)is not applicable.

8.4.3 Input Connected

8.4.3.1 Input Voltage Protection in Charge Mode

Sleep Mode

The bq2426x enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entrythreshold, VBAT+VSLP, and VIN is higher than the undervoltage lockout threshold, VUVLO. In sleep mode,the input is isolated from the battery. This feature prevents draining the battery during the absence ofVIN. When VIN < VBAT+ VSLP, the bq2426x turns off the PWM converter, turns the battery FET andBGATE on, sends a single 128s pulse on the STAT and INT outputs and the STATx and FAULT_x bitsof the status registers are updated in the I2C. Once VIN > VBAT+ VSLP, the STATx bits are cleared and the

device initiates a new charge cycle. The FAULT_x bits are not cleared until they are read in the I2

C andthe sleep condition no longer exists.

Input Voltage Based Dynamic Power Management (VIN-DPM)



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800us/div

2A/div

2A/div

500mV/div

2A/div

1V/div

ISYS

IBAT

IIN

VSYS(3.6V Offset)

VIN(5V Offset)

Normal Charging (1A)SYS enters supplement mode to ensure SYS load is supported

SYS load removed,normal charging

resumes

Input voltage regulated to VIN_DPM

Input current limit reduced to avoid crashing adapter


Device Functional Modes (continued)

During normal charging process, if the input power source is not able to support the programmed ordefault charging current, the supply voltage deceases. Once the supply drops to V IN_DPM (default 4.2V),the charge current limit is reduced to prevent the further drop of the supply. When the IC enters thismode, the charge current is lower than the set value and the DPM_STATUS bit is set. This featureensures IC compatibility with adapters with different current capabilities without a hardware change.

Figure 9shows the VIN-DPM behavior to a current limited source. In this figure the input source has a 2Acurrent limit and the device is charging at 1A. A 2.5A load transient then occurs on V SYS causing theadapter to hit its current limit and collapse, while VSYSgoes from VSYSREG(LO)to VMINSYS. If the 2X timer isset, the safety timer is extended while VIN-DPM is active. Additionally, termination is disabled.

Figure 9. bq24260 VIN-DPM

Input Over-Voltage Protection

The built-in input over-voltage protection protects the bq2426x and downstream components connectedto SYS and/or BAT against damage from overvoltage on the input supply (Voltage from V IN to PGND).When VIN > VOVP, the bq2426x turns off the PWM converter immediately. After the deglitch timetDGL(BUCK_OVP), an OVP fault is determined to exist. During the OVP fault, the bq2426x turns the batteryFET and BGATE on, sends a single 128s pulse is sent on the STAT and INT outputs and the STATxand FAULT_x bits are updated in the I 2C. Once the OVP fault is removed, the STATx bits are clearedand the device returns to normal operation. The FAULT_x bits are not cleared until they are read in theI2C after the OVP condition no longer exists.

The OVP threshold for the bq24260 is 10.5V for operation from standard adapters while the bq24261 isset to 14V to enable operation from 12V sources. The bq24262 OVP is set to 6.5V to operate fromstandard USB sources.

8.4.3.2 Charge Profile

When a valid input source is connected (VIN>VUVLO and VBAT+VSLP

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ermination

RegulationVoltage

PrechargePhase

Current RegulationPhase

Voltage RegulationPhase

Charge Current

BatteryVoltage

V

(3.6V)SYS

System Voltage

Linear Chargeto MaintainMinimumSystem

Voltage

V

(2.0V)BATSHORT

IBATSHORT

50mA Linear Chargeto Close Pack

Protector

Battery FET (Q3) isON

BatteryFET

is OFF

RegulationCurrent

bq24260bq24261,bq24262



The bq2426x supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. Charging isdone through the internal battery MOSFET. There are 6 loops that influence the charge current; constant currentloop (CC), constant voltage loop (CV), thermal regulation loop, minimum system voltage loop (MINSYS), inputcurrent limit and VIN-DPM. During the charging process, all six loops are enabled and the one that is dominanttakes control. The minimum system output feature regulates the system voltage to V SYSREG(LO), so that startup is

enabled even for a missing or deeply discharged battery. Figure 10shows a typical charge profile including theminimum system output voltage feature.

Figure 10. Typical Charging Profile of bq2426x with Termination Enabled

8.4.4 Battery Charging Process

When the battery is deeply discharged or shorted, the bq2426x applies a I BATSHRT current to close the batteryprotector switch and bring the battery voltage up to acceptable charging levels. During this time, the battery FETis off and the system output is regulated to VSYSREG(LO). Once the battery rises above VBATSHRT, the chargecurrent is regulated to the value set in the I2C register. The battery FET is linearly regulated to maintain thesystem voltage at VSYSREG(LO). Under normal conditions, the time spent in this region is a very short percentageof the total charging time, so the linear regulation of the charge current does not affect the overall chargingefficiency for very long. If the die temperature does heat up, the thermal regulation loop reduces the input currentto maintain a die temperature at 125C. If the current limit for the SYS output is reached (limited by the input


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current limit, VIN-DPM, or 100% duty cycle), the SYS output drops to the VMINSYS output voltage. When thishappens, the charge current is reduced to ensure the system is supplied with all the current that is needed whilemaintaining the minimum system voltage. If the charge current is reduced to 0mA, pulling further current fromSYS causes the output to fall to the battery voltage and enter supplement mode (see the Dynamic Power PathManagement section for more details).

Once the battery is charged enough that the system voltage rises above V SYSREG(LO) (approximately 3.5V), thebattery FET is turned on fully and the battery is charged with the full programmed charge current set by the I 2Cinterface, ICHARGE. The charge current is regulated to ICHARGE until the voltage between BAT and PGND reachesthe regulation voltage. The voltage between BAT and PGND is regulated to V BATREG (CV mode) while the chargecurrent naturally tapers down as shown inFigure 10. During CV mode, the SYS output remains connected to thebattery. The impedance of the battery FET is increased to 4x of the fully on value when IBAT falls below ~350mAto provide increased accuracy during termination. This will show a small rise in the SYS voltage when the RDSONincreases below ~350mA.

When termination is enabled (TE bit is '1'), the bq2426x monitors the charging current during the CV mode. Oncethe charge current tapers down to the termination threshold, I TERM, and the battery voltage is above the rechargethreshold, the bq2426x terminates charge, turns off the battery charging FET and enters battery detection (seeBattery Detection section for more details). The system output is regulated to the V SYSREG(HI)and supports the fullcurrent available from the input. The battery supplement mode is available to supply any SYS load that cannot

be supported by the input source (see the Dynamic Power Path Management section for more details). Thetermination current level is programmable. To disable the charge current termination, the host sets the chargetermination bit (TE) of charge control register to 0. Refer to I 2C section for details. When termination is disabled,VBATis continuously regulated to VBATREG. Termination is also disabled when any loop is active other than CC orCV. This includes VINDPM, input current limit, or thermal regulation. Termination is also disabled during TSwarm/cool conditions and when the LOW_CHG bit is set to '1'.

A charge cycle is initiated when one of the following conditions is detected:

1. The battery voltage falls below the VBATREG-VRCHthreshold.

2. IN Power-on reset (POR)

3. CE bit toggle or RESET bit is set (Host controlled)

4. CD terminal is toggled

8.4.5 Charge Time OptimizerThe CC to CV transition is enhanced in the bq2426x architecture. The "knee" between CC and CV is very sharp.This enables the charger to remain in CC mode as long as possible before beginning to taper the charge current(CV mode). This provides a decrease in charge time as compared to older topologies.

8.4.6 Battery Detection

When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT ispulled from VBAT for tDETECT(SNK) to verify there is a battery. If the battery voltage remains above VDETECT for thefull duration of tDETECT(SNK), a battery is determined to present and the IC enters Charge Done. If VBAT fallsbelow VDETECT, a Battery Not Present fault is signaled, the charge parameters are reset (VBATREG, ICHARGE andITERM) and battery detection continues. The next cycle of battery detection, the bq2426x turns on IBATSHRT fortDETECT(SRC). If VBATrises to VDET(SRC1), the current source is turned off and a No Battery condition is registered.In order to keep VBAT high enough to close the battery protector, the current source turns on if V BAT falls to

VDET(SRC2). The source cycle continues for tDETECT(SRC). After tDETECT(SRC), the battery detection continues throughanother current sink cycle. Battery detection continues until charge is disabled, the bq2426x enters high-z modeor a battery is detected. Once a battery is detected, the fault status clears and a new charge cycle begins. Withno battery connected, the BAT output will transition from VRCH to PGND with a high period of tDETECT(SRC) and alow period of tDETECT(SNK). See Figure 22 in the Application Curves section. Battery detection is not performedwhen termination is disabled.



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VSYS

DPPM loop active

SupplementMode

IBAT

IIN

ISYS

2000mA

1800mA

800mA

0mA

1500mA

~850mA

0mA

1A

0mA

200mA

3.6V3.5V

~3.1V

bq24260bq24261,bq24262



8.4.7 Battery Overvoltage Protection (BOVP)

If the battery is ever above the battery OVP threshold (VBOVP), the battery OVP circuit shuts the PWM converteroff and the battery FET is turned on to discharge the battery to safe operating levels. A battery OVP mostcommonly occurs when the bq2426x returns to DEFAULT mode after a watchdog timer expiration or RESET bitwritten to '1'. In this condition, the VBATREG is reset and may be below the battery voltage. Other conditions may

be when the input is initially plugged in before I2C communication is established or TS WARM conditions or whenwriting the VBATREG to less than the battery voltage. The battery OVP condition is cleared when the batteryvoltage falls below the hysteresis of VBOVP either by the battery discharging or writing the VBATREG to a highervalue. When a battery OVP event exists for tDGL(BOVP), the bq2426x turns the battery FET and BGATE on, sendsa single 128s pulse on the STAT / INT outputs and the STATx and FAULT_x bits are updated in the I 2C. Oncethe BOVP fault is removed, the STATx bits are cleared and the device returns to normal operation. TheFAULT_x bits are not cleared until they are read in the I2C after the BOVP condition no longer exists.

8.4.8 Dynamic Power Path Management

The bq2426x features a SYS output that powers the external system load connected to the battery. This output isactive whenever a valid source is connected to IN or BAT. When VSYS > VSYSREG(LO), the SYS output isconnected to VBAT. If the battery voltage falls to VMINSYS, VSYS is regulated to the VSYSREG(LO) threshold tomaintain the system output even with a deeply discharged or absent battery. In this mode, the SYS output

voltage is regulated by the buck converter and the battery FET is linearly regulated to regulate the charge currentinto the battery. The current from the supply is shared between charging the battery and powering the systemload at SYS. The dynamic power path management (DPPM) circuitry of the bq2426x monitors the current limitscontinuously and if the SYS voltage falls to the VMINSYS threshold, it adjusts charge current to maintain theminimum system voltage and supply the load on SYS. If the charge current is reduced to zero and the loadincreases further, the bq2426x enters battery supplement mode. During supplement mode, the battery FET isturned on and VBAT= VSYSwhile the battery supplements the system load.

Figure 11. Example DPPM Response (VSupply=5V, VBAT = 3.1V, 1.5A Input Current Limit)



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8.4.9 Battery Discharge FET (BGATE)

The bq2426x contains a MOSFET driver to drive an external discharge FET between the battery and the systemoutput. This external FET provides a low impedance path for supplying the system from the battery. ConnectBGATE to the gate of the external discharge P-channel MOSFET. BGATE is on (low) under the followingconditions:

1. No input supply connected.

2. HZ_MODE = 1

3. CD terminal = 1

8.4.10 DEFAULT Mode

DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the followingsituations:

1. When the charger is enabled and VBAT

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bq24260bq24261,bq24262



8.4.13 Power Source Selector Input (PSEL, bq24261/2 only)

The bq24261/2 contains a PSEL input that is used to program the input current limit during DEFAULT mode.Drive PSEL high to indicate a USB source is connected to the input and program the 100mA (bq24261) or500mA (bq24262) current limit for IN. Drive PSEL low to indicate that an AC Adapter is connected to the input.When PSEL is low, the IC starts up with a 1.5A input current limit. Once an I2C write is done and the device is in

HOST mode, the PSEL has no effect on the input current limit until the watchdog timer expires and returns thebq2426x to DEFAULT mode.

8.4.14 Safety Timer and Watchdog Timer in Charge Mode (bq24260/1 only)

At the beginning of charging process, the bq24260/1 starts the safety timer. This timer is active during the entirecharging process. If charging has not terminated before the safety timer expires, the IC enters suspend modewhere charging is disabled. When a safety timer fault occurs, a single 128s pulse is sent on the STAT and INToutputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. The CE bit, Hi-Z mode,or power must be toggled in order to clear the safety timer fault. The safety timer duration is selectable using theTMR_X bits in the Safety Timer Register/ NTC Monitor register. When the safety timer is active, changing thesafety timer duration resets the safety timer. The bq2426x also contains a 2X_TIMER bit that enables the 2xtimer function to prevent premature safety timer expiration when the charge current is reduced by a load on SYSor a NTC condition. When 2X_TIMER is enabled, the timer runs at half speed when any loop is active other than

CC or CV. This includes VINDPM, input current limit, or thermal regulation. The timer also runs at half speed duringTS warm/cool conditions and when the LOW_CHG bit is set to '1'.

In addition to the safety timer, the bq24260/1 contains a 30-second (t WATCHDOG) watchdog timer that monitors thehost through the I2C interface. Once a write is performed on the I2C interface, a watchdog timer is started. Thewatchdog timer is reset by the host using the I2C interface. This is done by writing a 1 to the reset bit(TMR_RST) in the control register. The TMR_RST bit is automatically set to 0 when the watchdog timer isreset. This process must continue as long as the input is connected in order to maintain the register contents. Ifthe watchdog timer expires, the IC enters DEFAULT mode where the default register values are loaded, thesafety timer restarts at 2 minutes once charging continues. The I 2C may be accessed again to reinitialize thedesired values and restart the watchdog timer. The watchdog timer flow chart is shown inFigure 12.



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Start Safety Timer

No

Start watchdog timer

No

Yes

WD timer expired?No

Yes

Receivedsoftware watchdog

RESET?

No

Yes

Safety timer expired?

No

Yes Safety timerfault

Charging suspendedEnter suspended

modeFault indicated inSTAT registers

Yes

Charge Done?I < ICHG TERM

No

STAT = HiUpdate STAT

bits

Yes

Reset watchdog timer

Safety timer expired? Safety timerfault

Charging suspendedEnter suspended

modeFault indicated in

STAT registers

No

Yes

I C Writeperformed?

2

STAT = HiUpdate STAT

bits

Charge Done?I < ICHG TERM

Reset to default

values in I Cregister

Restart 2 minsafety timer

2



Figure 12. The Watchdog Timer Flow Chart for bq24260

8.4.15 LDO Output (DRV)

The bq24260 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and othercircuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or the USB transceivercircuitry. The maximum value of the DRV output is 5.3V so it ideal to protect voltage sensitive USB circuits. TheLDO is on whenever a supply is connected to the input of the bq24260. The DRV is disabled under the followingconditions:

1. VSUPPLY < UVLO

2. VSUPPLY < VBAT+ VSLP

3. Thermal Shutdown


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DRV

COLD

V1

VRHI

1 1

RLO RCOLD

DRV

COLD HOT

VDRV DRV

HOT COLD

1 1V RCOLD RHOTV V

RLOV

RHOT 1 RCOLD 1V V

4.1 V

T1(0 C)

4.15 V

4.25 V

0.5 C

1.0 C

Portion of spec not covered by TSImplementation on bq2426x

T2(10 C)

T3(45 C)

T4(50 C)

T5(60 C)

Charging Current

VBAT

CoolCold Warm Hot

bq24260bq24261,bq24262



8.4.16 External NTC Monitorin g (TS)

The I2C interface allows the user to easily implement the JEITA standard for systems where the battery packthermistor is monitored by the host. Additionally, the bq24260 provides a flexible, voltage based TS input formonitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at asafe temperature during charging. The JEITA specification is shown inFigure 13.

Figure 13. Charge Current During TS Condition s

To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (TNTC 60C). These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOTthresholds in the EC table. Charging is suspended and timers are suspended when VTS < VHOT or VTS > VCOLD.When VCOOL < VTS < VCOLD, the charging current is reduced to half of the programmed charge current. WhenVHOT < VTS < VWARM, the battery regulation voltage is reduced by 140mV from the programmed regulationthreshold. The TS function is disabled by connecting TS directly to DRV (VTS> VTSOFF).

The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TSconnected to the center tap to set the threshold. The connections are shown in Figure 14. The resistor values arecalculated using the following equations:

(1)

(2)



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DISABLE

TEMPPACK+

PACK

+

+

+

+

VDRV

TS COLD

TS HOT

TS WARM

TS COOL

V

140 mV

BATREG

TS

bq2426x

RHI

RLO

1 x Charge/0.5 x Charge

VDRV

RLO RHI 0.383RWARM

RLO RLO 0.383 RHI 0.383

RLO RHI 0.564RCOOL

RLO RLO 0.564 RHI 0.564



Where:

VCOLD= 0.60 VDRVVHOT= 0.30 VDRV

(3)

(4)

Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at coldtemperature.

The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTCresistances for a selected resistor divider are calculated usingEquation 3and Equation 4.

Figure 14. TS Circuit

8.4.17 Thermal Regulation and Protection

During the charging process, to prevent overheating in the chip, bq2426x monitors the junction temperature, T J,

of the die and reduces the input current once TJ reaches the thermal regulation threshold, TREG. The inputcurrent is reduced to zero when the junction temperature increases about 10C above TREG. Once the inputcurrent is reduced to 0, the system current is reduced while the battery supplements the load to supply thesystem. When the input current is completely reduced to 0 and TJ>125C, this is may cause a thermal shutdownof the bq2426x if the die temperature rises too high. At any state, if TJexceeds TSHTDWN, bq24260 stops chargingand disables the buck converter. During thermal shutdown mode, PWM is turned off, all timers are suspended,and a single 128s pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the statusregisters are updated in the I2C. The charge cycle resumes when TJfalls below TSHTDWN by approximately 10C.



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bq24260bq24261,bq24262



8.4.18 Charge Status Outpu ts (STAT, INT)

The STAT/INT output is used to indicate operation conditions for bq2426x. STAT/INT is pulled low duringcharging when EN_STAT bit in the control register is set to 1. When charge is complete or disabled, STAT/INTis high impedance. When a fault occurs, a 128-s pulse (interrupt) is sent out to notify the host. The status ofSTAT/INT during different operation conditions is summarized in Table 1. STAT/INT drives an LED for visual

indication or can be connected to the logic rail for host communication. The EN_STAT bit in the control register isused to enable/disable the charge status for STAT/INT. The interrupt pulses are unaffected by EN_STAT and willalways be shown.

Table 1. STAT Terminal Summary

CHARGE STATE STAT and INT BEHAVIOR

Charge in progress and EN_STAT=1 Low

Other normal conditions High-Impedance

Charge mode faults: Timer faults, sleep mode, VIN over voltage, VIN < UVLO or Sleep 128-s pulse, then High Impedancemode, BOVP, thermal shutdown, No Battery and Battery Temperature faults

8.4.19 Boost Mode Operation

In HOST mode, when the operation mode bit (BOOST_EN) in the control register is set to 1, bq2426x operatesin boost mode and delivers 5V to IN to supply USB OTG devices connected to the USB connector. Boostoperation can start with VBAT between 3.45V to 4.5V, and will maintain boost output until VBAT falls to 3.3V. INsupplies up to 1A to power these devices. It is not recommended to operate boost mode when the batteryvoltage is less than 3.3V. Proper operation is not guaranteed.

8.4.19.1 Chip Disable Input During Boo st Mode (CD)

The bq2426x contains a CD input that is used to disable the IC and place the bq2426x into high-impedancemode. CD must be low to enter boost mode. Driving CD high during boost mode places the bq2426x into high-zmode and resets the BOOST_EN bit in the I2C. When CD is high, the buck converter is off, and the battery FETand BGATE are turned on. CD is internally pulled down to GND with a 100kresistor.

8.4.19.2 PWM Controller in Boost Mode

Similar to charge mode operation, in boost mode the IC switches at 1.5MHz to regulate the voltage at IN to 5V.The voltage control loop is internally compensated to provide enough phase margin for stable operation with thefull battery voltage range and up to 1A.

In boost mode, the cycle-by-cycle current limit is set to 4A or 2A (depending on the I2C setting) to provideprotection against short circuit conditions. If the cycle-by-cycle current limit is active for 8ms, an overloadcondition is detected and the device exits boost mode, and signals an over-current fault. Additionally, dischargecurrent limit (ILIM(DISCHG)) is active to protect the battery from overload. Synchronous operation and burst modeare used to maximize efficiency over the full load range.

The bq2426x will not enter boost mode unless the IN voltage is less than the UVLO. When the boost function isenabled, the bq2426x enters a linear mode to bring IN up to the battery voltage. Once V IN > (VBAT 1V), thebq2426x begins switching and regulates IN up to 5V. If VIN does not rise to within 1V of VBAT within 8ms, anover-current event is detected and boost mode is exited and a boost mode over-current event is announced, theBOOST_EN bit is reset to 0 and the STAT_x and FAULT_x bits in the Status/ Control register are updated.

8.4.19.3 Burst Mode during Light Load

In boost mode, the IC operates using burst mode to improve light load efficiency and reduce power loss. Duringboost mode, the PWM converter is turned off when the device reaches minimum duty cycle and the outputvoltage rises to VBURST(ENT) threshold. This corresponds to approximately a 75mA inductor current. The converterthen restarts when VIN falls to VBURST(EXT). SeeFigure 30in the Typical Operating Characteristics for an examplewaveform.



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8.4.19.4 Watchdog Timer in Boost Mode

During boost mode, the watchdog timer is active. The watchdog timer works the same as in charge mode. Writea 1 to the TMR_RST reset bit in the control register. If the watchdog timer expires, the IC resets theEN_BOOST bit to 0, signals the fault pulse on the STAT and INT terminals. The FAULT_x bits read "Low SupplyFault" as this is a higher priority fault than the WD timer.

8.4.19.5 STAT/ INT During Bo ost ModeDuring boost mode, the STAT and INT outputs are high impedance. Under fault conditions, a 128s pulse is sentout to notify the host of the error condition.

8.4.19.6 Protection in Boost Mode

8.4.19.6.1 Output Over-Voltage Protection

The bq2426x contains integrated over-voltage protection on the IN terminal. During boost mode, if anover-voltage condition is detected (VIN > VBOOSTOVP), after deglitch tDGL(BOOST_OVP), the IC turns off thePWM converter, resets EN_BOOST bit to 0, sets fault status bits and sends out a fault pulse on STATand INT. The converter does not restart when VIN drops to the normal level until the EN_BOOST bit isreset to 1.

8.4.19.6.2 Output Over-Current Protection

The bq2426x contains over current protection to prevent the device and battery damage when IN isoverloaded. When an over-current condition occurs, the cycle-by-cycle current limit limits the current fromthe battery to the load. If the overload condition lasts for 8ms, the overload fault is detected. When anoverload condition is detected, the bq2426x turns off the PWM converter, resets EN_BOOST bit to 0,sets the fault status bits and sends out the fault pulse on STAT and INT. The boost operation starts onlyafter the fault is cleared and the EN_BOOST bit is reset to 1 using the I 2C.

8.4.19.6.3 Battery Voltage Protection

During boost mode, when the battery voltage is below the minimum battery voltage threshold, VBATUVLO,the IC turns off the PWM converter, resets EN_BOOST bit to 0, sets fault status bits and sends out afault pulse on STAT and INT. Once the battery voltage returns to the acceptable level, the boost startsonly after the EN_BOOST bit is set to 1. Proper operation below 3.3V down to the VBATUVLOis not

specified.

8.5 Programming

8.5.1 Serial Interface Descriptio n

The bq24260 uses an I2C compatible interface to program charge parameters. I2C is a 2-wire serial interfacedeveloped by NXP (formerly Philips Semiconductor, see I2C-Bus Specification, Version 5, October 2012). Thebus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDAand SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/Oterminals, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls thebus. The master is responsible for generating the SCL signal and device addresses. The master also generatesspecific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmitsdata on the bus under control of the master device.

The bq2426x device works as a slave and supports the following data transfer modes, as defined in the I2CBus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to thebattery charge solution, enabling most functions to be programmed to new values depending on theinstantaneous application requirements. The I2C circuitry is powered from IN when a supply is connected. If theIN supply is not connected, the I2C circuitry is powered from the battery through BAT. The battery voltage muststay above VBATUVLOwith no input connected in order to maintain proper operation.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as theF/S-mode in this document. The bq24260/1/2 device only supports 7-bit addressing. The device 7-bit address isdefined as 1101011 (0x6Bh).



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DATA

CLK

Data LineStable;

Data Valid

Changeof DataAllowed

START Condition

DATA

CLK

STOP Condition

S P

bq24260bq24261,bq24262

www.ti.com SLUSBU4B DECEMBER 2013