Boolean Algebra

112/04/21 Jackie Kan - 2007 ([email protected]/[email protected])http://linton.1d24h.com/~jackiekan/ 1112/04/21 NTU DSD (Digital System Design)

20071

Boolean Algebra

112/04/21 Jackie Kan - 2007 ([email protected]/[email protected])http://linton.1d24h.com/~jackiekan/ 2

NOT Operation

The NOT operation (or inverse, or complement operation) replaces a Boolean value with its complement:

0’ = 1 1’ = 0 A’ is read as NOT A or

Complement A Boolean representation

F(A) = A’ = A Truth Table

U1A

DM7404

1 2A A’

Inverter symbol

A01

A’10


AND Operation

The AND operation is a function of two variables (A, B) Boolean function representation

F(A,B) = A • B = A * B = AB When both A and B are ‘1’, then F is ‘1’

0 • 0 = 0 0 • 1 = 0 1 • 0 = 0 1 • 1 = 1

Truth Table

A00

B01

11

01

Y0001

U2A

DM7408

1

23

B

Y

and symbol

A


OR Operation

The OR operation is a function of two variables (A, B) Boolean function representation

F(A,B) = A + B When either A or B are ‘1’, then F is ‘1’

0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 1

Truth Table

U3A

DM7432

1

23

B

Y

or symbol

AA00

B01

11

01

Y0111


U11

XOR2

12

3

XOR Operation

A00

B01

11

01

Y0110

A

B

Y=A B

XOR gate is usual in logic circuits that do binary addition/subtraction.

Note that: F = A B

= A’B + AB’


Boolean Functions

More complex Boolean functions can be created by combining basic operations

U3A

DM7432

1

23

U4A

DM7404

1 2 F(A,B) = A’ + BA A’

B

A00

B01

11

01

A’1100

F(A,B) = A’ + B1101


7408 – Quad 2-Input AND Gate IC

7432 – Quad 2-Input OR Gate IC


7404 – Hex Inverter

7486 – Quad 2-Input Exclusive-OR Gate IC


Laws and Theorems of Boolean Algebra

單變數定理 (Single Variables Theorem) Identity

X + 0 = X X * 1 = X

Null Element X + 1 = 1 X * 0 = 0

Idempotent Theorem X + X = X X * X = X

Theorem of Complementarity X + X’ = 1 X * X’ = 0

Involution Theorem (X’)’ = X


Laws and Theorems of Boolean Algebra

多變數定理 (Multiple Variables Theorem) Commutative law

X + Y = Y + X XY = YX

Associative law (X + Y) + Z = X + (Y + Z) = X + Y + Z (XY)Z = X(YZ) = XYZ

Distributive law X(Y + Z) = XY + XZ X + (YZ) = (X + Y)(X + Z)

Simplification theorems XY + XY’ = X (uniting) X + XY = X (absorption) (X + Y’)Y = XY (X + Y)(X + Y’) = X X(X + Y) = X XY’ + Y = X + Y

Consensus theorem XY + X’Z + YZ = XY + X’Z (X + Y)(X’ + Z)(Y + Z) = (X + Y)(X’ + Z)


Proof of The Consensus Theorem

XY + X’Z + YZ = XY + X’Z

XY + X’Z + YZ = XY + X’Z + 1·YZ = XY + X’Z + (X + X’)YZ= XY + X’Z + XYZ + X’YZ= XY + XYZ + X’Z + X’YZ= XY(1 + Z) + X’Z(1 + Y)= XY·1 + X’Z·1= XY + X’Z


Boolean Algebra and Truth Table

利用真值表證明兩邊的式子範例：

證明 x•(y + z) = (x • y) + (x • z)

x y z y + z x •(y + z)

x •y x •z (x • y) + (x•z)

0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0

0 1 0 1 0 0 0 0

0 1 1 1 0 0 0 0

1 0 0 0 0 0 0 0

1 0 1 1 1 0 1 1

1 1 0 1 1 1 0 1

1 1 1 1 1 1 1 1

x(y + z) = xy + xz


Simplification / Minimization ( 簡化 )

Simplification or Minimization tries to reduce the number of terms in a Boolean equation via use of basic theorems

A simpler equation will mean: Less gates will be needed to implement the equation Could possibly mean a faster gate-level implementation

Will use algebraic techniques at first for simplification Graphical method called K-maps Computer methods for simplification are widely used in industry


Example: full adder's carry out function Cout = A' B Cin + A B' Cin + A B Cin' + A B Cin

= A' B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin

= (A' + A) B Cin + A B' Cin + A B Cin' + A B Cin

= (1) B Cin + A B' Cin + A B Cin' + A B Cin

= B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin

= B Cin + A (B' + B) Cin + A B Cin' + A B Cin

= B Cin + A (1) Cin + A B Cin' + A B Cin

= B Cin + A Cin + A B (Cin' + Cin)

= B Cin + A Cin + A B (1)

= B Cin + A Cin + A B

Minimization Example


200715

Computation in Digital Logic Circuit


Half Adder / Full Adder

S = A’B + AB’ Cout = AB

Full Adder

0 0 01 0 12 1 03 1 1

A B S0110

Cout0001

A

BS

COUT

U20

XOR2

12

3

U21

AND2

12

3

HALFADDER

A

B

Cout

S

FULLADDER

AB

Cout

SCin

00 0 001 0 102 1 003 1 114 0 015 0 116 1 017 1 1

A B Cin S01101001

Cout

00010111


Full Adder with Truth Table

S = A’B’Cin + A’BCin’ + ABCin +

AB’Cin’

= A’(B’Cin + BCin’) + A(B’Cin’ + BCin)

= A’(B ⊕ C) + A(B ⊕ C)’= A⊕(B⊕Cin)

= (A⊕B)⊕Cin

Cout

= A’BCin + AB’Cin + ABCin’ + ABCin

= BCin + ACin + AB

00 0 001 0 102 1 003 1 114 0 015 0 116 1 017 1 1

A B Cin S01101001

Cout

00010111

F = A B = A’B + AB’


Circuit of Full Adder

S = A⊕B⊕Cin = (A⊕ Cin)⊕B

Cout = AB + BCin + ACin

U5 XOR2

12

3 U6 XOR2

12

3

U7 AND2

12

3

A

S

U10 OR3

1234

Cin

U8 AND2

12

3

B

Cout

U9 AND2

12

3


Behavior Level of Full Adder in Verilog Code

module full_adder (a, b, ci, s, co);input a, b, ci;output s, co; assign s = a ^ b ^ ci; assign co = (a & b) | (a & ci) | (b & ci);endmodule

Gate Level of Full Adder in Verilog & VHDL Code

module full_adder (a, b, ci, s, co);input a, b, ci;output s, co;wire NET1, NET2, NET3, NET4 ; xor ( NET1, a, b ); xor ( s , NET1, ci ); and ( NET2, a, b ); and ( NET3, a, ci ); and ( NET4, b, ci ); or ( co, NET2, NET3, NET4 );endmodule

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY full_add IS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; c_in : IN STD_LOGIC; sum : OUT STD_LOGIC; c_out : OUT STD_LOGIC); END full_add;

ARCHITECTURE behv OF full_add ISBEGIN sum <= a XOR b XOR c_in; c_out <= (a AND b) OR (c_in AND (a OR b)); END behv;


Verilog Code of 4-Bit Addermodule full_adder (a, b, ci, s, co);input a, b, ci;output s, co; assign s = a ^ b ^ ci; assign co = (a & b) | (a & ci) | (b & ci);endmodule

module f_fadder (a, b, s, co);input [3:0] a;input [3:0] b;output [3:0] s;output co;wire net1, net2, net3; full_adder f1(a[0],b[0],0,s[0],net1); full_adder f2(a[1],b[1],net1,s[1],net2); full_adder f3(a[2],b[2],net2,s[2],net3); full_adder f4(a[3],b[3],net3,s[3],co);endmodule

FULLADDER

A B

Cout S

Cin

FULLADDER

A B

Cout S

Cin

FULLADDER

A B

Cout S

Cin

FULLADDER

A B

Cout S

Cin

A[3] A[2] A[1] A[0]B[3] B[2] B[1] B[0]

S[3] S[2] S[1] S[0]

0


Answer of Quiz 1

1) Please complete this truth table

X Y Z XY Y’+Z’ X(Y’+Z’) (XY)’(XY)’+

ZX’Y XZ’ X’Y + XZ’

0 0 0 0 1 0 1 1 0 0 0

0 0 1 0 1 0 1 1 0 0 0

0 1 0 0 1 0 1 1 1 0 1

0 1 1 0 0 0 1 1 1 0 1

1 0 0 0 1 1 1 1 0 1 1

1 0 1 0 1 1 1 1 0 0 0

1 1 0 1 1 1 0 0 0 1 1

1 1 1 1 0 0 0 1 0 0 0


Answer of Quiz 2

2) Please design an 8-bit adder by drawing block diagram, schematic and related Verilog code

FULLADDER

A B

Cout S

Cin

FULLADDER

A B

Cout S

Cin

FULLADDER

A B

Cout S

Cin

FULLADDER

A B

Cout S

Cin

A[3] A[2] A[1] A[0]B[3] B[2] B[1] B[0]

S[3] S[2] S[1] S[0]

0

FULLADDER

A B

Cout S

Cin

FULLADDER

A B

Cout S

Cin

FULLADDER

A B

Cout S

Cin

FULLADDER

A B

Cout S

Cin

A[7] A[6] A[5] A[4]B[7] B[6] B[5] B[4]

S[7] S[6] S[5] S[4]


Answer of Quiz 2 module full_adder (a, b, ci, s, co); input a, b, ci; output s, co; assign s = a ^ b ^ ci; assign co = (a & b) | (a & ci) | (b & ci); endmodule

module f_fadder (a, b, s, co); input [7:0] a; input [7:0] b; output [7:0] s; output co; wire net1, net2, net3, net4, net5, net6, net7; full_adder f1(a[0],b[0],0,s[0],net1); full_adder f2(a[1],b[1],net1,s[1],net2); full_adder f3(a[2],b[2],net2,s[2],net3); full_adder f4(a[3],b[3],net3,s[3],net4); full_adder f5(a[4],b[4],net4,s[4],net5); full_adder f6(a[5],b[5],net5,s[5],net6); full_adder f7(a[6],b[6],net6,s[6],net7); full_adder f8(a[7],b[7],net7,s[7],co); endmodule


200724

Basic Input / Output Device

Input Devices


Logic Switch

DigitalCircuit

SW1

SWITCH

1 2

0

VCC

R1R

High Input Resistance

1

0ClosedOpen Open

Circuit

Logic Levels


Normally Open / Closed Pushbutton

DigitalCircuit

R1R

VCC

SW2

SW TACT-SPST

0

1

0ClosedOpen Open

ReleasePress

DigitalCircuit

SW3

SW TACT-SPST

R1R

VCC

0

1

0Closed Open

ReleasePress

Closed


Example 4x4 Keypad


Keyboard Scan

1

1

1

1

0

1

1

1

1

0

1

1

1

1

0

1

1

1

1

0


Keyboard Scan

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1


PS/2 Keyboard


Make Code & Break Code


Button Bounce

Analog Waveform

Digital Waveform

Debounce

Documents

Boolean Algebra