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eBook: Materials Matter in LED Applications

Performance Improvement• High Performance Electronic Interconnect Materials

Characterization – Techniques & Challenges…

• Effect of Thermal Properties of Die Attach Materials on Performance of High Power Blue LEDs…

• LED Thermal Management System – High Thermal and High Reliability Materials…

• High Thermal, High Operating Temperature Interconnects for Ultra-High Power LEDs…

• LED Die Attach Technologies – Considerations…

Reliability Improvement• Low Voiding Reliable Solder Interconnects for LED Packages

on Metal Core PCBs…

• Assembly Interconnect Reliability in Solid State Lighting Applications – Part 1…

• Impact of Substrate Materials on Reliability of High Power LED Assemblies…

• Fatigue Life Prediction Model for LEDs on Metal Core PCBs With Pb-Free Solder Alloys…

• Characterization of Board Warpage and Optimization for Linear LED Lighting Assemblies v2…

Materials Enabling Flip-Chip LED & Flexible Form Factors• Flip-Chip LED Assembly by Solder Stamping/Pin-Transfer…

• Enabling the Use of PET Flexible Substrates for LED Lighting Applications…

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PERFORMANCE IMPROVEMENT

Originally published in the Proceedings of SMTA International, Rosemont, IL, September 17‐ September 21, 2017.

HIGH PERFORMANCE ELECTRONIC INTERCONNECT MATERIALS CHARACTERIZATION - TECHNIQUES & CHALLENGES

Nicholas Herrick, Amit Patel, Gyan Dutt and Ranjit Pandher

Alpha Assembly Solutions South Plainfield, NJ, USA

[email protected] ABSTRACT High-power and LED devices generate significant heat that, if not efficiently removed from the assembly, leads to lower operating efficiency and / or lower luminous flux and shorter lifetime. Because the majority of heat is transported through the device interconnect layer, the thermal resistance of the heat path significantly impacts overall device performance. Higher thermal conductivity interconnect materials significantly decrease the thermal resistance of the stack. The effects of high performance interconnect materials are easy to observe and affect end user performance and reliability (e.g. by increasing total luminous flux, efficiency, and color stability). These effects become more pronounced as these devices are over driven and are particularly important in power electronics and UV LED applications. In this study, a series of interconnect materials, including sintered nano-silver (Fortibond™), SAC305 and a hybrid silver sintering epoxy (Atrox®), were used to assemble high-power AlGaInP/Si LEDs for laboratory testing. Junction temperature, thermal resistance, thermal conductivity, total luminous flux, peak wavelength, and efficiency were measured according to JESD51-1 and LM-79-08. In this paper we discuss the technical and design challenges associated with making accurate thermal resistance measurements across a multi-layered stack. The results of this laboratory study show the comparative performance of identical devices assembled with a variety of interconnect materials. A field example showing enhanced UV LED device performance with high thermal interconnect material is presented.

Key words: UV LED, die attach, sintered silver, thermal resistance, interconnects INTRODUCTION Proper cooling of LEDs during operation requires high performance interconnects to conduct heat away from the p-n junction (the light generating region). Doing so lowers the junction temperature of the LED and increases the efficiency. While 20-60% of the electrical power is converted to photons, the remainder is converted to heat. In laboratory settings and in luminaires convection across the die is negligible or non-existent. Instead, nearly all the heat moves down through the die, die attach layer, substrate trace, dielectric, and then the substrate base material (typically FR4, aluminum, or copper, see Figure 1) [1] [2]. It then moves

through the thermal interface material and into the heat sink where it is exhausted to ambient. Any of these layers can serve as a bottleneck for the heat transfer, but especially layers towards the top of the materials stack where the cross sectional area is still small. Therefore, these layers must have high thermal conductivity to effectively cool the LED [3]. The thermal performance of the whole LED stack is measured as thermal resistance (Rth) in units of degrees Kelvin/Watt (or, equivalently, degrees Celsius/Watt).

SINTERED SILVER AS DIE ATTACH MATERIAL The sintered nano-silver paste (brand name Fortibond) used here is designed for pressure-less die attach and assembly of electronics components, including high power LEDs. The material uses typical SMT manufacturing processes such as printing and dispensing. It must, however, be sintered at high temperature in an oven. During high temperature sintering the silver paste bakes off its solvents while adjacent nanoparticles diffuse together to form a porous structure as shown in Figure 2. Once the silver paste is printed, dispensed, or stamped, the LED is placed on the deposit via a standard SMT pick-n-place machine or a die bonder. This is possible because this sintered silver paste is so-called pressure-less – meaning many kilograms of pressure aren’t needed during the sintering process in order to make the silver bond. The thermal conductivity of bulk silver is 429 𝑊𝑊/𝑚𝑚 ∙ 𝐾𝐾, but because of nano-pores the expected thermal conductivity of sintered silver is lower. Nano-flash thermal conductivity measurement of bulk sintered silver is approximately 230

Figure 1. LED heat flow pathways.


𝑊𝑊/𝑚𝑚 ∙ 𝐾𝐾. A sintered silver die attach layer’s thermal conductivity will be based on the size of the nano-silver particles, the solvents and resins used in the paste, assembly pressure, and sintering temperature and duration.

HYBRID SILVER SINTERING MATERIALS Another high-performance die attach technology is known as hybrid silver sintering [4]. These are epoxy-based materials that combine the high thermal conductivity of nano-silver sintered materials and the adhesion properties of silver-filled epoxies. They are composed of micron-sized silver flakes and organic and polymer components. During curing they pull adjacent flakes together promoting increased contact and sintering. They have high thermal conductivities (up to 150 𝑊𝑊/𝑚𝑚 ∙ 𝐾𝐾) but are assembled pressure-less and adhere to bare substrates (whereas solder and nano-silver sintering pastes require metallized surfaces). Curing hybrid silver sintering materials is done in two steps in a box oven, with typical peak temperatures of 200-250 C for 1-2 hours. Alpha’s hybrid silver material is named Atrox. SUBSTRATE DESIGN FOR HIGH PERFORMANCE MEASUREMENTS Compared to all other LED thermal stack materials, dielectrics have high thermal resistance. This limits the junction temperature measurement precision and completely precludes measurement of high performance die attach materials. Using a metal substrate with an active pedestal eliminates the dielectric layer and permits a direct heat path from the LED to the heat sink (see Figure 3). In our high performance interconnect studies we use dielectricless substrates. High-power vertical LEDs are attached directly to the metal substrate via a die attach material. Heat conduction from the die then moves in approximately a one-dimensional fashion into the substrate. By varying the thickness of the die attach layer we can isolate its contribution to the material stack.

Substrates are clamped to a thermoelectric heat sink held at a constant 25 C. A thin ribbon of highly-conformable indium (thermal conductivity K = 81.8 𝑊𝑊/𝑚𝑚 ∙ 𝐾𝐾) is used as the thermal interface material.

MEASUREMENT TECHNIQUES Overview The thermal resistance of an LED stack can be measured directly via electrical and optical tests. Both have established industry standards. Depending on the sophistication of the test equipment greater precision and accuracy can be achieved. Higher precision methods measure the thermal conductivity of a layer, such as the die attach material. Junction Temperature The junction temperature of the LED is the temperature of the p-n junction. This shouldn’t be confused with the solder point temperature, which is the temperature of the solder pad. We measure the junction temperature of LEDs via the dynamic voltage method outlined in JESD 51-1 [5]. To calculate the junction temperature it is necessary to first measure the temperature sensitivity parameter of the LED, which is also known as the k-factor. The k-factor is determined by measuring the voltage across an LED at a series of known temperatures when operated at low power. To avoid self-heating, the current through the LED should be below the self-heating threshold of the diode. JESD 51-1 specifies this value as below the knee of the diode’s IV curve. For best results, and in all but the most simplified circumstances, LEDs should be placed in an oven to ensure a known temperature at the junction. The exception to this situation is if the LED die attach stack is sufficiently thermally conductive to allow for k-factor calibration on a heat plate. In general, LED packages have too much thermal

Figure 2. Electron microscope image of sintered silver microsctructure showing characteristic micro-pores.

Figure 3. An active pedestal with no dielectric layer. The die here is directly attached to the copper substrate via a sintered silver die attach material. This improves experimental precision and allows for measurement of high performance die attach materials.


resistance for heat plate calibration. Bare LED chips from the same bin have very similar k-factors, therefore measuring a few gives a reasonable approximation for the remainder. Once the k-factor is known, current is passed through the LED and it is allowed to come to thermal equilibrium with a heat sink held at a constant temperature. Once thermal equilibrium has been reached, the voltage is measured to determine the electrical power. The LED heating current is then switched off and a sensing current is applied. As the LED cools to the temperature of the heat sink, the voltage rises to a reference voltage that corresponds to the heat sink temperature. Depending on the total thermal resistance of the LED assembly, the duration of this cooling behavior can be from hundreds of microseconds to many seconds. The voltage of the LED immediately after the current switches is called the sensing voltage. The following equation is then used to calculate the junction temperature:

𝑇𝑇𝑗𝑗 = 𝑉𝑉𝑅𝑅−𝑉𝑉𝑆𝑆𝑘𝑘

+ 𝑇𝑇𝐻𝐻𝐻𝐻.

• 𝑉𝑉𝑅𝑅: is the reference voltage of the LED. • 𝑉𝑉𝐻𝐻: is the sensing voltage of the LED after switching

from heating to sensing current. • 𝑘𝑘: is the temperature sensitive parameter in units of

volts/degree Celsius. • 𝑇𝑇𝐻𝐻𝐻𝐻: is the temperature of the heat sink, in Celsius.

We measured the junction temperature of the LED at several operating currents and also measured the optical efficiency of the LED in an integrating sphere. The thermal power of the LED is the difference between the electrical power and the optical power. This is the amount of electrical energy per unit time that is converted to heat. Knowing this quantity and the junction temperature at several operating currents, we can calculate the thermal resistance of the LED assembly and test system:

𝑇𝑇𝑗𝑗 = 𝑅𝑅𝑡𝑡ℎ ∙ 𝑃𝑃ℎ + 𝑇𝑇𝐻𝐻𝐻𝐻. • 𝑇𝑇𝑗𝑗 : is the junction temperature, in Celsius. • 𝑃𝑃ℎ: is the thermal power of the LED, in Watts. • 𝑅𝑅𝑡𝑡ℎ: is the thermal resistance of the LED assembly, in

C/W (equivalent to K/W). • 𝑇𝑇𝐻𝐻𝐻𝐻: is the temperature of the heat sink, in Celsius.

Die Attach Influence on Junction Temperature Figure 4 shows a comparison of die attach materials used in the assembly of high-power vertical red LEDs on dielectricless substrates. These samples were constructed identically with only the die attach material differing. The bond line thicknesses of the samples were chosen to represent the ideal process conditions for that particular material so as to form a better picture of in-use performance (see Table I). Nano-silver particle size, paste rheology, and processing parameters all determine the ultimate thermal performance of the sintered silver die attach materials. In Figure 4, two sintered silver materials (AL12P and PDA1307D) show an

8% difference in junction temperature at 3.0 Watts. These are compared to Atrox hybrid silver sintering epoxy which is 5% higher at the same electrical power input and SAC305 which is extrapolated to be 10% higher. Differences between die attach materials become more pronounced the higher the electrical power.

Bond Line Thickness The thickness of the die attach layer, alternately referred to as the bond line thickness (BLT), is a key property of an LED assembly. Thicker BLTs relieve thermal stresses, but contribute to higher overall thermal resistance. We measured the BLT of our LEDs in two ways, via cross section and a vertical measuring microscope.

Cross sectioning - The LED is cross sectioned to allow direct optical inspection of the bond line. This is the most accurate way to measure bond line thickness, but does not allow for die tilt measurements because it is a single slice through the die. Figure 3 is an example of an LED assembly cross section.

Vertical measuring microscope – A measuring microscope was used to optically measure the bond line thickness of an intact LED assembly. This type of microscope has a very

Figure 4. Junction temperature measurements of LEDs assembled with different die attach materials. For each material the ideal bond line thickness was used (see Table I).

25

27

29

31

33

35

37

39

41

0 0.5 1 1.5 2 2.5 3

Junc

tion

Tem

pera

ture

(C)

Electrical Power (W)

Die Attach Material Comparison

Solder (SAC305) Fortibond PDA1307D

Atrox Hybrid Ag Fortibond AL12P

Material BLT Range # of LEDs Fortibond AL12P 20-32 um 9 Fortibond PDA1307D 20-32 um 8 Atrox Hybrid Ag 13-35 um 6 Solder (SAC305) 53-68 um 10

Table I. Die attach material BLTs and sample quantities used in Figure 4.


narrow depth of field and a calibrated focus axis. By focusing the microscope on a surface, zeroing the z-axis, and then refocusing on a new surface, the user can measure the vertical distance between the two.

This procedure requires knowing some information about the LED package, specifically the thickness of the LED die and the planar location of the bottom of the die attach layer. If these are known, then by measuring the vertical distance between the two and subtracting the die thickness we can calculate the BLT. Performing these measurements for all four corners gives an indication of the die tilt. In practice, this method is accurate to within +/-5 µm.

Thermal Resistance Results We measured the junction temperature of 80 high-power vertical red LEDs assembled on dielectric-less substrates. As in Figure 4 (a subset of these samples), dies were assembled identically except for the die attach material.

Plotting these LEDs’ thermal resistances versus their BLTs shows comparative performance of the thermal stacks, shown in Figure 5. The slope of the fitted lines are proportional to the thermal conductivity of the die attach materials. Sintered silver shows the lowest thermal resistance values – especially at high BLTs where the effect is exaggerated. The measurements overlap at low BLTs. This is likely due to low measurement accuracy because Figure 4 showed a clear difference between die attach materials at high electrical powers. Generally, though, thinner bond lines have better thermal performance and smaller differences between die attach materials.

Optical Measurements In addition to measuring the junction temperature and thermal resistance, there are a few optical measurements that are useful in the LED industry. These measurements were performed in an integrating sphere according to LM-79-08 [6].

A 0.5 m diameter integrating sphere was used in 2π mode, meaning that the LED was placed on the edge of the interior of the sphere as shown in Figure 6. For calibration, two radiometrically calibrated halogen lamps were used to serially calibrate the integrating sphere and then thermoelectric heat sink’s test surface and mounted LED (Figure 7).

Figure 5. Comparison of die attach materials used to assemble red vertical LEDs. Thermal resistance (Rth) values refer to the total Rth of the LED assembly and heat sink.

4

4.5

5

5.5

6

6.5

7

7.5

8

0 50 100 150

Ther

mal

Res

istan

ce (

K/W

)

Bond Line Thickness (µm)

Die Attach Material Rth Comparison

Fortibond PDA1307D Solder (SAC305)

Atrox Hybrid Ag Fortibond AL12P

Figure 6. Integrating sphere used to measure optical emissions. A heat plate mounted on the outside of the sphere holds the LED sample at a constant temperature during tests. This integrating sphere is set up to perform 2π measurements.

Figure 7. 2π sphere geometry for performing spectroradiometric measurements on LEDs [5]. In our case we utilized a secondary sphere as the fiber output instead of a cosine-collector. Two radiometrically calibrated lights were used to calibrate first the sphere and then the LED and socket.


A linear CCD-spectroradiometer gathered light via a small satellite sphere and optical fiber. The spectroradiometer had a spectral range of 360 - 1000 nm. After the LED was illuminated it was required to stabilize to within 0.02 C for 15 seconds. Measured Optical Parameters The following optical parameters were acquired for each current level: • Emission Spectrum - was measured from 360-1000 nm.

Peak, center, and dominant wavelengths can be extracted from the emission spectrum.

• Optical Power - is the total amount of light emitted by the LED and measured in Watts.

• Luminous Flux - measures the total optical power of the LED as seen by the human eye. It is expressed in Lumens and is calculated by multiplying the photopic response of the human eye by the radiometrically calibrated emission spectrum.

• Efficiency - communicates the conversion rate of electrical power (in Watts) to optical power (also in Watts) of the LED. It is expressed as a percentage. When this parameter includes the efficiency of the power driver and electronics it is referred to as wall plug efficiency.

• Efficacy - is measured in Lumens/Watt and is an indicator of how efficiently the LED converts electrical power into visible radiation.

• Color Coordinates – CIE 1931 (XYZ) and CIE 1976 (u’, v’) color coordinates as well as color-correlated temperature, and duv.

Optical Results Optical tests show a clear and significant impact of die attach material on LED emission. Figure 8 shows that LEDs assembled with Fortibond sintered silver have 30% higher luminous flux at 0.7 A (approx. 1.6 W) than LEDs assembled with SAC305. Figure 9 shows a trend among all LEDs

towards lower efficiencies as electrical power increases. This is typical among LEDs. However, LEDs assembled with sintered silver had 22% higher power efficiency than those assembled with SAC305 when operated at 0.7 A (~1.6 W). The spectra plotted in Figure 10 show significantly higher radiant emission from an LED assembled with sintered silver versus an LED assembled with SAC305. Furthermore, SAC305 samples showed a shift in peak wavelength at higher operating currents than sintered silver LEDs.

These results are significant and point to clear benefits to end-users regarding overall LED efficiency and brightness. Considered over the lifetime of typical LEDs, the use of

Figure 8. The average luminous flux of LEDs assembled with SAC305 and Fortibond sintered silver die attach materials. Luminous flux is a measure of the total light output of an LED.

Figure 9. The average efficiency (measured in Watts/Watt) of LEDs assembled with SAC305 and Fortibond sintered silver die attach materials. As the electrical power increases all LEDs experience lower efficiency. This effect can be somewhat mitigated by using higher thermally conductive die attach layers, such as sintered silver, as shown.

Figure 10. Emission spectra of two LEDs assembled with SAC305 solder and Fortibond sintered silver die attach materials with equal bond line thickness. The LED assembled with sintered silver showed higher radiant flux and a smaller peak wavelength temperature shift than the LED assembled with SAC305.


sintered silver in commercial die attach applications presents significant cost- and energy-savings to consumers. FIELD EXAMPLE – UV DIE ATTACH SINTERED SILVER APPLICATION For this field example we assembled four vertical InGaAlN on metal alloy UV LEDs onto 3535 packages using a sintered silver die attach material and a silver-filled epoxy. The dies were manufactured by SemiLEDs, model EV-D45A, and had dimensions of 1.2 x 1.2 mm with a maximum forward current of 0.7 A. The LEDs were placed via die bonder and then sintered in a box oven. The packages were then soldered to a substrate. The LEDs in this study came from two different lots. The sintered silver dies had a k-factor of -1.19 mV/C and silver-filled epoxy dies had a k-factor of -1.51 mV/C. Voids Voids were measured using an x-ray inspection system. In each case voiding was minimal, but we observed voiding on both interconnect layers (see Figure 11 and Figure 12): • L1 – The die attach layer composed of sintered silver.

Two LEDs were assembled with sintered silver paste, and two LEDs were assembled with silver-filled epoxy.

• L2 – The package attach layer composed of solder paste.

X-ray void analysis of these samples showed both L1 and L2 voids (see Figure 13). L2 voids are classic solder voids and appear with rounded edges and high contrast. They are located throughout the L2 interconnect pads. L1 voids are only on the periphery of the die attach layer. They are smaller and don’t have the nice rounded edges of classic solder voids. It is especially easy to spot the difference between these two features because L2 voids will extend across the edge of the die (because they are on the layer below the die), while L1 voids only appear under the die. Optical Results The UV LED packages were placed in an integrating sphere as described above and illuminated with 0.1, 0.35, 0.5, and 0.7 Amperes until they reached thermal equilibrium with a thermoelectric heat sink held at 25 C. Radiant power, rather than luminous flux, is communicated here because these are UV LEDs and emit outside the visible spectrum.

Figure 11. Packages (left) and UV dies (right) assembled with Fortibond (sintered silver).

Figure 12. Packages (left) and UV dies (right) assembled with silver-filled epoxy.


LEDs assembled with sintered silver show 18% higher radiant power at 0.7 A than LEDs assembled with silver-filled epoxy while also consuming 8% less power (Figure 14). This is because the LEDs are operating at higher efficiencies, as shown in Figure 15. Sintered silver samples run with 24% higher efficiency than silver-filled epoxy samples at 0.7 A.

Lastly, Figure 16 shows a smaller shift in color coordinates for sintered silver samples. Note that these LEDs appear to be from different production lots because they have different color coordinates. However, the relative shift in their coordinates still communicates relative performance.

CONCLUSIONS The choice of die attach material significantly affects the thermal performance of LEDs, and therefore the optical performance. High thermal conductivity materials, such as Fortibond sintered silver, reduce junction temperatures, increase radiant power and optical efficiency, and stabilize thermally-induced color shifts. Measuring the precise performance of these materials can be challenging and

Figure 13. Voiding on the L1 and L2 layers of a UV LED assembled with silver-filled epoxy on a soldered package. The L1 layer is silver-filled epoxy, the L2 layer is solder.

Figure 14. Radiant power of UV LEDs assembled with sintered silver and silver-filled epoxy die attach materials.

00.10.20.30.40.50.60.70.80.9

0 0.5 1 1.5 2 2.5

Radi

ant P

ower

(W)


Radiant Power of UV LEDs

Fortibond, LED 1 Silver Epoxy, LED 1


Figure 15. Optical efficiency of UV LEDs assembled with sintered silver and silver-filled epoxy die attach materials.

25%

30%

35%

40%

45%

50%

55%

60%

65%

0 0.5 1 1.5 2 2.5

Opt

ical

Effi

cien

cy (W

/W)


Optical Efficiency of UV LEDs



Figure 16. CIE Color coordinates of UV LEDs assembled with sintered silver and silver-filled epoxy die attach materials. Sintered silver samples showed a shorter color shift, which implies a higher thermal conductivity die attach material.

0.06

0.08

0.1

0.12

0.14

0.16

0.16 0.18 0.2 0.22

v'

u'

Color Coordinate Shift of UV LEDs




requires the use of dielectricless substrates. However, observing the influence of high performance interconnects on end-use applications (such as UV LEDs) is easier because the influence on final device performance is large. LEDs operating at high electrical powers especially benefit from high performance interconnects.

REFERENCES [1] N. Herrick and R. Pandher, "Thermal, Optical, and

Electrical Performance of LED Die Attach," in SMTA LED, Atlanta, Georgia, USA, 2016.

[2] T. Burkhardt, M. Hornaff, A. Acker, T. Peschel, E. Beckert, K.-H. Suphan, K. Mensel, S. Jirak, R. Eberhardt and A. Tünnermann, "Die-Attach Technologies for Ultraviolet LED Multichip Module Based on Ceramic Substrate," Journal of Microelectronics and Electronic Packaging, vol. 9, pp. 113-119, 2012.

[3] P. Panaccione, T. Wang, X. Chen, S. Luo and G.-Q. Lu, "Improved Heat Dissipation and Optical Performance of High-power LED Packaging with Sintered Nanosilver Die-attach Material," in 6th Int. Conf. and Exhibition on Device Packaging, Arizona, USA, 2010.

[4] H. (. I. Jin, S. Kanagavel and W. F. Chin, "Novel Conductive Paste Using Hybrid Silver Sintering Technology for High Reliability Power Semiconductor Packaging," Electronic Components & Technology Conference (IEEE), 2014.

[5] Electronics Industries Association, "EIA/JESD51-1 Integrated Circuits Thermal Measurement Method Electrical Test Method (Single Semiconductor Device)," 1995.

[6] Illuminating Engineering Society, "IES LM-79-08, Electrical and Photometric Measurements of Solid-State Lighting Products," 2008.

EFFECT OF THERMAL PROPERTIES OF DIE ATTACH MATERIALS ON PERFORMANCE OF HIGH POWER BLUE LEDS

Aloka Khanna, Ranjit Pandher, Ph.D. and Ravi Bhatkal, Ph.D.

Alpha, an Alent plc Company South Plainfield, NJ, USA

[email protected]

ABSTRACT InGaN-based High Power blue LEDs exhibit a maximum light conversion efficiency of 40%, which decreases further at high drive currents. Thus, more than 60% of the electrical input power is dissipated as heat in an LED chip, leading to a rise in the junction temperature of the LED. Junction temperature has a significant impact on the light conversion efficiency of the LEDs. Also, it reduces LED lifetime by excessive heating and results in subsequent failure of the LED chip. Thus, heat flow from junction to heat sink is important for maintaining the junction temperature as well as the light conversion efficiency and light output in a high power LED package. Heat flow can be facilitated by using high thermal conductivity die attach materials for packaging LED die on the MCPCB. Therefore, commercially available LEDs have been characterized for evaluating the affect of different die-attach materials on LED junction temperature and light conversion efficiency at different drive currents. Also, the variation of peak emission wavelength and light conversion efficiency with heat sink temperature has been determined for the packaged LEDs. The results and observations have been presented here along with recommendations for future work. INTRODUCTION The junction temperature in the LED increases with increasing drive current since, more than 60 % of electrical input power is dissipated as heat due to efficiency droop at high drive currents in InGaN LEDs. This rise in the junction temperature reduces the light output by increasing the probability of non-radiative recombination. Thus, the dissipated heat needs to be removed from the junction in order to maintain the light conversion efficiency and light output from the High Power LED package. The various components in the heat flow path in a High Power LED package as shown in Figure-1 are LED junction, substrate (Sapphire, SiC, Si), die attach material, MCPCB, thermal interface material and heat sink. The thermal conductivity of the die attach being lower than some of the other components in the heat flow path can play a significant role in determining the thermal resistance from junction to heat sink which further affects the heat flow rate and junction temperature in the LED package.

Figure 1. High Power LED

Thus, in order to evaluate the affect of die attach materials with different thermal conductivities on LED junction temperature, light conversion efficiency and light output, commercially available 1 W blue LED chips from SemiLED were packaged on Aluminum Metal Core PCB and characterized by junction temperature and optical measurements. LED junction temperature cannot be measured directly and therefore, forward voltage method was used for evaluating junction temperature at different drive currents, utilizing the variation in the LED forward voltage with junction temperature. Optical measurements were done on the packaged LEDs in a Labsphere Integrating Sphere for determining their light output, light conversion efficiency and peak emission wavelength. EXPERIMENTAL LED packaging For junction temperature and light output characterization, 1W blue SemiLED chips with peak emission wavelength of 455 nm were used. These were packaged on a 1 cm × 1 cm Aluminum Metal Core PCB with two different die attach materials (SAC-305 and SnBiAg) used as models. The thermal conductivities and packaging processes used for these two die attach materials are summarized in Table-1.

Table-1.

Junction temperature measurement by Forward Voltage Method Equation-1 describes the variation of the LED forward voltage with junction temperature. In order to assess the junction temperature of the LED using forward voltage, two sets of measurements need to be done- a calibration

measurement and the actual junction temperature measurement. The calibration measurement is done in a temperature-controlled oven wherein the forward voltage is measured at different ambient temperatures when the LED is driven at a very low drive current (<30 mA) to avoid self-heating so as to keep the junction temperature as close to the ambient temperature as possible. The calibration measurement gives the temperature coefficient of the diode forward voltage (dVf/dT).

In the second set of measurements, the forward voltage drop from high drive currents (0.3 A, 0.5 A, 0.7 A) to 0.01 A is recorded while maintaining the heat sink temperature at 20 °C. This forward voltage drop and the temperature coefficient of diode forward voltage derived earlier are used to calculate the junction temperature of the LED at different drive currents. Optical measurements using Labsphere Integrating Sphere

Labsphere electrical, optical and thermal characterization system (TOCS) was used for the light output measurements of LEDs packaged with different die attach materials. Two sets of measurements were done- light conversion efficiency and peak emission wavelength versus drive current and sink temperature. For these measurements, the LEDs were placed on the heat sink with indium foil as the thermal interface material between the MCPCB and heat sink. The sink temperature was varied using Arroyo Instruments TECSource temperature controller and LEDs were driven using Agilent Power Supply. For the first set of measurements with varying drive current, heat sink temperature was maintained constant at 20 C with the TECSource temperature controller and for the second set of measurements with varying heat sink temperature, the drive current was maintained constant at 30 mA to avoid self-heating of the LED die.

RESULTS AND DISCUSSION

Effect of Different Die Attach Materials on LED Junction Temperature

Figure-2 shows the junction temperature as a function of the LED drive current for the two die attach materials measured using the forward voltage method described in Sec-2.2. It is seen that the LEDs packaged with die attach materials whose thermal conductivities are 60 W/m-K and 20 W/m-K, resp. exhibit a small difference in the junction temperature (2.2 °C) at the maximum rated drive current for SemiLED (0.7 A). In order to confirm these results, the junction temperature at a drive current of 0.7 A was calculated for LEDs packaged with these two die attach materials using Equation-2.

Figure 2. Junction Temperature as a function of the LED

drive current for LEDs packaged with SAC-305 and SnBiAg die attach materials

In Equation-2, Tj represents the junction temperature,

Tboard is the board temperature, Rjunc-board is the thermal resistance from junction to board and ∆W is the heat generated from input power. At a drive current of 0.7 A, the power dissipated in the SemiLED package is nearly 2.2 W. For junction temperature calculations, the board temperature was calculated using Equation-3 and the thermal resistance value for the thermal interface material (82 W/m-K for indium foil) with a cross-sectional area of (1 cm×1 cm) and thickness of 0.1 mm.

The heat sink temperature was maintained at 20 °C for junction temperature measurement using forward voltage method and this value was used for the calculation of board temperature. The calculated board temperature at 2.2 W power dissipation is 20.02 °C. The value of thermal conductivities, cross-sectional area and thickness for heat flow for the various components in the heat flow path are presented in Table-2. Thermal resistance and calculated junction temperature values are presented in Table-3. It is seen from Table-3 that the calculated value of difference in the junction temperature (1.9 °C) of LEDs packaged with the two die attach materials is in good agreement with the value determined experimentally (2.2 °C).

The assembly process for the LED package may yield less than 100 % pad coverage and voiding in the die attach layer. For the junction temperature calculation using package thermal resistance, it has been assumed that the pad coverage is 100 % and no voiding occurs in the die attach layer and thus, the thermal resistance of the die attach layer for these calculations is lower than the thermal resistance in the actual package. This explains lower junction temperatures from package thermal resistance calculations as compared to the values measured by the forward voltage method. Effect of different die Attach materials on LED light output and quality

Junction temperature has a significant impact on the light conversion efficiency of the LEDs. High thermal conductivity die attach materials can improve the light conversion efficiency by reducing the junction temperature at high drive currents. Thus, the light conversion efficiency and light output of LEDs packaged with two die attach materials (SAC-305 and SnBiAg) was recorded at different drive currents. Figure-3 (a-b) show the light conversion efficiency and light output versus drive current data measured at a constant sink temperature of 20 C for the two LED packages with different die attach materials. It is seen from Figure-3 (a) that the LED packaged with SAC-305 shows lower drop in light conversion efficiency at high drive currents as compared to the LED packaged with SnBiAg due to better thermal management in the former resulting from higher thermal conductivity of SAC-305. At 1 A drive current, the LED packaged with SAC-305 shows 2.4% higher efficiency than the LED packaged with SnBiAg. The high light conversion efficiency is translated into higher light output (Figure-3 (b)) which is almost greater than1.1 times for the LED packaged with SAC-305 as compared to the LED packaged with SnBiAg at 1 A drive current.

Figure 3. (a) Light Conversion Efficiency, (b) Light Output as a function of the LED drive current for LEDs packaged

with SAC-305 and SnBiAg die attach materials Figure-4 (a-b) show the variation of the peak emission wavelength with LED drive currents for LEDs packages with SAC-305 and SnBiAg die attach materials, respectively. The peak emission wavelength for both LEDs follows a similar trend i.e. the peak emission wavelength first decreases with increasing drive current and then increases at high drive currents. For these measurements, the sink temperature was maintained at 20 °C. This trend is explained by two competing effects with increasing drive current i.e. rise in junction temperature and QCSE (Quantum Confined Stark Effect). While QCSE causes the energy levels in the quantum wells to move farther apart due to increasing electric field, the junction temperature rise with increasing drive current causes the effective band-gap to decrease. This leads to decrease in the peak emission wavelength as QCSE dominates at lower drive currents and increase in peak emission wavelength as effect of junction temperature dominates at higher drive currents. Since, a noticeable variation in peak emission wavelength due to junction temperature requires at least a 20 °C difference in the junction temperature (Figure-6), no difference in peak emission wavelengths for the two LEDs was recorded in this case as the junction temperature difference for these is only 2-3 °C.

Figure 4. Peak Emission Wavelength as a function of the

LED drive current for LED packaged with (a) SAC-305 and (b) SnBiAg die attach material.

Effect of heat sink temperature on light output and quality

For a 1 W LED on FR4 PCB with a TIM of thermal conductivity 3 W/m-K, there is almost a 50 °C difference between the sink and junction temperature. For such an LED on Si substrate with a die attach material of thermal conductivity 57 W/m-K under 1 W operation, the junction temperature is 104 °C while the sink temperature is 53 °C. Thus, in order to emulate the real operating conditions of a 1 W LED, the light conversion efficiency of SemiLEDs LEDs with different die attach materials was characterized at different sink temperatures. The sink temperature was regulated using the Arroyo Instruments TECSource Temperature Controller. Figure-5 (a-b) show the variation in the light conversion efficiency as a function of the sink temperature at drive currents of 1 A and 1.1 A, resp. for LEDs packaged with SAC-305 and SnBiAg die attach materials.

The junction temperature of the LEDs increases with the sink temperature and thus, light conversion efficiency decreases with increasing sink temperature. Heat flow from the junction is affected by the thermal conductivity of the die attach material and thus, the drop in LED efficiency with sink temperature is an indication of effectiveness of the die attach material in heat flow from the LED junction to the heat sink. It can be seen from Figure-5 (a-b) that the efficiency drop from 20 °C to 70 °C sink temperature is higher for LEDs packaged with SnBiAg as compared to SAC-305 due to higher thermal conductivity of SAC-305 die attach material. As seen from Figure-5 (a-b), the light conversion efficiency at a sink temperature of 70 ºC is 0.2 % and 0.8 % higher for LEDs packaged SAC-305 as compared to those with SnBiAg at 1 A and 1.1 A drive currents, respectively. Also, the typical sink temperature for a 60 W LED lamp in the open base down configuration is 75 °C. As seen from Figure-6, the LED peak emission wavelength changes at the rate of 1 nm per 20 °C. Therefore, a typical LED lamp in this configuration would show a 2-3 nm variation in peak wavelength under operation.

Figure 5 (a-b). Light Conversion Efficiency as a function of

the Sink Temperature for LEDs packaged with SAC-305 and SnBiAg die attach materials at different drive currents

Figure 6. Peak Emission Wavelength as a function of Sink Temperature for blue 1W SemiLEDs at 30mA drive current

CONCLUSIONS

Commercially available blue LEDs have been characterized for evaluating the affect of different die-attach materials on LED junction temperature, light output and quality at different drive currents. It was found that by replacing a

die attach materials with thermal conductivity of 20 with a material having thermal conductivity of 60 W/m-K, the light conversion efficiency could be increased by 2.4% at 1 A drive current. Also, this translates into a light output improvement of 10-11%. Further, the affect of sink temperature on light output and quality was determined for the LEDs packaged with these two die attach materials. It was found that high sink temperatures led to loss of LED light conversion efficiency which further increased the junction temperature of the LED. Thus, the LEDs packaged with SAC-305 exhibited 0.2 % and 0.8 % higher light conversion efficiency as compared to LEDs packaged with SnBiAg as SAC-305 facilitated efficient heat flow from the LED junction to the heat sink. Also, it was determined that the peak emission wavelength of the 1 W blue LED changed at a rate of 1 nm per 20 °C change in sink temperature which could cause significant shift in the chromaticity of LED lamps where the typical sink temperatures are in the range of 75-100 °C.

LED THERMAL MANAGEMENT SYSTEMS – HIGH THERMAL AND HIGH RELIAIBLITY MATERIALS

Ravi Bhatkal, Ph.D., Gyan Dutt Alpha, an Alent plc Company

South Plainfield, NJ, USA [email protected]

INTRODUCTION LED technology is seeing widespread adoption in range of end markets including lighting, automotive and display applications. LEDs offer several advantages such as energy efficiency, long life, instant turn on and off, high luminance, high brightness, color control (e.g. pure red, orange, and white light), shock and vibration resistance, and styling and design freedom. LED lighting systems such as exterior lighting, can be described in terms of a hierarchy shown in Figure 1 below.

Figure 1. Hierarchy of an LED Lighting System

For high power LED applications such as projection, street lighting and automotive headlamps, materials used in the packaging and assembly of LEDs need to be able to handle high thermal loads and high thermal cycle and vibration reliability requirements. In this paper, we discuss the mitigation of thermal and reliability issues in high power LED lighting systems with two of Alpha®’s advanced materials platforms. KEY ISSUES IN LED LIGHTING Key issues in high power LED lighting include:

Heat dissipation at all levels of the lighting system o Heat buildup can lead to device failure o Voiding under thermal pads leads to heat

buildup, loss of efficiency and potential failures

Directionality of light output

o Applications such as spotlights or headlights need good control of LED die/package tilt and optical axis

Reliability and Longevity o Long term thermal cycling requirements

and vibration resistance during operation are critical for reliable operation of the LEDs for the design life.

Efficiency and brightness improvement o Efficiency is critical for reduction of

energy consumption, while brightness improvement (increased light output) is needed to reduce cost per lumen.

Rework o It is difficult to rework LEDs assembled,

so first pass yield is critical Materials and components were chosen based on commercially available LED packages, solder pastes and flexible substrates. THE ROLE OF HIGH THERMAL AND HIGH RELIABITY MATERIALS IN LED LIGHTING

High thermal and high reliability die attach and assembly materials enable rapid heat extraction, thus enabling performance improvement, reliably, over the expected lifetime.

Key requirements for advanced die attach and assembly materials used in LED die attach and package-on-board assembly are:

Die Attach o Very high thermal conductivity o Thin, uniform bond line for die tilt control

and thermal performance o No bleed-out or die top contamination o High thermal cycle reliability with high

CTE mismatch o High creep resistance

Package-on-Board Assembly o Low/acceptable void level assembly o Package tilt control o High creep-fatigue resistant solder alloys

leading to better thermal cycling performance

o High vibration resistance o Excellent printability and first time right

assembly

TWO KEY ALPHA® TECHNOLOGY PLATFORMS FOR HIGH THERMAL, HIGH RELIABIITY

Alpha®’s novel high thermal, high reliability materials for LED die and package attach can help improve the design window and performance.

High creep fatigue resistant solders o Maxrel™ alloy based preforms and paste

for die/package attach Silver sintering die attach materials

o Argomax® Ag film for die attach o Fortibond™ pressureless sintering

Maxrel™ Creep Resistant Alloy Maxrel™ alloy is a creep resistant solder material that increases reliability of the solder joints subjected to thermal cycling in high CTE mismatch material stacks. Figure 2 shows Maxrel alloy performance vs SAC305 alloy in thermal cycling of ceramic submount LEDs assembled on Metal Core PCBs. High creep resistance of Maxrel™ alloy provides better thermal cycling performance.

Figure 2. Thermal Cycling Performance of Maxrel™ Alloy vs SAC305 Alloy Maxrel™ alloy has unique reflow properties that minimize die / package tilt and die float. This leads to more uniform bond lines and control of die tilt as shown in Figure 3. Further, the higher creep resistance of Maxrel™ alloy provides increased reliability while reducing bond line, which in turn means that Maxrel™ alloy can provide lower thermal resistance in the joint. Further improvements in reliability can be obtained by tailoring the ratio of modulus of the solder to the modulus of the dielectric.

Figure 3. Bond Line Uniformity of Maxrel™ Alloy

Joint vs SnAg Alloy Joint

Argomax® Ag Sintering Technology Argomax® Ag sintering materials can be processed at 190C to 300C under pressure, to form a pure Ag interface. After bonding, Argomax® joint has a melting point of 962 C, same as bulk silver. The material and process yields joints with thermal conductivities in the ~250W/mK range, with thin, uniform bond lines. The resulting bond is a pure diffusion bond with no intermetallics. Argomax® Ag sintering technology, offered in a film form factor, can provide automotive Led assemblies with:

• No die tilt, highly controlled and uniform bond line, which provides excellent control of directionality and optical axis.

• No bleed-out of the die attach material, ensuring die-footprint-conformal die attach yielding smaller package and module sizes.

• Placement of an array of dies closer together without movement or "die float" which yields higher lumen density in smaller area.

• Ultra-high thermal conductivity, enabling thermal resistance reduction, and therefore lower junction temperatures, or higher drive currents. This can yield brightness improvement and control of wavelength shift and ability to handle very high power densities.

• Very high die shear strength and thermal cycling/thermal shock reliability as shown in Figure 4.

Figure 4. Argomax® Provides High Thermal Cycle and

Thermal Shock Reliability The process is high volume manufacturing capable, with sintering process UPH capability in excess of 20,000 die bonded per hour. This is shown in Figure 5. Processing Options

Die-level film lamination (DTF Process) Wafer back-side lamination Large area bonding

Figure 5. Argomax® Processing Options and HVM

Capability Fortibond™ Pressureless Ag Sintering Technology Fortibond™ pressureless Ag sintering technology, currently in paste form, is new Ag sintering technology platforms developed by Alpha that can be used for die attach using existing equipment sets for printing/dispensing, placement and sintering.

• Pressure-less Silver Sintering Paste compatible with existing dispense / printing, die bonding and curing equipment

• Sintered silver joint enables high temperature stability during secondary reflow

• High bulk thermal conductivity (135+ W/mK) enables lower junction temperature / higher light output

• Available in print & dispense versions with pin transfer versions in development.

• Regular refrigerator storage and shipping without dry ice for easy economical handling

Fortibond pastes demonstrate high performance. For example, the Fortibond AL12P printable paste shows shear strength in the 25 MPa range, passes typical LED package thermal cycling, thermal shock and thermal aging requirements, as well as withstanding multiple reflows in MSL Level 1 testing for the die attach material.

• Die-Shear Strength: >25MPa • Thermal Cycling: Passed 1000 cycles with -40 to

125C • Passed 1000 hrs aging at 175C with no change in

die-shear strength • Thermal Shock : Passed 1000 cycles from -55 to

+125C • Passed Moisture Sensitivity Level (MSL) Level 1

Fortibond™ is a Pressure-less silver sintering technology platform designed to address applications that require assembly at zero / low pressure by processes compatible with existing equipment. (on both semiconductor packaging as well as SMT assembly lines) shown in Figure 6.

Figure 6. Fortibond™ Processing Options and HVM

Capability Summary and Conclusions High reliability, high thermal technologies such as Maxrel™ alloy, Argomax® Ag sintering film and Fortibond™ pressureless sintering technology can be used to provide high reliability, high thermal joints for LED assembly in high power lighting applications. Acknowledgements Bawa Singh Oscar Khaselev Ranjit Pandher Shamik Ghoshal Sathish Kumar Siuli Sarkar Mike Marczi Julien Joguet Gustavo Greca Monnir Boureghda Paul Koep Anna Lifton

High Thermal, High Operating Temperature Interconnects For Ultra High Power LEDs

Ravi M. Bhatkal, Ph.D. and Ranjit Pandher, Ph.D.

Alpha Assembly Solutions South Plainfield, NJ, USA

[email protected]

ABSTRACT Use of super/ultra-high power LEDs is increasing. For high performance applications such as street lighting and ultra-high power density illumination, use of ultra-high power can enable significant systems cost reduction through use of fewer LEDs, smaller PCBs, smaller heat sinks and lighter load bearing structures. In order to be able to drive the LEDs harder and to increase light output in a smaller footprint, one needs efficient thermal performance at the LED die-to-package connection. The ultra-high power density, combined with high thermal metal substrates, (which have high CTE mismatch with ceramic sub-mount LEDs) necessitates use of ultra-high reliability interconnects for elevated temperature operation at the package-to-board connection. This paper presents two technology platforms: 1. Sintered silver, which enables significant increase in light output at package level, and 2. High temperature creep resistant solder alloys that provide high thermal cycling reliability under high temperature and high CTE mismatch conditions. Key words: LED, Ultra High Power, High Reliability, LED Lifetime, Sintered Silver, Creep Resistant Solders INTRODUCTION The LED lighting revolution is on. The global acceptance of LED based light sources has entered many different markets including, high power lighting segments which are largely driven by their end-application. Several applications are adopting high and ultra-high power LEDs [1,2]. Examples include roadway/street, industrial, architectural lighting, projection and entertainment lighting. All these applications demand long term reliability of the light source. New high and ultra-high power LED package designs provide high lumen density that can enable significant system cost reductions through fewer LEDs, smaller PCBs, and smaller heat sink size requirements. However, the high lumen density and smaller heat sink also means long term operation of LED at elevated temperatures. That means all the components and materials have to survive in those operating conditions. The role of interconnects in LED assembly is fundamental to:

• Convey power and information efficiently and reliably over the rated life.

• Get the heat out faster and more reliably over the rated life.

• Enable more light output, consistently, for longer periods of time from the same package and system footprint.

KEY ISSUES IN ULTRA-HIGH POWER LED ASSEMBLY AND POTENTIAL SOLUTIONS Key issues in ultra-high power, high operating temperature applications include:

• Lifetime improvement through higher reliability and lumen maintenance over long periods of use.

• High rate of thermal dissipation through the stack, enabling lower junction temperatures while pumping increased current through the system.

Ultra-high power LEDs (> 5W) have significant current flowing through them [2], which generates large amounts of heat. In a typical LED package architecture, LED dies are bonded on a ceramic substrate (also called submount) which has circuit designed for electrical and thermal interconnects. This LED mounted on submount with electrical connects and possibly with a lens at the top is usually called a LED package. To improve heat dissipation, these ultra-high power LED packages are assembled on Metal Core PCBs (either Al or Cu based-metal), MCPCB. There is a significant CTE mismatch between the ceramic submount in the LED package and the MCPCB. For example, the ΔCTE between AlN submount and the Al MCPCB is 20 ppm/C, and the ΔCTE between the AlN sub-mount and the Cu MCPCB is 12 ppm/C, as shown in Figure 1.

Figure 1. Drawing of an Assembled High-Power Ceramic LED on a Metal-Core PCB Showing CTE Differentials. During thermal cycling experienced by the ultra-high power LED assembly in applications such as projection, or outdoor lighting or automotive, the high ΔCTE causes significant strain energy build-up in the solder joint between the LED submount and the MCPCB, during the thermal cycling experienced in use. This is shown schematically in Figure 2 demonstrated by Peter Hall at AT&T Bell Laboratories [3,4]. This strain energy buildup causes micro-cracking, and eventually, failure of the joint.

Figure 2. Solder Joint Hysteresis Loop During Thermal Cycling Between -25°C and 125°C. One strategy to combat this issue and improve the reliability of ultra-high power LED assemblies is to use high temperature creep resistant solder alloys. High temperature creep resistant alloys help improve microstructural stability under high operating temperature and thermal cycling conditions [5]. EXPERIMENTAL DEATAILS To understand the LED lifetime dependence on the second level interconnect (LED package to circuit board) we used commercially available Luxeon Rebel white LED packages from Lumileds. These LED packages were assembled on Aluminum core MCPCB’s using two types of solder pastes. One of the pastes was made with SAC305 powder while the other one was made with another SAC alloy designed for high reliability (called Maxrel alloy in this paper). Following two reflow profiles were used:

1. 260LV: 150-200C soak for 120min, 260C peak and

90-96s TAL. 2. RecoLV: 150-200C for soak 110s, 240c peak and

90-70s TAL. All the reflows were in N2 atmosphere. A total of 72 LEDs were assembled for each paste and each reflow. Of the 72

LEDs, 36 were used for LED light up test and other 36 were used for die shear test. For die shear test, 12 packages were sheared right after soldering, another 12 each after 500 temperature cycles and 1000 cycles respectively. All the assembled LED were x-rayed to measure voids in the reflowed joints. Both the pastes showed similar voids (8-14%) under both the reflow conditions. All the LED’s were forward biased using a low voltage DC power supply running in constant voltage mode and current was recorded for each LED. These LEDs were then subjected to temperature cycling in an air to air chamber with -40 to +125C and 30min dwell at both the extremes. LEDs were taken out at regular intervals, biased again under identical conditions and forward current recorded each time. An LED was considered a failure if the electrical power through the LED dropped below 70% of the original. The test was run up to 1000 cycles. To understand the effect of thermal conductivity of the interconnect materials, commercially available 1mm X 1mm UV LED dies from SemiLeds were attached to ceramic substrates using two types of die-attach pastes. One of the die attach pastes was a sintered silver paste with bulk thermal conductivity ~130W/mK while other material was a conductive epoxy paste with bulk thermal conductivity ~20 W/mK. Both of these pastes were sintered/cured at 200C. After die bonding the bonded LEDs were singulated and tested individually. Each LED was mounted on a thermoelectrically cooled heat sink set at 25C. LEDs were powered by a DC power supply capable of switching current within <30 µS and current through LED was measured using a fast sampling (10 Ks/S micro-amp capable multi-meter. LEDs were operated up to maximum specified power. Junction temperature at each operating current was measured following the technique described in EIA/JESD 51-1 standard [6]. Light emitted by LEDs was collected using an integrating sphere. Output of integrating sphere was monitored using a spectrometer. Integrating sphere and spectrometer setup was calibrated using a standard light source. RESULTS AND DISCUSSION Figure 3 shows the failure rate as a function of the number of thermal cycles of ceramic submount high power LEDs assembled on Al MCPCB with SAC305 alloy and a creep resistant test alloy called Maxrel alloy. MCPCB dielectrics and solders have much different CTE as compared to the ceramic submount on which LED die is attached. Because of this CTE mismatch, the interconnect goes through cyclic stress during temperature cycling test. At some stage one or the other interface starts cracking resulting in an increase in electrical resistance of the interconnect. This results in decrease in LED power. In this test a drop in 30% of the initial power is considered a failure. The test alloy Maxrel is designed to resist the creep. It is clear that solder joints

with creep resistant Maxrel alloy show much lower failure rates than those with SAC305 alloy. There was absolutely no difference in the light-up test of the LEDs assembled under two reflow profile. Figure shows combined results of both the reflow profiles.

Figure 3. Failure rate vs. number of thermal cycles of ceramic submount high power LEDs on MCPCB. Figure 4 shows the shear results for a high power ceramic LED on a metal core PCB subjected to 0, 500 and 1000 cycles at -40°C to 125°C. The results indicate that the Maxrel alloy has higher shear strength and the lower degradation / drop upon thermal cycling as compared to SAC305 alloy. After 1000 cycles, Maxrel alloy shows a ~25% drop in shear strength from its initial value. In contrast, we see that the SAC305 alloy showed a drop of ~60-61% from its initial value. There is no significant difference effect of the reflow profile on the shear strength.

Figure 4. Thermal Cycles vs Shear Strength for Maxrel and SAC305 alloys. Thus, for a given LED package structure and board material used, it is beneficial to use solder joints with improved mechanical and thermal fatigue/creep and vibration

resistance. A new class of creep-resistant and vibration resistant alloys has been developed, that can provide this capability, via a micro-structural control approach[3]. These advanced alloys have been developed with special additives for improved thermal stability for high temperature operation and higher thermal fatigue and vibration resistance. The high heat generated by ultra-high power LEDs also necessitates very rapid heat extraction, to allow the LED to operate at or below the maximum junction temperature specified for the LEDs. For most of LEDs, maximum operating junction temperature is below 125C in continuous operation mode. Further, extremely rapid heat extraction can allow driving the LED harder, while maintaining the junction temperature at an acceptable operation range, especially for the vertical LEDs. This in turn allows for packing higher lumen output in a more compact space. Sintered silver technology allows for such rapid heat extraction, while providing very high thermal cycle reliability. Silver sintering materials can be processed at 200C to 300C under pressure or without pressure, to form a sintered Ag interface [7,8] If the joint does not contain any resin, after bonding, the joint has a melting point of 962C, which is the same as that of bulk silver. The materials and processes yield joints with thermal conductivities in the 130-250W/mK range, with thin, uniform bond lines.The resulting bond is a diffusion bond with no intermetallics. Sintered silver provides ultra-high thermal conductivity, enabling thermal resistance reduction, and therefore lower junction temperatures, or higher drive currents. This can yield brightness improvement and control of wavelength shift and ability to handle very high power densities. An example of this property is shown in Figures 5a and 5b using Fortibond Prelssureless Ag.

Figure 5a. UV LED: Junction Temperature vs Power for Fortibond Sintered Ag vs Conductive Adhesive

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Figure 5b. UV LED: Radiant Power vs Electrical Input Power for Fortibond Sintered Ag vs Conductive Adhesive Figure 5a plots Junction Temperature vs Electrical Input Power for high power LEDs and Figure 5b plots Radiant Power vs Electrical Input Power, for high power UV LEDs, for Fortibond sintered Ag die attach material compared to conductive adhesive die attach material. It is clear that sintered Ag consistently results in lower junction temperature at a given input power, and provides higher radiant power at a given input power. Further, Ag sintering technology in a film form factor [7,8], can provide LED assemblies with several additional advantages such as: • No die tilt, highly controlled and uniform bond line,

which provides excellent control of directionality and optical axis.

• No bleed-out of the die attach material, ensuring die-footprint-conformal die attach yielding smaller package and module sizes.

• Placement of an array of die closer together without movement or "die float" which yields higher lumen density in smaller area.

• Very high die shear strength and thermal cycling/thermal shock reliability.

CONCLUSIONS 1. For high and ultra-high power LEDs, for a given LED

package structure and board material used, it is beneficial to use solder joints with improved mechanical and thermal fatigue/creep and vibration resistance. A new class of creep-resistant and vibration resistant alloys has been developed, that can provide this capability, via a micro-structural control approach. These advanced alloys have been developed with special additives for improved thermal stability for high temperature operation and higher thermal fatigue and vibration resistance.

2. Sintered silver technology has several benefits for high and ultra-high power LEDs, including enabling higher

light output while maintaining junction temperature, enabling excellent control of tilt, directionality and optical axis, and providing very high thermal cycling reliability.

3. These emerging technologies are enabling us to push the envelope in implemeting ultra-high power LEDs in several applications.

ACKNOWLEDGEMENTS The authors would like to thank Nicholas Herrick, Westin Bent, Ramazan Soydan, Amit Patel and Gyan Dutt, for input and data presented in this paper. REFERENCES

[1] M. H. Crawford, J. J. Wierer, A. J. Fischer, G. T. Wang, D. D. Koleske, G. S. Subramania, M. E. Coltrin, R. F. Karlicek, Jr., and J. Y. Tsao, “Solid-State Lighting: Toward Smart and Ultraefficient Materials, Devices, Lamps, and Systems 1”, in D.L. Andrews, Ed., “Photonics Volume 3: Photonics Technology and Instrumentation” (Wiley, 2013).

[2] Stephanie Pruitt, “Global LED Market Overview”, Strategies in Light, Santa Clara, March 11-13, 2016.

[3] Hall, P. M., "Strain measurements during thermal chamber cycling on leadless ceramic chip carriers soldered to printed boards", Proceedings, 34th Electronic Components Conference, New Orleans, LA, May 14-16, 1984, pp. 107-116.

[4] Hall, P.M., “Forces, moments, and displacements during thermal chamber cycling of leadless ceramic chip carriers soldered to printed boards”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, 1984, Vol. 7, No. 4, Dec. 1984, pp. 314-327.

[5] Pritha Choudhury, Morgana Ribas, Anil Kumar, Sutapa Mukherjee, Siuli Sarkar, Ranjit Pandher, Rahul Raut, Bawa Singh, and Ravi Bhatkal, “NEW Lead-Free Alloy For High Reliabilty, High Operating Temperature Applications” International Conference on Soldering and Reliability (ICSR), Toronto, Canada May 13-15, 2014.

[6] EIA/JESD 51-1 Integrated Circuits Thermal Measurement Method – Electrical Test Method.

[7] Dmitry Titushkin, Alexey Surma, Michiel de Monchy and Anna Lifton “Aspects of reliability improvement for large area power semiconductor devices through sintering” PCIM Europe Conference, 10–12 May 2016, Nürnberg, Germany.

[8] Francois Le Henaff, Gustavo Greca, Paul Salerno, Olivier Mathieu, Martin Reger, Oscar Khaselev, Monnir Boureghda, Jeffrey, Durham, Anna Lifton, Jean Claude Harel, Satyavrat Laud, Weikun He, Zoltan Sarkany, Joe Proulx, John Parry, “Reliability of Double Side Argomax® Silver Sintered Devices with various Substrate Metallization”, PCIM Europe Conference, 10–12 May 2016, Nürnberg, Germany.

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LED DIE ATTACH – TRENDS & CONSIDERATIONS

Gyan Dutt & Ravi Bhatkal

Alpha Assembly Solutions

Somerset, New Jersey, USA

[email protected]

ABSTRACT

Die attach material plays a key role in performance and reliability of mid, high and super-high power LEDs. The selection of the suitable die-attach material for a particular chip structure and application depends on several considerations. These include packaging process (throughput and yield), performance (thermal dissipation and light output), reliability (lumen maintenance) and cost. Eutectic gold-tin, silver-filled epoxies, solder, silicones and sintered materials have all been used for LED die-attach. Often, use of a particular technology platform results in trade-off between different attributes.

This paper reviews process, performance and reliability attributes of the die attach technologies for LED assembly. Then it addresses the fit between these die-attach materials, different chip structures (like lateral, vertical and flip-chip) and their operating power levels. Finally it describes the positioning of different technologies for applications in general lighting segment. This review clearly shows that given the diversity in chip structures, package designs and applications, all material platforms have a place in LED die attach. A diverse portfolio that provides die attach options to LED device makers and packagers is required to meet the process and performance demands in this rapidly changing market.

Keywords: Die Packaging, Die Attach, Silver Sintering, Conductive Adhesive, Solder

LED PERFORMANCE, RELIABILITY & DIE-ATTACH

Mid to super-high power LEDs are being operated at increasing current and power levels (for lighting and mobile flash applications among others). This trend has, again, brought the need for robust thermal dissipation to the forefront. If the heat is not managed properly, the LED performance can degrade significantly – resulting in loss of radiant flux, increase in forward voltage, wavelength shift and consequentially reduced lifetime.

Die-attach is the first layer that comes into contact with the LED die and its thermal performance and stability has a direct impact on LED light output, light extraction and lumen maintenance over time. The die-attach material and (more importantly) the process together have a significant effect on the cost of ownership of the light engine.

LED CHIP STRUCTURES, POWER LEVELS & PERFORMANCE INDICATORS

There are three main LED chip structures (Figure 1). The Lateral structure consists of laterally spaced electrodes (with one wirebond for each electrode) and is used in low power applications. The Vertical structure, used for most of the high and super-high power applications, consists of a conductive substrate at the bottom which forms the bottom electrode with the current flowing vertically. The flip-chip structure has both electrodes on one side and is put face down on the substrate. It provides the highest lumen density at cost lower than vertical structure. These three structures can also be mounted directly on a board,

next to each other, to form modules called Chip-on-board.

Figure 1: Relative power levels of common LED chip structures

DIE-ATTACH TECHNOLOGY PLATFORMS – GOLD-TIN EUTECTIC, SOLDER, CONDUCTIVE ADHESIVE, SINTERED MATERIALS

Eutectic gold-tin or AuSn (80/20 Au/Sn by wt) has been the “gold standard” die-attach material for high reliability applications for several decades. For LED die attach it is used either as a pre-coated layer on LED backside, or a preform or in form of solder paste. All these forms involve different processes and performance. Although the cost of ownership of AuSn die attach is much higher than other materials, it is still the material of choice for high power applications due to its proven thermal (57W/mK) and reliability (high creep & fatigue resistance with secondary reflow compatibility).

Conductive Adhesives (mostly silver filled epoxies) constitute the largest class of thermal die-attach materials (by unit number), not just for LEDs, but for all semiconductor packages. They are compatible with the existing back-end packaging equipment and provide an attractive cost / performance balance (typically up to 50W/mK thermal with secondary reflow compatibility). Since they stick to bare silicon, they are the preferred material of choice for dies without back-side metallization (like GaN on silicon).

Sintered silver materials consist of micro/ nano scale silver particles which undergo atomic diffusion to fuse together at 180-300°C to form nano-porous yet pure silver joint (961°C m.p.). They can be applied in either paste or film format and sintering can happen either in a

press (requires new equipment) or a regular oven. These materials, with cost in-between conductive adhesive and eutectic-AuSn, have been shown to provide superior mechanical reliability and higher thermal performance (than AuSn). For LEDs, sintered materials have been shown to improve the lumens output by up to 30% for super high power red & green LEDs.

Solder (mostly SAC based), provides exceptional value with low cost, fast assembly process with reasonable thermal performance (50-60W/mK). Lately there has been a trend to make flip-chip structure compatible with solder on SMT lines. However, since SAC solder melts in 217-221C range, its use is limited to applications where either high temperature stability is not required in operating conditions or during further processing (like secondary reflow). SnSb based solder with melting point range 245-251C can survive second reflow below 240C.

LED DIE-ATTACH MATERIALS COMPARISON

There are three key considerations for selecting material for die attach in a LED application.

1) Thermal Resistance - Among the materials discussed above, sintered silver has the highest bulk thermal conductivity (>100W/mK) and has been shown to have the lowest thermal resistance in head-to-head comparison with AuSn and silver epoxies. Eutectic gold-tin thermal conductivity has been measured around 57W/mk, which at thin bond lines (~5um) results in lower overall thermal resistance than silver epoxies (thermal conductivity <50W/mK at ~25um bond lines).

2) Second Reflow Compatibility - LED packages assembled on a submount undergo an additional solder reflow step to attach to the board. AuSn, conductive adhesive as well as sintered silver materials can easily withstand the second reflow. Obviously SAC based solders cannot be used reliably in these packages. However, for applications in which the COB module is screwed to the heat sink, second reflow is not needed and solder can be used.

3) Cost of Ownership - The die-attach step, due to the cost of the die-bonders, is usually the most capital-intensive step in LED packaging. So it

LATERAL

VERTICAL

FLIP-CHIP

POWER

CHIP-on-BOARD

is important that die-attach material and process is compatible with the existing high throughput dispense/pin transfer bonders. Solder, silver epoxy and pressure-less silver sintering die attach do not need special equipment and related new capital expenditure. This makes these materials particularly attractive over AuSn and pressure-assisted sintering materials.

These three attributes of the die-attach platforms discussed here are compared in Figure 2.

Figure 2. Die-Attach material platforms comparison

CHIP AND PACKAGE STRUCTURES FIT WITH COMMON DIE-ATTACH MATERIALS

The starting point for die attach selection is usually the end application and design. End application determines the operating environment, while design determines the number and power levels of the dies. For example, an outdoor lamp will have higher power dies designed to operate in a harsher environment, compared to low-mid power dies in a bulb designed for use in relatively benign indoor conditions. Within the bulb/luminaire application, different designers, for example, may choose between smaller numbers of high-power dies in packages or larger number of low power dies directly on board (COB).

Once these design and end-use decisions have been made, the three attributes described in the previous section are sufficient to make the die attach selection. The power level of the die determines the heat dissipation requirements - higher power dies require higher thermal conductivity die attach to keep the thermal resistance low (while lower thermal die attach is okay for low power dies). So for high-power and super high power vertical LEDs sintered materials (both pressure-assisted and pressure-less) and thin eutectic gold-tin are most suitable to lower the thermal resistance and keep the junction temperature manageable for optimal LED performance. The mid-power dies (either vertical or flip-chip in package) can use solder and high thermal epoxy. Finally for the low-power lateral LEDs, lower end epoxies (or silicone) may be good enough thermally. The chip structures and die attach material fit is shown in Figure 3.

For assemblies that do not go through second reflow (like COB), solder is the preferred die-attach material. For in-package attach, silver epoxy, AuSn or sintered materials are essentially the only options. The final major consideration is the cost of ownership (process equipment and throughput). While eutectic AuSn and pressure-assisted sintered materials provide exceptional thermal performance and mechanical reliability, they are not compatible with mainstream die bonding equipment.

Conductive epoxies and pressure-less sintered silver materials can be adopted easily on the existing lines. Solder, on the other hand, is unique in its compatibility with semiconductor packaging as well as SMT lines.

Figure 3. Chip structures fit with different die attach platforms

Secondary Reflow Possible

Yes No Yes Yes

Thermal (W/mK)

~57 ~60 2-50 >100

Cost of Ownership

Very High Low Medium Med-High

LED Die-Attach

Au /AuSn

SAC Solder

Silver Epoxy

Sintered Silver

The relative positioning of LED die-attach materials for different applications on different substrates is shown in Figure 4. Pressure-sintered silver with the highest thermal and reliability is the highest performance option for super-high power applications like projection and entertainment lighting. Pressure-less sintering silver, which is compatible with existing equipment yet provides higher thermal and reliability than silver epoxy, is suitable for most high power applications – like vertical UV, flip-chip on ceramic and lead frames (for general lighting and mobile flash) and laser diodes. Conductive epoxy can meet the requirements for most of the mid power and some high power vertical dies in general lighting applications (like retrofit bulbs), especially with dies without metallization. Finally solder is the material of choice for any low-mid power application that requires die attach directly on the board (no secondary reflow). Most of these materials (except pressure-assisted sintered silver) are compatible with existing equipment on packaging and assembly lines. Each of the technology platforms on this chart are in production commercially.

Figure 4. LED die attach materials and applications

CONCLUSION

This review clearly shows that the diversity of LED structures, power levels, applications and process equipment considerations require different die attach solutions. Every die attach material technology is being used in mass production for packaging LEDs and assembling modules – from silicones and solder to AuSn and sintered silver materials. It is also very important to note that apart from this diversity, LED market and applications are much more cost-of-ownership sensitive

and are growing at much faster rate than traditional semiconductor and electronics markets. This has resulted in shorter qualification cycles with renewed emphasis on lower packaging cost-of-ownership with each design cycle. Having a broad die attach materials portfolio provides the most appropriate options to the customer, depending on the specific application and production infrastructure available. Most of the LED device makers and packaging houses do prototype builds with several material technologies on different product platforms and end up making the final decision that is unique to their application and business model.

RELIABILITY IMPROVEMENT

LOW VOIDING RELIABLE SOLDER INTERCONNECTS FOR LED PACKAGES ON METAL CORE PCBS

Ellen Tormey, Ph.D., Rahul Raut, Westin Bent, Ranjit Pandher, Ph.D., Bawa Singh, Ph.D. and

Ravi Bhatkal, Ph.D. Alpha, an Alent plc Company

South Plainfield, NJ, USA 07080 [email protected]

Justin Kolbe

The Bergquist Company 18930 W 78th Street, Chanhassen, MN 55137, USA

ABSTRACT SSL Assemblies need to meet high reliability requirements such as Energy Star Category A which dictates a B50/L70 lifetime of 35,000 hours for commercial and outdoor residential lighting. Solder joints with low void content are critical for long term performance and reliability. Two types of MCPCB substrates, 4 different solder pastes and one type of LED ceramic package were evaluated in this study to develop a low voiding assembly process. Results of the study and recommendations for achieving low voiding are presented. Key words: LED package, MCPCB; solder joint % voids INTRODUCTION Applications for light emitting diodes (LEDs) are increasing dramatically in the lighting sector. The benefits of LEDs over competing technologies include versatility and long-term reliability. Package and luminaire design are critical considerations in ensuring that performance and reliability targets are met for commercial applications. Customer expectations for LED based luminaires (Solid State Lighting) are very high due to the relatively high cost of such luminaires. For commercial and outdoor residential lighting, 70% lumen maintenance after 35,000 hours and a (3) year warranty is required for LED packages, modules and arrays to meet Energy Star Category A criteria. For high reliability, long lifetime and color maintenance of LED lights, it is critical to have excellent assembly interconnect reliability; i.e., package to insulated metal-core substrate solder joints with low voiding for low thermal resistance and hence good heat dissipation. ASSEMBLY MATERIALS & COMPONENTS: Materials and components were chosen based on commercially available LED packages, solder pastes and MCPCB substrates. High power LED package: A high power InGaN-based LED package (Ref.1) was used in this study. It is a compact package that can be surface

mounted and can provide high lumen output and superior thermal performance. An image and cross-section of the LED package are shown in Figures 1 and 2, respectively (Ref 1).

Figure 1. Image of InGaN LED package

Figure 2. Cross section of LED package

MCPCBs and Dielectric: The LED package is a surface mount component and can be assembled on a typical FR4 board or on an MCPCB (Metal

Core Printed Circuit Board). MCPCBs are also referred as Metal Clad PCBs. An MCPCB has a thin, thermally conductive dielectric layer bonded to an aluminum or copper substrate for good heat dissipation. Each of the board materials has its own benefits and limitations. For example, a FR4 board with open or filled and capped vias is a low cost solution for a regular LED assembly. MCPCBs offer more rigidity than typical FR4 boards along with improved thermal performance, enabling heat conduction from LED packages into the metal core board material. A partial image of the MCPCB used in this study is shown in Figure 3; a 6x6 array of 36 parts per substrate was used here. A cross-section of a MCPCB is shown in Figure 4 (Ref 2).

Figure 3. Image of MCPCB Test Board

Figure 4. Cross Section of MCPCB substrate For this study MCPCB boards with two dielectric materials were used, as described below: MCPCB with Dielectric A: An MCPCB with dielectric A minimizes thermal impedance and conducts heat more effectively and efficiently than standard printed wiring boards (PWBs), an attribute important for LED packages. MCPCB with Dielectric B: Dielectric B is a low modulus dielectric designed to reduce the strain on solder joints in applications where there is a large CTE mismatch between the surface mount component and the MCPCB substrate. This dielectric is also preferred when the application

requires reliable operation over a large temperature range and number of thermal cycles, while still providing very good thermal performance. The relationship between the modulus of the MCPCB dielectric and the solder over the range of application temperatures to which the assembly will be subjected is a major factor in determining where the strain resulting from CTE mismatch between the surface mount component and substrate will be distributed. The modulus of dielectric A is of the same order of magnitude as that of most common MCPCB dielectrics available on the market, and as such can be referred to as a “standard” MCPCB material in terms of solder joint reliability. Table 1 summarizes the materials and dimensional details of the MCPCB substrates used in this study, which have ENIG surface finish. Table 1. MCPCB Materials and Thicknesses

Layer ID Material and Thickness Metal Core Aluminum: 1.57 mm

Dielectric A: 76 µm; B: 102 µm

Circuit Layer Copper: 35 µm Solder paste materials: Four different solder pastes (with four different metal alloys) were selected for this study. These pastes used Type 3 solder powder and have 88-90 wt% metal contents. Details of these solder pastes are as follows: Solder Paste A: This is a no-clean, zero halogen, and lead-free SAC305 alloy solder paste designed for a broad range of applications. This solder paste has a broad processing window thereby providing excellent print capability performance and high production yields. Solder Paste B: This is a no-clean, zero halogen, and lead-free MaxrelTM alloy solder paste that is suitable for fine feature printing applications. The MaxrelTM alloy is known for its superior thermal cycling/shock performance relative to other high temperature solder alloys. Solder Paste C: This is a no-clean, zero halogen, and lead-free SACX PlusTM0807 alloy solder paste that is suitable for fine feature printing applications and has reduced Ag level for lower cost. Solder Paste D: This is a no-clean, zero halogen, and lead-free solder paste that enables low temperature surface mount assembly due to the low melting point (<140°C) of the SnBiAg alloy. LED ASSEMBLY PROCESS Table 2 summarizes the SMT equipment that was used for the LED assembly.

Table 2. Assembly Process Equipment

SMT Equipment SMT Equipment Details

Stencil Printer Speedline MPM UP3000 Ultraflex

Pick and Place Universal Advantis with FlexJet Head

Reflow Oven Electrovert OmniFlo 7

Solder Paste Printing: Solder paste printing was done using the MPM UP3000 stencil printer with a 5 mil thick laser cut stainless steel stencil with a 1 to 1 ratio of aperture size to pad size. Stencil printing parameters used for all solder pastes are shown in Table 3. Table 3. Stencil printing parameters

Print Parameters Print Parameter Details

Print Speed 2.54 cm/sec

Print Pressure 268 grams/cm of blade

Stencil Release 0.051 cm/sec

Snap off 0 cm (on contact printing)

Component Placement: Universal Instrument’s Advantis pick and place machine with FlexJet head was used for the LED assembly. An off-center pick-up was programmed for the LED package pick-up and placement. Care was taken to avoid any contact of the nozzle exterior with the LED domed silicone lens. Reflow Soldering: An Electrovert OmniFlo 7 reflow oven, with seven heating and two cooling zones was used for the reflow assembly. All boards were assembled in an air atmosphere. Voids Measurement: A Nikon Model XTV160 Xray machine was used to measure the voids percentages (by area) of the reflowed solder joints. For each solder paste and board dielectric type, (5) boards were assembled and at least 50% of the solder joints on each board were measured for %voids. Reflow Profile Pre-Screening Test: A pre-screening test was performed using two types of reflow profiles (high soak and straight ramp), the SAC305 solder paste and MCPCB board with type B dielectric, to determine the best type of profile for the LED assembly based on percent voids in the reflowed joints. The pre-screening test results (shown in Figure 5) show that a high soak profile results in slightly fewer voids and also a narrower % voids distribution. Therefore, high soak profiles were used for this study. The high soak profiles used for the high temperature alloy solder pastes (SAC305, MaxrelTM and SACX PlusTM0807 pastes) and the low temperature SnBiAg paste are shown in Figures 6 and 7, respectively.

Str RampHigh Soak

25

20

15

10

5

0

Profile

% V

oids

5.875.71

Boxplot of % Voids - MCPCB w/ Type B Dielectric; SAC305 Alloy Paste

Figure 5. Box plot of %Voids vs Reflow Profile

Figure 6. High Soak Profile for SAC305, SACX PlusTM0807 & MaxrelTM Alloy Pastes; 150-200°C/115 sec Soak/ 240°C Peak/ 67sec TAL VOIDING TEST RESULTS The % voids data for the test boards was analyzed using Minitab and Microsoft Excel. A main effects plot for the (2) variables in this study (MCPCB board dielectric and solder paste) is shown in Figure 8. This plot shows that the board dielectric has a relatively minor effect on the overall % voids for the LED package assembled with the various solder pastes on the MCPCB boards. However, the solder paste has a significant effect on % voids. The MaxrelTM alloy paste results in average void percentages of ~15%, while the SAC305 paste results in <9% voids overall. In Figure 9 is shown a box plot for % voids verses the MCPCB board dielectric type. It shows that overall, the board dielectric had very little effect on the % voids with almost the same medians (10.5, 10.9 % voids) and ranges for both types.

Figure 7. High Soak Profile for SnBiAg Alloy Paste; 100-110°C/75 sec Soak/ 175°C Peak/ 60sec TAL

BA

35

30

25

20

15

10

5

0SnBiAgSACX0807SAC305Maxrel

Board Dielectric

Mea

n

Paste Alloy

Main Effects Plot for % VoidsData Means

Figure 8. Main Effects Plot for Board Dielectric and Solder Paste In Figure 10 is shown a box plot for % voids by MCPCB board dielectric type and solder paste alloy. Apparent here is a slight effect of board dielectric type for the different solder pastes, but the trend varies depending on paste alloy. For the MaxrelTM and SAC305 alloy pastes, the type B dielectric results in lower voids percentages, while for the SACX PlusTM0807 and SnBiAg alloy pastes the type A board dielectric results in lower voids percentages. The SAC305 solder paste results in the lowest void percentage of the four pastes; this particular solder paste is known for its’ low voiding attribute. Note that all of the solder pastes resulted in <20% voids, meeting the IPC Class 2 voids specification.

BA

35

30

25

20

15

10

5

0

Board Dielectric

% V

oids

10.80510.465

Boxplot of % Voids

Figure 9. Box Plot of %Voids Verses MCPCB Board Dielectric

Paste AlloyBoard Dielectric

SnBiAgSACX0807SAC305MaxrelBABABABA

35

30

25

20

15

10

5

0

% V

oids 20

Boxplot of % Voids

Figure 10. Box Plot of % Voids verses Board Dielectric Type and Paste Alloy Figure 11 is a bar chart of void size verses the % of solder joints. Overall, >90% of the solder joints have void sizes that are 0-4% of the solder joint area. The “Zero” value on the x-axis refers to void sizes that are <0.005%.

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

% o

f J

oin

ts

ZERO 0-4% 4-8% 8-12% 12-16% 16-20% >20%

Void Size as % of Joint Area

LED Assembly Voids Sizes

B Diel/ SAC305A Diel/ SAC305A Diel/ SnBiAgB Diel/ SnBiAgA Diel/ MaxrelB Diel/ MaxrelA Diel/ SACX0807B Diel/ SACX0807

Figure 11. LED Assembly Void Sizes

Figures 12 and 13 are bar charts of the average and maximum void sizes, respectively, as a function of solder paste alloy and MCPCB dielectric type. For all (4) solder pastes, the type A MCPCB dielectric results in smaller average and maximum void sizes than does the type B dielectric. The low melting point SnBiAg paste results in the smallest average void size, probably because it is reflowed at a lower temperature than the SAC and MaxrelTM alloy pastes. In terms of maximum void size, the SAC305 and SnBiAg alloy pastes are comparable, with maximum void sizes of 10~13% of the joint area.

LED Assembly Average Void Size

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

SAC305 Maxrel SACX0807 SnBiAg

Paste Alloy

Ave

rge

Vo

id S

ize

(% jo

int

area

) Dielectric A

Dielectric B

Figure 12. LED Assembly Average Void Sizes

LED Assembly Max. Void Size

0.0

5.0

10.0

15.0

20.0

25.0

30.0

SAC305 Maxrel SACX0807 SnBiAg

Paste Alloy

Ma

x. V

oid

Siz

e (

% jo

int a

rea

) Dielectric A

Dielectric B

Figure 13. LED Assembly Maximum Void Sizes Table 4 shows typical Xray voids images and corresponding voids percentages for each solder paste and board dielectric combination. SUMMARY AND CONCLUSIONS Commercially available solder pastes with (4) different metal alloys were evaluated for % voids in the reflowed joints when used to attach a commercially available LED package on MCPCB substrates having (2) different dielectric types. The SAC305 alloy paste results in the

lowest void percentages in the reflowed joints for both MCPCB dielectrics. This particular paste is known for its good voiding performance. Not discussed herein, but key, is the effect of paste flux on voiding. The effect of board dielectric type on voiding performance is solder paste specific with (2) of the pastes resulting in lower % voids when reflowed on boards with the type A dielectric (SACX PlusTM0807 and SnBiAg pastes) and (2) pastes showing better voids performance on boards with the type B dielectric (SAC305, MaxrelTM). In terms of average and maximum void sizes, the reflowed joints for the type A dielectric boards are superior for all pastes, and the SnBiAg paste results in the smallest void sizes. Table 4. X-ray Voids Images

Solder Paste

MCPCB Dielectric A

MCPCB Dielectric B

A (SAC305)

9.25%

7.2%

B (Maxrel™)

15.8%

12.6%

C (SACX0807)

10.0%

12.3%

D (SnBiAg)

11.6%

12.3%

Overall, for all pastes and board dielectric types, >90% of the solder joints had void sizes of 0-4% of the solder joint area and less than 20% voids on average. The SAC305 alloy paste combined with the type B board dielectric results in the lowest % voids (<8.5%). The boards assembled for this study will be subjected to further tests including electrical measurements, die shear, thermal cycling, thermal shock and solder joint characterization by cross-sectioning (Ref.3).

ACKNOWLEDGEMENTS The authors gratefully acknowledge the contributions of George Banis (an Intern working with CE) and Esse Leak to this work. REFERENCES 1. LUXEON® Rebel Board Design and Assembly

Application Brief AB32; ©2008 Philips Lumileds Lighting Company.

2. Thermal Management for LED Applications – Solutions Guide, The Bergquist Company.

3. R. Raut, R. Bhatkal, W. Bent, B. Singh, S. Chegudi, and R. Pandher, “Assembly Interconnect Reliability in Solid State Lighting Applications – Part 1”, Proceedings of the Pan Pacific Microelectronics Symposium, Hawaii, January 18-20, 2011.

ASSEMBLY INTERCONNECT RELIABILITY IN SOLID STATE LIGHTING APPLICATIONS – PART 1

Rahul Raut, Ravi Bhatkal, Westin Bent, Bawa Singh, Sujatha Chegudi and

Ranjit Pandher Alpha, an Alent plc Company

South Plainfield, NJ, USA, 07080 [email protected]

Justin Kolbe and Sanjay Misra

The Bergquist Company, 18930 W 78th Street, Chanhassen, MN 55317

ABSTRACT Customer expectations for light emitting diode (LED) based luminaries (Solid State Lighting) are very high due to the relatively high cost of such luminaries. For commercial and outdoor residential applications, a B50, L70 of 35,000 hours and a 3 year warranty is needed to meet EnergyStar Category A requirements. For such high reliability and lifetime requirements, it is critical to have excellent assembly interconnect reliability (i.e. Package to Insulated Metal Substrate attach). This study presents the results of initial work related to understanding the reliability of Solid State Lighting assembly interconnects in a LED Package-Insulated Metal Substrate system. INTRODUCTION Applications for light emitting diodes (LEDs) are increasing dramatically in the lighting sector. Their benefits of LEDs over competing technologies include versatility and long-term reliability. Package and luminaire design are critical considerations in ensuring that performance and reliability targets are met for commercial applications. Customer expectations for LED based luminaries (Solid State Lighting) are very high due to the relatively high cost of such luminaries. For commercial and outdoor residential applications, a B50, L70 of 35,000 hours and a 3 year warranty is needed to meet EnergyStar Category A requirements. For such high reliability and lifetime requirements, it is critical to have excellent assembly interconnect reliability (i.e. Package to Insulated Metal Substrate attach). This study covers the selection of various materials and development of assembly process. The results of initial work related to understanding the reliability of Solid State Lighting assembly interconnect in a LED Package-Insulated Metal Substrate system are discussed along with the process recommendations.

SELECTION OF ASSEMBLY MATERIALS & LED PACKAGE: Materials were chosen based on commercially available LED package, solder paste and MCPCB substrates and compared to potential improvements in solder pastes and MCPCB substrate for the same LED package. Selection of high power LED package: In this study, LUXEON® Rebel a high power LED package manufactured by Philips Lumileds Lighting Company was used. It is a compact package that can be surface mounted and can provide high lumen output and superior thermal performance. From the InGaN and AlInGaP metallization patterns, we selected an InGaN LED package. Image of an InGaN Rebel package with isolated fiducials is shown in Figure 1. A cross section of the Rebel package is shown in Figure 2 (Ref 1).

Figure 1. Image of InGaN LUXEON Rebel package

Figure 2. Cross section of LUXEON Rebel package Selection of MCPCBs and Dielectric: The LUXEON Rebel is a surface mount component and can be assembled on a typical FR4 board or on an MCPCB (Metal Core PCB). MCPCBs are also referred as Metal Clad PCBs. An MCPCB has a thin thermally conductive layer bonded to aluminum or copper substrate for heat dissipation. Each of the board material has its own benefits and limitations. For example a FR4 board with open or filled and capped vias is a low cost solution for a regular LED assembly. MCPCBs offer more rigidity than a typical FR4 board along with improved thermal performance as all of the SSL packages conduct heat into the board material. An image of the MCPCB is shown in Figure 3. A cross-section of a MCPCB is shown in Figure 4 (Ref 2). Table 1 shows basic details of a typical MCPCB. In this study we selected an MCPCB with two dielectric materials as described below: MCPCB with Dielectric A: MCPCB with dielectric A minimizes thermal impedance and conducts heat more effectively and efficiently than standard printed wiring boards (PWBs).The low thermal impedance of MCPCB’s outperform other PCB materials and offers a cost effective solution, eliminating additional LEDs for simplified designs and an overall less complicated production process. MCPCB with Dielectric B: Dielectric B is a low modulus dielectric designed to reduce the strain on solder joints in applications where there is a large CTE mismatch between the surface mount component and the substrate of the MCPCB and a significant combination of temperature range and number of cycles in the application as well as high reliability requirements, while still providing very good thermal performance.

Base Layer

0.020”-0.125” / 0.5 –3.2 mm

Aluminum, Copper, Steel, or exotic

Dielectric 0.003”-0.006” / 75 -150 micron

Usually includes thermally conductive electrical insulator

Circuit Layer

1 oz –10 oz / 35 –350 micron

One or two-layer copper is common. More layers can be used

Table 1. Basic details of MCPCB

The relationship between the modulus of the dielectric in the MCPCB and the solder over the range of application temperatures that the assembly will be subjected to is a major factor in determining where the strain resulting from CTE mismatch between the surface mount component and substrate will be distributed. The modulus of dielectric A is of the same order of magnitude as most common MCPCB dielectrics available on the market, and as such can be referred to as a ‘standard’ MCPCB material in terms of solder joint reliability

Figure 3. MCPCB Test Vehicle used for the study

Figure 4. Cross section of a typical MCPCB

Selection of solder paste materials: Two different solder pastes were selected for this study. Details of these solder pastes are: Solder Paste A: A no-clean, lead-free SAC305 alloy solder paste with Type 3 grade solder powder, designed for a broad range of applications was selected for this study. This solder paste has a broad processing window therby providing excellent print capability performance and high production yields. Solder Paste B: A no-clean, lead-free Maxrel™ based alloy solder paste with Type 3 grade solder powder, that is suitable for fine feature printing application was used in this experiment. ASSEMBLY PROCESS DEVELOPMENT: After selection of LED package, soldering and dielectric materials, a robust assembly process was developed. Assembly was performed on the same day for all the test boards and pastes. Table 2 summarizes the SMT equipment that was used for this LED assembly.

SMT Equipment SMT Equipment Details

Stencil Printer Speedline MPM UP3000 Ultraflex

Pick and Place Universal Advantis with FlexJet head

Reflow Oven Electrovert OmniFlo 7

Table 2. Assembly process equipment Detailed assembly process parameters are discussed in the following three sections: Solder Paste Printing: MPM UP3000 stencil printer was used for solder paste printing. A 5mil thick Ni electroform stencil with 1:1 aperture was selected. Though stencil design can be optimized further, a 1:1 aperture stencil data has initially been generated for setting a baseline data. Stencil print parameters used for both solder pastes are shown in Table 3.

Print Parameters Print Parameter Details

Print Speed 1 inch / sec

Print Pressure 1.5 lbs / inch of blade

Stencil Release 0.02 inches / sec

Snap off 0 inches (on contact printing)

Table 3. Stencil print parameters Component Placement: Universal Instrument’s Advantis pick and place machine with FlexJet head was used for the LED assembly. An off-center pick-up was programmed for the LUXEON Rebel package pick-up and placement. Care was taken to avoid any contact / touching of the nozzle exterior to the silicone lens (LED dome). Reflow Soldering: An Electrovert OmniFlo 7 reflow oven, with seven heating zones and two cooling zones was used for the reflow assembly. All boards were assembled in an air atmosphere. A straight ramp reflow profile with a peak temperature of 240°C was used for both solder pastes. Please refer to Figure 5 for the reflow profile details. FUNCTIONAL AND RELIABILITY TESTING A comprehensive evaluation of the assembled LEDs has been undertaken. This evaluation includes both functional, mechanical and reliability testing of the assembled LED packages. The comprehensive test matrix being investigated is shown in Table 5. This paper presents results from the air to air thermal cycling tests. 1. Electrical Measurements: Test description: Electrical measurements were performed on the as assembled (as soldered) LED packages. Measurements were performed after boards went through air to air thermal cycling test. Test method: A power supply with the output set at 3V and the current limited over 1 Amp was used to perform the testing. Measurements were done on as soldered boards and on the boards that went through thermal cycling every 100 cycles.

Figure 5. MCPCB Straight Ramp Profile - 1.2C/s 240°C Peak 55s TAL

TEST NAME TEST DESCRIPTION

1 Electrical measurements

‘Initial Amperes’ measurement Initial LEDs (as assembled) After thermal cycling& After thermal shock

2 Voiding analysis Voiding performance for each solder paste on two dielectric materials

3 Thermal cycling analysis

Thermal cycling air to air analysis -40°C to 125°C, 1000 cycles with dwell time of 30 minutes

4 Thermal shock analysis

Thermal shock liquid to liquid analysis -40°C to 105°C, 1000 cycles with dwell time of 30 minutes

5 Solder joint characterization

Cross sections of LEDs and IMC measurements: Initial LEDs (as assembled) After thermal cycling & After thermal shock

6 Mechanical testing (Package shear)

Package shear: Initial LEDs (as assembled) After thermal cycling

Table 5. Test matrix for functional, mechanical and reliability testing

Test results on as assembled boards:

Dielectric-BDielectric-A

0.26

0.25

0.24

0.23

0.22

0.21

0.20

SolderPaste-BSolderPaste-A

Dielectric

Mea

n

Solder Pastes

Main Effects Plot for Initial AmpsData Means

Figure 6. Initial Amperage for different solder pastes and

board dielectrics Figure 6 shows the main effects plot with electrical measurements on as assembled boards. The solder pastes appear to have a greater effect on amperage than the dielectric material. 2. Thermal Cycling Analysis: Test description: For reliability study, air to air thermal cycling was performed on the assembled boards. Test details: Assembled boards were placed in a Thermotron thermal cycling chamber for reliability studies at -40°C to 125°C, with 30 minute dwell time. Electrical measurements were undertaken with a power supply with a voltage limit of 3.0 volts and a current limit of 2 amps at 0 cycles and then every 100 cycles. Working LEDs were considered as passing, and non-working or dark LEDs were considered failing. Test results and observations:

‐60

‐40

‐20

0

20

40

60

80

100

120

140

12:00:00 12:14:24 12:28:48 12:43:12 12:57:36 13:12:00 13:26:24 13:40:48

Temperature (degrees C)

Time (hr:min:sec)

Air to Air Thermal Cycle

Figure 7: Thermal cycles as measured in the Thermotron

environmental chamber

0

0.2

0.4

0.6

0.8

1

1.2

0 200 400 600 800 1000 1200

percent of population w

ith the light still on

Thermal Cycles (‐40C to 125C, 30 minute dwell time)

Failure Rates of Thermally Cycled LEDs

Dielectric A, Solder A

Dielectric B, Solder A

Dielectric A, Solder B

Dielectric B, Solder B

Figure 8: Failure rate vs. number of thermal cycles of

combinations of MCPCB dielectrics and solders

Figure 8 shows the failure rate as a function of the number of thermal cycles of combinations of MCPCB dielectrics and solders. It is clear that with the lower modulus dielectric, joints with both solder paste A and solder paste B show almost no failures over 1000 cycles. With the higher, modulus dielectric, joints with solder paste B with Maxrel™ alloy show much lower failure rates than those with solder paste A with SAC305 alloy. 3. Solder Joint Characterization: Test description: For solder joint characterization, as assembled boards were cross sectioned for microstructure and IMC measurement analysis. Test details: IMC measurements on the MCPCB A and MCPCB B were performed on as assembled boards for both solder pastes used. SEM images of the cross-sections for both solder pastes were taken and are shown in Figure 9. All IMC measurements are in microns. Test results and observations: SEM images and IMC measurements show: - Presence of a continuous Ni layer was noted at the

interface of the MCPCB and solder pastes. - Both Solder paste A and Solder paste B had similar

IMC thickness on MCPCB A (around 1.65 micron). For MCPCB B material, Solder paste A had IMC thickness of 1.3 microns while Solder paste B had IMC thickness of 1.08 microns.

4. Voiding Analysis, Thermal Shock and Component

Shear: Voiding analysis, Thermal shock and Component shear tests are currently underway and will be published in Phase II of this work.

Figure 9. SEM micrographs of solder joints on MCPCB A

for Solder Paste A and Solder Paste B CONCLUSIONS AND SUMMARY From the test results, one can conclude that: 1. The creep resistance of the solder is a significant factor

in minimizing failures in solder joints due to strains incurred in thermal cycling.

2. The relationship between the modulus of the dielectric to the modulus of the solder over the temperature range in the thermal cycle can be an effective way to manipulate the strain away from the solder joint in thermal cycling, hence reducing failures due to solder joint fatigue.

Further, it is well understood in the literature that the magnitude of the thermal cycle, the geometry of the assembly under test, the CTE mismatch of the materials, and the duration of the dwell time in the thermal cycle (up to the time it takes for creep in the solder joint to be complete) will also have an impact on the device reliability as a function of

solder joint fatigue and cracking in thermal cycling. With that understanding, we would expect that: 1. An MCPCB with a copper substrate would put less

strain on the solder joint resulting in less damage to solder joints.

2. A smaller magnitude thermal cycle (such as one for indoor lighting applications) should also cause less strain on the solder joint.

3. A shorter dwell time at the extreme temperatures would allow the solder joint less time to creep, resulting in less damage to the joint per cycle.

4. Using a more creep resistant solder material would increase reliability of the solder joints subjected to such cycling.

5. The combination of solder and dielectric materials can be optimized in order to provide the required reliability for a given application.

ACKNOWLEDGEMENTS The authors would like to thank Proloy Nandi and Anil Kumar K. REFERENCES 1. ‘LUXEON® Rebel Board Design and Assembly

Application Brief AB32 (10/08)’ by Philips Lumileds Lighting Company.

2. ‘Thermal Management for LED Applications – Solutions Guide’ by Bergquist Company.

3. ‘Performance and Reliability of Thermal Management Substrates for LEDs’ by Justin Kolbe and Sanjay Misra.

0-Cycles – Solder Paste B

Cu

Solder

Ni Layer

Cu Ni Layer

IMC

Solder

0-Cycles – Solder Paste A

IMC

Impact of Substrate Materials on Reliability of High Power LED Assemblies

Ranjit Pandher, Ph.D. and Ravi Bhatkal, Ph.D.

Alpha Assembly Solutions, a MacDermid Performance Solutions Business South Plainfield, NJ, USA

[email protected]

Kurt-Jürgen Lang Osram Opto Semiconductors, Regensburg, Germany

ABSTRACT New high power LED package designs provide high lumen density that can enable significant system cost reductions through fewer LEDs and smaller PCBs. The materials stack determines the CTE mismatch between the high power LED ceramic sub-mount and the substrates (including Metal Core PCB or FR4 substrate types). Choice of the substrate can impact reliability of the solder joints in thermal shock/cycling. One of the key questions is: What role does the substrate type play in the LED package-to-board assembly reliability? This paper presents a study to help answer this question. Assembly of high power ceramic sub-mount LEDs was conducted with both aluminum MCPCB and FR4 substrates with multiple solder alloys. Thermal cycling was conducted under the conditions of -40C to 125C for 1000 cycles. Solder joint strength was measured at multiple intervals during thermal cycling by conducting package shear. The impact of substrate type is quantified for multiple solder alloys and recommendations are presented. Solder alloy characteristics and failure mechanisms that impact reliability for a given substrate are discussed. Key words: LED, MCPCB, Substrates, Thermo-mechanical reliability INTRODUCTION Development of high power blue LEDs brought the use of LED in general lighting to a reality. For LED lights to compete with other traditional lighting technologies such as incandescent and Compact Fluorescent Lamps (CFL), they had to have good luminous efficacy and long operating life while maintaining competitive cost structures. While LED chip designers were working to improve the quantum efficiency of the LED chip itself, the packaging and assembly industry started exploring backend process materials and processes to improve performance and reduce costs. While it is well known that LEDs chips are efficient in converting electrical energy to light energy as compared to others (and are expected to be more efficient in the future as scientists are working new chip designs, materials and processes), there remains a large fraction of electrical energy is lost as heat[1]. Removal of this heat from the chip to ambient has been a challenge for the LED packaging

industry[2]. The mechanism of heat dissipation in LEDs is totally different from that observed in incandescent lamps and CFLs. For example, the filament temperature in an incandescent lamp is ~2500C, while the typical LED chip junction temperature is below 125C. In incandescent lamps, a significant amount of unwanted heat generated is dissipated as infra-red (IR) radiation while heat transfer by radiative process in LEDs is negligible. The primary mode of heat dissipation in LED is conduction through the substrate. Therefore, the LED packaging and assembly industry had to find creative ways to find a low resistance heat conduction path from LED to ambient. This led to development of new packaging materials including the sub-mounts/substrates, circuit boards and materials used to join these parts. This study investigates the impact of substrate materials on long-term reliability of high power LEDs. Traditionally, LED dies are mounted on an Al2O3 or AlN sub-mount using a die attach material. Then this LED package is assembled with solder materials on a circuit board. In a new emerging packaging process, LED die are directly attached on a circuit board through a chip-on-board (COB) process. In both packaging schemes, the circuit board technologies, in addition to its primary role of providing a mechanical fixture and path for electrical connections, also provide a route for heat dissipation from LED die to the heat sink. Therefore, appropriate selection of the circuit board material is of utmost importance as the total thermal resistance of the whole stack should be as low as possible (provide ref). Materials with poor thermal conductivity can result in fast degradation of the LED due to high temperature operation at high power [3]. Operating the LED at lower current to maximize efficiency, limits the total light output from the LED.

Table I: Properties of common materials used in substrates and circuit boards.

Material Thermal Conductivity

(W/m.K)

Coefficient of Thermal Expansion (CTE)

(ppm/K) Aluminum (MCPCB

204 25

Copper (MCPCB)

386 16

FR4 (PCB) 0.3-0.8 17 Al2O3 (Sub-mount)

18 7

AlN (Sub-mount)

140 4

Table I shows two of the most important properties of a few common materials used in high power LED substrates and circuit boards [4]. Al-core and Cu-core MCPCBs have the best thermal conductivity. Even though the thermal conductivity of the substrate material determines its heat dissipation capability, other properties such as CTE and strength and modulus of the material will determine its long-term performance in high stress situations. EXPERIMENTAL DETAILS A comprehensive study was undertaken with multiple variables. Details of the Test Vehicle, LED Package and solder paste used are summarized in this section. Table II: Substrate Materials

Substrate Materials Details: FR-4 Epoxy / Fiber Glass AL MCPCBs TC LM AL MCPCBs TC MP

Package - Oslon LED A commercially available LED package (Oslon LX) was used in this study[4]. OSLON LEDs are used in applications that need maximum luminous flux with little consumption of space, and with a very stringent lifetime requirements [4]It is a square LED with a ceramic base and integrated contacts (bottom terminated) and a hard silicone cast as lens. Figures 1 and 2show the schematics of Oslon LED package[5]. This LED is compatible for Pb-free soldering (what does this statement mean?) and can be surface mounted. Their performance and design, make them suitable for various forms of lighting and illumination technology, ranging from general lighting, industry, backlighting, projection and automotive applications. Due to their very compact design, the LEDs are also particularly suitable for being operated in clusters. The ceramic base has the decisive advantage that it is stable with regard to light, regardless of the wavelength. In addition, it has sufficiently good thermal conductivity and enables thermal connection to the PC board.

Details of the package used are as follows:

- Thin GaN Technology - Part Number: LXW CNAP - Type: LMW CNAP-6J7K-37-DF-LH

Figure 1: Oslon LED structure.

Figure 2: Primary heat flow in the Oslon

Solder Pastes Two different solder pastes with Pb-free alloys were selected for this study. Table III: Solder Paste details

Solder Paste Solder Alloy

NC Paste#1 SAC305 Type 4

NC Paste#2 Maxrel Alloy Type 4

Table IV: Test Matrix Test Factors/Variables:

PCB Substrates FR-4 (Epoxy / Fiber Glass) AL MCPCBs (TC MP) AL MCPCBs (TC LM)

Solder Paste

NC Paste # 1 (with SAC305 Alloy) NC Paste# 2 (with Maxrel Alloy)

Reflow Profile 260C LV Constant Factors: Reflow Environment

N2

Package Osram Oslon Table V: Evaluation Matrix:

Test Initial (O Cycles)

500 Cycles

1000 Cycles

1 Voiding – X-Ray Analysis

All Parts

2 Thermal Cycling 3 Package Shear 10% 10% 10% 4 Cross-section

(IMC Measurement)

10% 10% 10%

5 Failure Analysis 10% 10% 10% ASSEMBLY Table VI List the SMT equipment that was used for the LED assembly. Table VI: Assembly Process Equipment

SMT Equipment SMT Equipment Details Stencil Printer DEK Horizon 03iX Stencil 4 mil Laser Cut Stainless

Steel Pick and Place Universal Advantis with

FlexJet Head Placement Nozzle 234J-FJ Reflow Oven Electrovert OmniFlo 7

Solder Paste Printing: Solder paste printing was done using DEK Horizon 03iX printer with a 4 mil thick laser cut stainless steel stencil with a 1 to 1 ratio of aperture size to pad size. Stencil printing parameters used for all solder pastes are shown in Table VII below. Table VII: Stencil printing parameters

SMT Equipment SMT Equipment Details Print Speed 1 inch/sec. Print Pressure 1.25 lbs/inch of blade Stencil Release 0.02 inches/sec. Snap off 0 inches (on contact printing)

Component Placement: Universal Instrument’s Advantis pick and place machine with FlexJet head was used for the LED assembly. Placement nozzle 234J-FJ was used for the LED package pick-up and placement. Reflow Soldering: An Electrovert OmniFlo 7 reflow oven, with seven heating and two cooling zones was used for the reflow assembly. The reflow profile used is shown in Figure 3. Table VIII: Test Conditions

Test Conditions: Temperature 20°C Relative Humidity 46% RH

Reflow Atmosphere Nitrogen (<500 ppm O2 throughout the assembly process)

Figure 3: Reflow profile Thermal Cycling Test Test description: Air to air thermal cycling was performed on the assembled boards. Test details: Assembled boards were placed in an air-to-air dual chamber thermal cycling chamber with a temperature profile ranging from -40°C to 125°C, with 15 minute dwell time at extreme temperatures. Cycle time was 40 minutes. The Thermal Cycling Profile is shown in Figure 4 below.

Figure 4: Temperature Cycling profile.

Temperature Cycel TC

-60

-40

-20

0

20

40

60

80

100

120

140

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85

Time [min]

Tem

p [°C

]

Solder Joint Shear Test To assess the mechanical integrity of the solder joints, joints were sheared and peak shear force was recorded for each of the sheared components. A Dage 4000 shear tester was used for Oslon Package Shear. Eight components were sheared for each set. After temperature cycling, parts were taken out after 500 and 1000 cycles and sheared to record any drop in solder joint strength. RESULTS AND DISCUSSION PACKAGE SHEAR TEST DATA Test description: For the reliability study, shear tests were performed on the assembled boards. These included initial shear, after 500 TCs and 1000 TCs.

Figure 5: Package Shear Results - SAC305 solder.

Figure 6: Package Shear Results – Maxrel solder. Figures 5 and 6 show the shear test results on LEDs assembled with NC Paste # 1-SAC305 and NC Paste # 2 with Maxrel alloy respectively. Shear data is shown for the LEDs assembled on FR4 and MCPCB-MP test boards. No shear data was generated on LEDs on MCPCB-LM boards because the dielectric used in LM boards is so soft that dielectric itself is torn during the shear test. Therefore, shear test results on LM boards were not representative of the solder joint strength. As seen in Figures 5 and 6, Shear strength of LEDs on FR4 substrates sees almost no change after 1000 cycles while that

on MCPCB-MP show a drop by 60% for LEDs assembled with P33-SAC305. The drop in shear strength of LEDs on MCPCB-MP for LEDS assembled with NC Paste # 2 with Maxrel alloy is about 20%.

Figure 7: Percentage drop in package shear strength after 1000 cycles. Figure 7 shows the % drop in shear strength. This can be explained keeping in mind the physical properties of the test board materials and LED package substrate. During temperature cycling the solder joints experience cyclic stress in the lateral direction due to CTE mismatch between the circuit board material and the LED sub-mount material. As shown in table I, the CTE of FR4 is 17 ppm/K and Aluminum is 25 ppm/K while that of Al2O3(LED substrate) is 7ppm/K. Therefore, the CTE mismatch for LEDs assembled on FR4 boards is 10ppm/k while those assembled on MCPCB-MP boards is 17ppm/k. Therefore, the solder joints in LEDs on MCPCB will experience much higher stress during temperature cycling as compared to those assembled on FR4 boards. In addition to CTE mismatch, modulus of the materials involved also plays a key role. While solder joint is experiencing a cyclic stress during temperature cycling if the circuit board material is soft (have low modulus), it will tend to deform first which will in turn reduce stress at the solder joint. FR4 has relatively lower modulus than Aluminum, therefore, stress on the solder joints of LEDs on FR4 boards will still be lower. That also further explains almost no drop in shear strength of the LEDs on FR4 boards. As seen in Figure 7, the drop in shear strength of LEDs on MCPCB assembled with SAC305 solder is 60% while for the LEDs assembled on with Maxrel solder drop in shear strength is only 20%. This is due the fact that Maxrel solder is designed to withstand high stress situations.

CROSS-SECTION ANALYSIS OF SOLDER JOINTS

Figure 8: NC Paste # 1 with SAC305 on MCPCB-MP after 1000 cycles. Cracks are observed in solder joints for all three pads.

Figure 9: NC Paste # 2 with Maxrel alloy on MCPCB-MP after 1000 cycles. Small cracks observed in solder joints on only one of the pads. Figures 8 and 9 show pictures of typical cross-sectioned solder joints. The cross-section analysis shows that: SAC305 alloy joints on MCPCB-MP show cracking after 1000 cycles for all three pads. Maxrel alloy joints on MCPCB-MP show only minor cracking (and only on one side of the pad) after 1000 cycles, and crack growth is minimal. Interestingly, Maxrel alloy joints showed no cracks in assemblies on FR4 and MCPCB-LM even after 1000 cycles. OBSERVATIONS AND CONCLUSIONS Performance of LEDs assembled on three types of the substrates has been compared. Key observations are:

• LEDs on FR4 boards show minimal drop in shear strength irrespective of the solder alloy.

• Due to high mismatch in CTE, the MCPCB-MP substrates show a steep degradation of shear strength upon temperature cycling.

• Maxrel alloy showed highest strength and little drop in shear strength after thermal cycling.

• In thermal cycling test, Maxrel alloy showed stable performance on all types of substrates.

In conclusion, for a given alloy (SAC305 or HR Pb-Free), FR4 shows the least drop in shear strength of the joints. In the case of MCPCB-MP substrates, Maxrel shows the highest reliability. ACKNOWLEDGEMENTS The authors would like to thank Westin Bent and Ramazan Soydan of Alpha for their help in assembly of the LEDs, testing and analysis. REFERENCES

[1] M. H. Crawford, J. J. Wierer, A. J. Fischer, G. T. Wang, D. D. Koleske, G. S. Subramania, M. E. Coltrin, R. F. Karlicek, Jr., and J. Y. Tsao, “Solid-State Lighting: Toward Smart and Ultraefficient Materials, Devices, Lamps, and Systems 1”, in D.L. Andrews, Ed., “Photonics Volume 3: Photonics Technology and Instrumentation” (Wiley, 2013).

[2] Mehmet Arik, Charles Becker, Stanton Weaver and James Petroski, “Thermal Management of LEDs: Package to System”, Third International Conference on Solid State Lighting, edited by Ian T. Ferguson, Nadarajah Narendran, Steven P. DenBaars, John C. Carrano, Proc. of SPIE Vol. 5187.

[3] Steven Keeping, “Understanding the Cause of Fading in High-Brightness LEDs”, Electronic Products Feb 2012

[4] Andreas Stich, Kurt-Jürgen Lang, Rainer Huber “Details of the Assembly and Solder Pad Design of the OSLON, OSLON SSL and OSLON Square Family” an Application Note, Osram Opto Semiconductors.

[5] Reliability of the OSLON Product Family” an Application Note, Osram Opto Semiconductors.

“

FATIGUE LIFE PREDICTION MODEL FOR LEDS ON METAL CORE PRINTED

CIRCUIT BOARDS (MCPCBS) WITH PB-FREE SOLDER ALLOYS

Maxim Serebreni1, Nathan Blattau1, Craig Hillman1, Ravi Bhatkal2, Gyan Dutt2, Ranjit Pandher2

1DfR Solutions, 9000 Virginia Manor Rd #290, Beltsville MD 20705 [email protected]

2Alpha Assembly, 300 Atrium Drive, Somerset NJ 08873 [email protected]

ABSTRACT There is currently no applicable model for solder fatigue of components attached to Metal Core Printed Circuit Boards (MCPCBs). The increased implementation of MCPCBs for LED lighting application has introduced large variability in material properties of the base substrate material, dielectric material and LED package materials. The contribution of the exact combination of MCPCB material properties and package type on the solder interconnects fatigue under cyclic thermal loads cannot be analyzed currently without complex numerical simulations. This study proposes an improved semi-analytical model to predict the fatigue life of LED solder interconnects under fluctuating thermal conditions. Strain energy calculations were performed by incorporating the effective interfacial stiffness and material properties of each layer in the LED and MCPCB assembly. In addition, SAC305 and a High Creep Resistant Solder Alloy Alpha Maxrel™ (CRA) were assessed in combination of different dielectric materials. CRA demonstrated better fatigue performance compared to conventional SAC305 solder. The semi-analytical model enables to determine trends in fatigue life predictions of solder interconnects due to changes in MCPCB and solder alloy materials and geometry. This study has shown the applicability of the semi-analytical model to LEDs assembled on MCPCB using conventional and high reliability solder alloys. Key words: LED solder joint reliability, MCPCB, Fatigue life prediction model, dielectric, creep resistant alloy INTRODUCTION Light emitting diodes (LEDs) are solid-state lighting sources which enable high energy efficiency and compact form factors with longer life than conventional fluorescent lights. Since LEDs are semiconductor powered devices they require materials and processing which subject them to distinct failure modes and mechanisms. Failure modes in LED range from lumen degradation to short circuits. Causes for these failure modes vary from thermo-mechanical overstress, electrical overstress, thermal resistance increases etc. [1].

Interconnect failure, primarily in the anode or cathode solder joints can be classified as a system level failure. This failure mechanism is driven by thermal cycling and carries highest degree of risk during the operational lifetimes of LEDs. During the lifetime of the component, fluctuations in temperature cause cyclic expansion and contraction. Due to the mismatch in coefficient of thermal expansion (CTE) within the LED package and with the MCPCB, fatigue failure of solder joints can occur and results in catastrophic failure [2]. Factors contributing to the wear out of solder joint in LED packages can be driven by internal heating as the device is powered on and off, changes in operating environment and cooling system degradation in high power applications which can result in an increase of the junction temperature and accelerate solder joint fatigue. Voids in solder joints can increase the thermal resistance and reduce the heat dissipation to the substrate. These are process induced factors which negatively affect interconnect life by predefining the fatigue life of the LED package throughout its operational lifetime. LED light engines are either chip-on-board (COB) or package-on-board assemblies. Thermo-mechanical fatigue is of major concern in package-on-board assemblies in which the dominant CTE mismatch is between the LED package and circuit board [3]. LED packages are usually bonded to ceramic metal or FR4 substrates using variety of solder alloys. Insulated metal substrates (IMS) often referred to as Metal Core Printed Circuit Boards (MCPCBs) are comprised of a metal PCB substrate bonded to copper traces using a thin thermally conductive dielectric layer as shown in Figure 1. MCPCBs are commonly used in high-power LED applications along with FR4 laminates. The most common MCPCB substrates utilize aluminum or copper for their superior thermal conductivity. The thin dielectric material used with MCPCBs provides electrical insulation and offers high thermal conductivity and bonds the base metal and copper circuit metal together. Popular dielectric materials used in MCPCB applications are epoxy or polyimide thin films and their derivatives. Significant change in mechanical and electrical properties occurs above the dielectric material glass transition

mailto:[email protected]

temperature (Tg). Change in peel stress of the copper layer, increase in CTE and decrease in storage modulus can occur simultaneously across the Tg. These changes in mechanical properties contribute to reduction of strain in the Z-axis during thermal expansion [5].

Figure 1. Cross-section of conventional PCPCB [4] The model presented in this work follows the methodology of one dimensional strain energy models. One-dimensional creep strain energy density models have been extensively developed, applied and validated by Clech for a variety of solder alloys in leaded and leadless electronic components [6-9]. Similar models have been previously developed for solder joints in various electronic packages ranging from flip chip BGAs with underfill to chip components [10-12]. These models implement analytical formulations to describe the mechanical loads solders joints experience during thermal expansion of the components or assemblies along with empirical parameters to correlate the strain energy with thermal cycles to failure. Some of the limitations of these models is the non-convergence of creep energy hysteresis loop for solder joints under field conditions which experience much lower temperatures than ones under accelerated life testing. Therefore, these models rely on acceleration factors to correlate the fatigue life from high temperatures environments to lower temperature field conditions. In the model proposed in this paper, strain energy density is calculated only from the shear stress and strains due to global CTE mismatch between the substrate and chip component. The model is optimized for LED packages on MCPCB by incorporating the change in mechanical properties of the dielectric materials and variation in creep behavior of solder alloys. To better understand the effect of CTE mismatch on fatigue life of solder interconnects in LED packages, these complex interactions are incorporated in a simple to use analytical model. MATERIAL PROPERTIES The dependence of solder material elastic modulus on temperature is necessary in order to determine the stresses and strains solder interconnects are exposed to at various temperatures. Figure 2 shows the measured elastic modulus of CRA (Alpha Maxrel™) and SAC305 solder alloys. Both alloys show a near linear dependence of the elastic modulus with temperature with CRA alloy having larger modulus up

to a temperature of 140ºC. It important to note that even slight changes in solder alloy composition and microstructure can result in largely dissimilar temperature dependent properties [13].

Figure 2. Elastic modulus with temperature for SAC305 and CRA solder alloys. Changes in the dielectric elastic modulus are modeled using an empirical relationship previously developed for mold compound of QFN packages shown in equation 1 [14]. Figure 4 illustrates the change in storage modulus for three common dielectric materials used in MCPCBs [15].

Figure 3. Change in storage modulus with temperature for three common dielectric materials used in MCPCBs [32]. The glass transition temperature of these materials ranges from 85ºC to 130ºC and modulus ranges from 12 to 18 GPa prior to the Tg. These dielectric materials are classified as high temperature (HT), Multi-purpose (MP) and circuit material laminate (CML). Some Polyimide based dielectric materials could poses storage modulus as low as 4 GPa while other ceramic-polymer blends could be larger than 20 GPa in some MCPCBs. Coefficients in equation 1 were determined by curve fitting modulus data from Dynamic Mechanical Analysis (DMA) results for the dielectric materials shown in Figure 4.

−+=∆

STT

baETE gmolddielectric

maxtanh)( (1)

Where S is a shape parameter corresponding to the length of the transition region, Tg is the glass transition temperature of the dielectric, Tmax is the maximum temperature of the thermal profile, Emold is the measured modulus of the dielectric prior to the glass transition temperature and a & b are empirical regression constants shown in Table 1 for each of the dielectric materials. Equation 1 is used to determine the elastic modulus of the dielectric material with respect to the maximum temperature experienced during a thermal cycle. This value in necessary to determine the change in interfacial stiffness of the dielectric layer as temperatures increases to be able to determine the corresponding stress relaxation. Table 1. Constants used in equation 1 for three dielectric materials

HT MP CML a 0.5 0.425 0.425 b 1.2 1.4 1.5

S (°C) 55 25 35 Tg (°C) 140 85 85

Figure 4 illustrates a conventional LED package geometry with ceramic sub-mount. The LED consists of an anode and cathode solder pads along with a large central thermal pad. The area fraction of solder with respect to the substrate size varies between LEDs and can influence the elastic compliance of the package during thermal expansion. The LED geometry and material properties shown in Figure 4 are used as a case study in this paper to demonstrate progression in model predictions with variation of MCPCB properties and solder alloys. The solder pad areas in various LED substrates controls the area in which crack propagation occurs Larger solder pads will provide longer fatigue crack propagation path than shorter solder pads.

Figure 4. Dimensions of LEDs used in test vehicle. Digital Image Correlation (DIC) technique was used to measure the CTE of two typical LED ceramic substrates (Table 2) in order to provide a more accurate material property input. The two ceramic sub-mounts measured consisted of an aluminum nitride and silicon nitride materials shown in Table 2.

Table 2. Measured LED ceramic substrate properties.

Material E (GPa) α

(ppm/°C) ν

Aluminum Nitride 330 4.9 0.27 Silicon Nitride Si3N4 166 2.7 0.25

MODEL DEVELOPMENT Several analytical approaches can be used in order to calculate the shear stress and strain solder joints experience. These methods can be referred to as continuous attach or equivalent stiffness models. The continuous attach models treat the substrate, solder and electronic package as a tri-layer structures during thermal expansion. In their formulation, the shear stress can be calculation as a function of distance along the material interface while the equivalent stiffness models provide a single stress value for the entire solder joint interface based on global geometric parameters. The most popular methods used to calculate the mechanical behavior of electronic packaging during thermal expansion have been proposed by Chen and Nelson [16] and Suhir [17]. Chen and Nelson used force equilibrium equations to predict thermal stresses in bonded joints while Suhir utilized Timoshenko’s bi-metallic thermostat approach based on beam bending theory. Both of these methods calculate the interfacial stresses between disjoint materials during thermal expansion. Similarly, their models provide a solution for shear and normal stresses that arise from bending at the free edge of multi-layer electronic assembly during thermal expansion. For simplicity, only the shear stress component will be included in this analysis.

Figure 5. Predictive model procedure Temperature dependence of the elastic modulus (E) CTE during thermal expansion of the LED on MCPCB assembly influences the shear stress and strain values. As thermal expansion increases, strain range increases concurrently with the decrease in stress attributed to reduction of elastic modulus. This behavior is inherent to both SnPb and Pb-free

solder alloys. Implementing this temperature dependent solder behavior is critical for accurately capturing the correct stress state at the appropriate thermal cycle. The model introduced in this paper follows a logic structure which depends on the Tg of the dielectric material. Figure 5 shows the model flow chart and corresponding to the necessary steps required in order to obtain accurate fatigue life predictions using inputs of package geometry, material properties and thermal cycle conditions. The effective interfacial stiffness of LED and MCPCB is constructed from five general components shown in Figure 6. Each component in the effective stiffness equation is contributing to the shear stress acting on solder interconnects of the LED assembly [18]. In order to represent the interfacial stiffness of the dielectric, Biot’s formulation of the stiffness of beam on elastic foundation can be used. This method is similar to beam supported by a series of spring. The methodology addresses the reaction of the foundation as being proportional to the local deflection of beam due to linear elastic foundation stiffness.

Figure 6. LED structure on elastic foundation represented by series of elastic springs. The equivalent stiffness of the LED structure shown in Figure 6 is represented by equation 2. The effective stiffness is used in solving force-displacement compatibility relationship to determine the force acting on solder interconnects due to thermal expansion mismatch.

pfJCKKKKK

K

pab

eff 111111

++++=

(2)

Equations 3 through 6 represent the foundation stiffness for sub-mount ceramic substrate, solder joint, metal core substrate and dielectric layer, respectively.

length

submountthickwidthC C

ECCK = (3)

solder

padtpadsolderJ h

ECGK = (4)

length

widthsubstratesubstratepa C

CtEK 2= (5)

Where C represents dimensions taken from the components. The stiffness is weighted by the physical dimensions attributed to each material in the assembly. Since sub-mount LEDs are constructed with either two or three solder pads, the elastic modulus of solder is area weighted by the area of solder encompassed by anode, cathode and thermal pads. There are several methods to represent the stiffness of the elastic foundation. One method utilizes the approach of rigid surface foundation on homogeneous elastic half-space. Equation 6 represents stiffness derived from single degree of freedom mass-spring-dashpot system [19].

sb

GRKυ−

=2

81, (6)

Where 𝑅𝑅 = �𝑊𝑊𝑊𝑊𝜋𝜋

is the radius of the circular rigid loading

area, G and 𝜐𝜐𝑠𝑠 are the shear modulus and Poisson ratio of the homogeneous half-space, respectively. The second approach to the stiffness of the elastic dielectric layer is provided by the beam on elastic foundation. Biot’s formulation for beam stiffness on elastic foundation is represented in equation 7. This approach assumes that the beam is resting on continuously distributed set of springs with stiffness defined by the elastic modulus [20].

108.0

2

4

22,)1(

)(

)1(

95.0

−−=

EIBTEEK

s

s

s

sb υυ

(7)

Where sE the temperature dependent elastic modulus of the

dielectric, sυ is the Poisson ratio of the dielectric, B is the

copper pad width, E is the elastic modulus of the copper pad and I is the second moment of inertia of the copper pad. Stiffness parameter for plate on elastic half-space is describes by equation 8. This representation of the relative stiffness parameter defined by Gorbunov-Posadov and Serebrjanyi provides a measure of the foundation flexibility [21]. Where

03, =bK represents perfectly rigid plate and ∞=3,bK

represents theoretically a perfectly flexible plate. 22

2

2

3, )1(

)()1(12

−−

=ppps

spb t

bta

ETE

Kυυπ

(8)

Where a and b are the width and length of the copper layer. Figure 7 illustrated the change in three stiffness parameters with temperature. It is important to note that the thickness of the dielectric layer is not incorporated in any of the stiffness parameters.

Figure 7. Dielectric interfacial stiffness with temperature for Tg of 80°C. Figure 7 illustrates stiffness for the LED geometry shown in Figure 4 with dielectric modulus of 12 GPa and Tg of 80°C. Stiffness parameter in equations 7 and 8 correlate better with respect to each other after the glass transition region. The shear stress is then calculated by the reduced force-displacement compatibility form of equation 9 using the effective stiffness.

pad

effsubs A

KTL )( ∆∆=

ατ (9)

Where Lsub is the half diagonal length of the ceramic sub-mount. The half diagonal length incorporates the distance to neutral effect during CTE mismatch. Shear strain is then calculated from the global CTE mismatch driven by metal substrate and ceramic submount given by equation 10.

solder

LEDs h

TL∆∆=

αγ (10)

Modified Norris-Landzberg equation is used to correlate the plastic strain to the creep strain experienced under test conditions [22]. The relationship shown in equation 11 utilizes an acceleration factor approach to correlate the amount of creep strain experienced at a particular temperature and dwell time based on solder properties.

=

−−

TMaxfMax

a

TTkEn

test

dwellMax

DwellMax e

TT ,,

11

γγ (11)

The activation energy of creep in SAC305 is lower than for creep resistant alloys. This information enables the Arrhenius component to adjust the effective creep strain experienced by each solder at a respective temperature and dwell time. Using the strain range computed by equation 11 and shear stress from equation 9, the strain energy is calculated using equation 12 assuming the hysteresis loop is roughly equilateral [23].

ssW γτ2

1= (12)

A deterministic component in a fatigue model is introduced using a 2-parameter Weibull distribution shown in equation 13. These parameters enables the representation of the

predicted cycles to failure in the form of a characteristic life of a 63.2 percent failure probability.

( )β1

1 )5.0(

2.6301.01(%)2.63( 2

−= −

LNxLNWCN C

Maxf (13)

The two-parameter Weibull distribution have been shown to fit solder joints fatigue data particularly well in mildly accelerated test conditions [24]. Where β is the shape parameter of the Weibull distribution. The relationship between cycles to failure and strain energy density is based on work performed by Sayed [25]. A power law relationship exists between creep strain energy and cycles to failure. Strain energy damage coefficient for SAC305 were taken from previous investigations [26]. These coefficients can vary depending on the approach used to determine them. In this model C1 was found to be in the range of 0.0009 to 1.05 with C2 to be in the range of 1 and 1.05 for both solder alloys. The creep activation energy can be determined by plotting creep rate vs. 1/T. From review of experimental testing the Ea/k ratio was found to be in the ranges of 2185 and 6250. The exponent n was determined to vary from 0.136 to 0.36 [27-28]. MODEL PREDICTIONS The model incorporates the influence of geometric parameters and material properties such as solder pad area and substrate CTE on fatigue life of solder joint in the LED package. Decreasing the substrate CTE contributes to the decrease in fatigue life by increasing the global CTE mismatch which results in larger shear strain; however, increasing the solder pad dimension will increase the effective area of fatigue crack propagation and therefore increase fatigue life. As a result, the model can be used for a parametric analysis in order to optimize the pad dimension based on a given substrate material and size in order to achieve optimal fatigue life under the intended operating conditions. Figure 8 shows the predicted shear stress, strain and creep energy for the LED configuration described above.

Figure 8. Shear stress, strain and creep energy with temperature for dielectric Tg=100°C. The model prediction is performed for variation of thermal profiles while maintaining the dielectric Tg. Since the shear stress calculations depend on change in dielectric modulus across the glass transition temperature, a reduction in the peak stress occurs across the transition. The shear strain

values are driven by the global CTE mismatch between the ceramic submount and aluminum substrate. Figure 9 displays predictions of characteristic life for the two interfacial stiffness parameters described in the previous section as function of temperature. In this example, a dielectric layer with Tg of 80°C, CTE of 80 ppm/°c and modulus of 16 GPa was used for the LED geometry described in the experimental section of this paper. Model prediction using stiffness of plate on elastic half-space matches that of the Gorbunov-Posadov stiffness parameter and results in equivalent fatigue life predictions between the two stiffness parameters. Both parameters indicate dependence on the dielectric layer temperature dependent modulus and are found to be the same order of magnitude. The Gorbunov-Posadov stiffness shows provides a relationship that depends less on empirical constants between material properties and contributes to more conservative fatigue life prediction.

Figure 9. Variation in predicted fatigue life for the two dielectric stiffness parameters Figure 10 illustrates the influence of the dielectric material Tg on fatigue life prediction. Two temperature profiles of 20 to 85°C and -20 to 100°C are used to demonstrate the dependence of temperature profile on Tg. The model indicates similar trends on the influence of the Tg on fatigue life in both thermal profiles. Higher values of fatigue life are predicted in the region in which the Tg falls within the thermal profile. Below a ratio Tmax/Tg of 1 fatigue life is lowest since the Tg is outside the temperature range and does not contribute to the necessary stress relaxation which increases fatigue life. In both temperature profiles, an equivalent order of magnitude

Figure 10. Influence of dielectric Tg on fatigue life predictions for two thermal profiles. of 2.7X in fatigue life increase is observed at both temperature profiles with high temperature extreme above the dielectric material Tg. Previous investigation into the effect of dielectric material elastic modulus on the fatigue life of LED on MCPCB was achieved [4]. In their investigation, two dielectrics with high and low elastic modulus subjected to thermal cycling of -40 to 125°C with 30-minute dwell time. After 1000 thermal cycles, 55 percent of population of the stiffer dielectric has failed compared to only 5 percent of the softer dielectric. This indicates that the characteristic fatigue life of the LEDs tested largely depends on the mechanical properties of the dielectric layer. Figure 11 illustrates the influence of dielectric modulus ranging from 4 to 22 GPa on fatigue life predictions. Dielectric with Tg within the temperature profile show incremental improvement in fatigue life of 24 percent and dielectric with 4 GPa indicates a more mild improvement of 13 percent. At more sever thermal profiles, the reduction in predicted fatigue life increases from a factor of 3.1X to 3.6X. This increase could be influenced by a combination in increase solder creep strain and location of Tg within the thermal profile more so than purely on the elastic modulus of the dielectric.

Figure 11. Fatigue life prediction for two thermal profiles across a range of dielectric elastic modulus. The model predictions and variation across the dielectric Tg and modulus do agree with the reported trends in experimental observations. With large change in dielectric elastic modulus, order of magnitude difference in fatigue life can be expected. Figure 12 illustrates the influence of the solder alloy creep parameters on fatigue prediction at different thermal cycles. The peak temperature of the cycle and dwell time have greatest impact on the predicted fatigue life. The influence from increased dwell time for solder alloys is introduced in equation 11. This behavior is shown to have larger difference between the solder alloys at lower maximum temperature (100°C vs 125°C). Higher creep resistant CRA characteristic life is 4-5X that of SAC305 at 100C dwell temperature and 2.5-3X at 125°C. For lower temperature extremes, predicted fatigue life increases for shorter dwell times due to partial creep accumulation. The

short dwell times can cause deviation from the proportionality of creep damage per cycle to the square of temperature range [29].

Figure 12. Effect of dwell time on fatigue life for SAC & Alpha Maxrel™ CRA solder alloys at two thermal profiles. To illustrate the increased thermal fatigue performance of the CRA over conventional SAC alloys, shear strength tests was performed on sub-mount ceramic LEDs which were assembled on an aluminum MCPCB with three different solder alloys. Figure 13 depicts the change in shear strength over a span of 1000 thermal cycles. The increased strength of CRA prior to thermal cycling indicates higher yield stress (probably due to higher elastic modulus). The more stable behavior of the CRA alloy with thermal cycles can be correlated to the improved creep resistance of the material.

Figure 13. Component shear data for ceramic based LED on MCPCB using Maxrel™ creep resistant alloy, over 1,000 [-40°C / + 125°C] thermal cycles [30]. Solder alloy strength decreases with temperature and aging time reducing the necessary creep activation energy. This is indeed the case. The creep deformation for the CRA as compared to SAC305 as measured at Alpha is shown in Figure 14. CRA creep strength at 150°C (measured in number of hours to rupture) is 2X that of SAC305, while the creep elongation is ~3X.

Figure 14. Creep Strength (Rupture Time) and Elongation for SAC305 vs CRA (Alpha Maxrel™) With the development of higher creep resistant solder alloys a benefit for high power LED interconnect reliability can be achieved. By incorporating the previously characterized CRA properties necessary for performing fatigue life predictions, the benefits of utilizing these alloy in LED on MCPCB application can be observed. Figure 15 illustrates model predictions with temperature for the three different dielectric materials shown in Figure 3 along with SAC305 and CRA solder alloys.

Figure 15. Variation in fatigue life prediction with maximum temperature for three different dielectrics and two solder alloys. A clear trend is observed between the different dielectric materials. Higher modulus dielectric is shown to have lower fatigue life for both solder alloys. The inherent improvement in fatigue life between the solder alloys is more evident at lower operating temperatures in which the higher creep resistance of CRA will result in significantly higher fatigue life. Even at high temperature extremes of 130°C. The model account for 2-3X improvement in fatigue life between equivalent dielectric material properties. This increase in fatigue life between SAC305 and CRA was independently verified and was found to agree with model predictions. To validate fatigue life predictions at low temperature extremes, much longer thermal cycling experiments would be needed. The analytical fatigue life prediction model developed for LEDs on MCPCB demonstrates the possibility of performing

accurate fatigue life predictions using fundamental understanding of linear elastic material behavior. In addition, incorporating simple understanding of solder alloy creep behavior for the appropriate creep damage mechanisms which dominates during LED lifetime assists in quantifying the improvement in fatigue life creep resistant solder alloys provide. The model does not aim to replace finite element simulation in addressing reliability predictions. A much more detailed representation of the geometry and solder material behavior can be achieved using numerical tools in order to address specific failure modes and mechanisms affecting LED package reliability. The model presented here addresses the need for a quick parametric understanding of the key factors influencing solder fatigue in sub-mount LED packages on MCPCBs. The model provides a first order prediction for engineering analysis of LEDs soldered to MCPCBs. This approach provides a complementary assessment and understanding to the factors which influence fatigue life of solder interconnects in LEDs on MCPCBs CONCLUSION This paper presented the development of an analytical solder fatigue model for LED packages on MCPCBs. Interfacial stiffness is calculated for LED on MCPCB stack up in order to determine the shear stresses influencing solder joint fatigue. Creep strain energy is determined from the temperature dependent package and solder properties. Model was shown to follow failure trends found in literature. Increase in fatigue life is found for MCPCBs with low modulus dielectric and Tg that falls within the thermal cycle and provides sufficient stress relaxation which reduces the effective shear strain interconnects experience. The model correlates with the fatigue life improvements Creep Resistant Alloy (Alpha Maxrel™) provides in power LEDs on MCPCB under thermal cycling. ACKNOWLEDGEMENT The authors acknowledge the support from Cookson India Research Center’s Pritha Choudhary and Morgana Ribas for the Creep Resistance data on CRA Maxrel™ and SAC305 alloys. REFERENCES

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CHARACTERIZATION AND OPTIMIZATION OF BOARD WARPAGE FOR

LINEAR LED LIGHTING ASSEMBLIES

Amit Patel, Karen Tellefsen, Sarjil Mansuri, and Ranjit Pandher Alpha Assembly Solutions

South Plainfield, NJ, USA

[email protected]

ABSTRACT Board warpage in fiber-glass epoxy laminate boards known

as “FR” boards, is familiar phenomenon seen in traditional

electronics manufacturing. The growth of the LED general

lighting market has propelled the usage of high-aspect ratio

boards where the length is significantly greater than the width

FR type boards for a variety of applications. A significant

percentage of these boards are adopted for linear lighting

applications where warpage of the PCBs is most commonly

seen.

Warpage, also known as bow is defined as the deviation from

flatness of a board characterized by a roughly cylindrical or

spherical curvature1.Board warpage leads to stress and

defects in the material stack such as weakening/cracking of

solder joints, cracking of solder mask, component

misalignment and in some cases, such warpage inhibits

subsequent processing stages of the assembly.

This paper presents a structured study to characterize the

effect of warpage “bow” driven by different assembly

process conditions on FR circuit boards with two dissimilar

glass-transition properties designed as high aspect ratio linear

lighting strips.

Keywords: LED, Linear Lighting, Tube Lights, Solder, Bow,

Warpage, Flex.

INTRODUCTION

Linear “tube” lights are one of the most adopted design forms

for illumination. Historically, these tube lights have used

florescent technology. The applications for linear lighting

range across numerous applications from retail, industrial,

commercial, and residential lighting. Today, with the realized

benefits of Light Emitting Diodes (LEDs), these designs are

being converted to this solid state technology.

LED-based linear lighting lamps may look similar to their

traditional counterparts on the outside, but differ vastly upon

closer inspection:

(I) Materials Stack: Aside from the difference in light

sources, the overall material stack varies. Figure 1 depicts a

typical completed stack of a linear light strip with a mid-

power LED on an FR based printed circuit board (PCB).

Despite many types of PCBs in use, from thick Metal Core

PCBs, to thin polymer based flexible substrates, the most

1 (Khandpur, 2005)

widely adopted PCBs for linear lighting is FR. An FR based

board provides many advantages for the LED lighting

industry, primarily, ease of sourcing, flame-resistance,

retention of high mechanical and electrical insulation and

lastly, and a diverse choice of fabrication designs and

material cost advantages.

Figure 1. Cross section of a commercial mid-power LED on

FR PCB2.

(II) The Process: One of the major differences between

fluorescent and LED technology is how the assembly process

takes place. LED based lighting systems require a heavier

usage of SMT / Wave soldering processes. In the case of

linear light systems the construction uses a panelized design

to process multiple strips simultaneously. It is ultimately this

very process of thermal excursion combined with the material

selection that causes warping/bow.

Today, there are several key ways to reduce or eliminate

warpage, each having their own advantages and

disadvantages: (I) Optimization of assembly process

conditions, (II) Mechanically adhering PCBs i.e. with

fasteners and or clips and lastly, (III) Modification of material

selection and/or design.

2 Alpha® Cross Sectional Analysis

For this evaluation, the motivation to evaluate the effects of

item (I): the assembly process and its effect on warpage is

crucial as this is conventionally, the first article that is

examined in the occurrence of warpage. Table 1 summarizes

our approach to characterize different types of FR properties

under variable process conditions of a soak and straight ramp

profiles.

Factors Factor Levels

FR PCB Property FR – 180 Glass Transition

FR – 130 Glass Transition

Processing Temperature

Condition

Profile – High (245°C Peak)

Profile – Low (180°C Peak)

Profile Straight

Soak

Table 1. 2 Factorial Level Design of Experiment

ASSEMBLY MATERIALS & COMPONENTS

Test Vehicle

The test vehicles used for this evaluation are designed in-

house at Alpha®. The design considerations are based on

general market observations. Furthermore, the boards are

functional which allows for operational testing. Table 2

summarizes dimensions and general attributes of the test

vehicle.

Parameters Board 1 Board 2

Dimensions 460mm x 65mm 460mm x 65mm

Thickness 0.75mm 0.75mm

FR-Grade FR4 FR4

Filler Filler No Filler

Laminate (Tg)3 180 130

Copper Layer 35µm Thick 35µm Thick

Surface Finish OSP OSP

Table 2. Test Vehicle Summary

LED Component

For this study a mid-power package was selected due to its

common utlization in indoor linear lighting applications. It

consists of a 3535 lead-frame design (3.5mm x 3.5mm). A

small notch on the corner of the package marks the cathode

side of the emitter package. The anode and cathode both

serve as thermal pads for the emitter, with the majority of the

heat being conducted through the larger pad, corresponding

to the cathode as seen in Figure 2.

3 Glass Transition Temperature

Figure 2. LED Package Rendering Including Solder

Footprint3

Solders

The processing temperature conditions and its effect on

different Tg laminates are largely dictated by alloy selection.

A standard SAC305 alloy with a melting point range of 217-

221°C and a novel low-temperature Sn-Bi based alloy

(SBX02) with a melting point of 138.5°C are used.

PROCESS AND TEST METHOD

Equipment Processing Details

Table 3 summarizes the SMT equipment used for assembling

mid-power LED packages on the test vehciles.

SMT Equipment Equipment Details

Stencil Printer DEK Horizon 03iX

Pick and Place Fuji NXT II

Placement Nozzle Flex Jet nozzle

Reflow Oven Electrovert OmniFlo 7 Zone

Table 3. Equipment Process Details

Reflow Soldering A reflow oven with seven heating and two cooling zones was

used for the reflow assembly. All boards were assembled in

an air atmosphere with the following Temperature/Humidity

conditions: 20.4-25.2°C / 16-47% RH. Table 4 summarizes

both reflow profiles under low and high temperature

conditions.

Alloy Profile Condition

SAC305 Soak 150-200_83s 245°C Peak 63-66s

SAC305 Straight 150-200_60s 244°C Peak 62-65s

SBX02 Soak 150-180_30s_180°C Peak_76s

SBX02 Straight 150-180_27s_179°C Peak_76-80s

Table 4. Reflow Process Conditions

Test Method

A variety of test methods and procedures exist to measure the

deviation from flatness. This evaluation uses the IPC 650TM

2.4.22 methodology, Figure 3 describes the procedure of

measuring the subject. The linear lighting test vehicles are

laid on a flat surface with all four corners making contact,

using a filler gauge, the highest point from the surface is

measured which is approximately at the center. The same

procedure is repeated for each board that has undergone

reflow. The values are recorded as a difference between pre-

assembly and post reflow assembly.

Figure 3. IPC 650TM 2.4.22 Measurement Technique

RESULTS AND CONCLUSIONS

Results

The interaction between the factors and their effect on

warpage can be seen in Figure 4 below. Processing under

lower peak temperature of 180°C driven by the use of the

SBX02 alloy produces the lowest levels of warpage.

Secondly, the type of profile used - Straight vs. Soak has

minimal effect on this particular assembly. Lastly, the

laminate system with glass transition temperature (Tg) of

130°C generated lower levels of warpage.

Figure 4. Main Effects Plot-Effect of Variables on Warpage

Overall, with the exclusion of the Tg property, the use of low

temperature SBX02 alloy produces a 38% reduction in warp

as seen in Figure 5.

Figure 5. Warpage versus Processing Temperature as a

Function of Alloy Selection.

It is evident that low temperature processing using SBX02

alloy produces lower levels of warpage when compared to

standard SAC assembly. Now, the effect of processing

temperatures with laminates of different Tg properties are

investigated in Figure 6.

Figure 6. Boxplot of Warping as a Result of Tg Property

versus Alloy.

Interestingly, we observe that linear boards built with

laminates using the 130°C Tg property produces lower levels

of warpage when compared to 180°C Tg. We hypothesize that

the influence of CTE interaction plays a more significant role.

The combination of low temperature SBX02 alloy and 130C

Tg produces the lowest level of warpage.

Conclusions and Summary

Board warpage leads to stress and defects in the material

stack such as weakening/cracking of solder joints, cracking

of solder mask, and component misalignment. In some cases,

it can inhibit subsequent processing stages of the assembly.

It is clear that using lower processing temperatures can

reduce warpage by 38% as shown in this evaluation. This is

ultimately driven by the selection of low versus high melting

point alloys. End-use environment and application needs to

be carefully considered when attempting to covert to different

alloys. In the case of indoor linear lighting using mid power

LEDs on FR boards: it is feasible to use Sn-Bi based alloys

such as SBX02 alloy.

SAC305SBX02

20

15

10

5

0

Warp

(m

m)

5.35

14.1325

Boxplot of Average Warping (Delta)Alloy

TG_180-SBX02TG_130-SBX02TG_180-SAC305TG_130-SAC305

20

15

10

5

0

Warp

(m

m)

10.5

17.765

4

6.7

Boxplot of Average Warping (Delta)Alloy vs Tg

MATERIALS ENABLING FLIP-CHIP

LED & FLEXIBLE FORM FACTORS

FLIP CHIP LED ASSEMBLY BY SOLDER STAMPING / PIN-TRANSFER

Gyan Dutt, Srinath Himanshu, Nicholas Herrick, Amit Patel & Ranjit Pandher

Alpha Assembly Solutions

South Plainfield, New Jersey, USA

[email protected]

ABSTRACT

Flip-Chip and Chip Scale Package (CSP) Light Emitting Diodes (LEDs) are being increasingly adopted for applications in TV backlight and mobile flash. Lately they are also being used for automotive interior, street lighting and even and general lighting applications. The advantages of very small form factor, easier optics, improved thermal dissipation and no wire-bond result in unrivaled high lumen density at lower cost.

Eutectic gold tin (AuSn 80/20) is the die attach material of choice for flip-chip LEDS. Lately, there has been a significant effort to make these devices compatible with SMT. However, SMT assembly of these small packages is challenging. Package float and tilt can result in sub-par assembly yields. Flip-chip LEDs are tricky because of their rectangular interconnect pads with small gaps (which are getting even smaller). Finally, performance issues like luminous flux degradation due to flux residue and current leakage during reverse bias remain.

In this study, pin transfer (also called stamping) process was adapted to assemble flip-chip CSP LEDs with fine pitch solder paste. Solder reservoir height and die attach conditions were varied to optimize solder spread, voiding and die shear for commercial flip-chip CSPs. Also preliminary results on the effect of cleaning of LEDs (after assembly) on light output and color are also presented.

This study is relevant for LED packaging and LED module assembly makers who use flip chip for automotive, backlight and general lighting applications.

Keywords: LED, Die Packaging, Die Attach, Flip chip, Solder, SMT, Pin Transfer, Cleaning

LED CHIP STRUCTURES

There are three main LED chip structures (Figure 1). The Lateral structure consists of laterally spaced electrodes (with one wire-bond for each electrode) and is used in low power applications. The Vertical structure, used for most of the high and super-high power applications, consists of a conductive substrate at the bottom which forms the bottom electrode with the current flowing vertically. The Flip-Chip structure has both electrodes on one side and is put face down on the substrate. It provides the highest lumen density at cost lower than vertical structure. These three structures can also be mounted directly on a board, next to each other, to form Chip-on-Board (CoB) modules.

Figure 1: Common LED structures

FLIP CHIP and CHIP SCALE PACKAGE LED

The high lumen density (and low lumen/$) advantage of the Flip-Chip LED structure (as mentioned above) essentially stems from replacement of the wire-bonds by relatively large area contacts that serve as both electrical

LATERAL

VERTICAL

FLIP-CHIP

INCREASING POWER

CHIP-on-BOARD

and thermal pads. The improvement in heat dissipation allows the chip to be driven at high currents without the need for expensive highly conductive substrate (like CuW) – which, along with reduced defects from absence of the wire-bonds, extends the lifetime. The small form factor (and flat wire-bond free surface) also makes optical design much easier – thereby reducing the cost even further.

Lately there has been a concerted effort by most LED makers to use the flip-chip structure to make a chip-scale package (CSP) with the foot print very close to the flip-chip pads compatible with solder (and SMT reflow process) – especially for COB applications. The idea is to put the solder compatible pads (and sometimes even interconnects) at the wafer-level. The chips can then be picked and placed by either a high precision die bonder (with solder printed or stamped on substrate pads), or preferably, by a regular pick-place machine (also sometimes called a chip shooter) on the SMT line.

The SMT option is very attractive for several reasons. While it adds one step at the back-end (solder pads), it skips the traditional packaging (die attach on a sub-mount substrate and wire-bonding) step completely. As a result the module makers can buy the CSPs and assemble them directly on SMT lines (cheaper equipment with higher throughput).

EXPERIMENTAL

In this study, pin transfer process was adapted to assemble commercially available flip-chip LEDs with solder.

Pin transfer (also called stamping) consists of using a pin (or a set of pins configured to match the foot print of the die) to stamp the solder off a reservoir on to the substrate. The die is then aligned and placed on the substrate (with the solder stamp) and then reflowed. Pin transfer is a very popular for both lateral (mesa) and vertical LED die attach since it is a very high throughput process (up to 9-10K units per hour), and is SMT compatible. The thin bond line (5-20um typical) ensures lower thermal resistance compared to conventional printing.

ASM pin transfer die bonder ASMD838L was used for the pin transfer with Alpha’s Lumet P23 no-clean solder paste (with 5-15um fine Type 6 SAC305 alloy). Commercially available UV flip-chip dies (from Lumileds) were assembled on custom designed silver finish lead frames. Heller 7-stage reflow oven was used to reflow the assemblies. The flip-chip die pads, and the

substrate pad are shown in Figure 2, while the reflow profile used is shown in Figures 3.

(a)

(b)

Figure 2. (a) Flip-chip die pad and (b) Substrate pad

Figure 3. Reflow profile used

First the pin transfer stability of Lumet P23 solder paste was studied over typical 8-hour work shift with 1x1mm dummy silicon dies (Cr/Ni/Au finish) on FR4 substrate. Paste volume transfer (which translates into bond line thickness control), die shear and die shear failure mode were recorded over 8-hours.

Next the flip-chip dies were assembled on the substrate. Pin transfer reservoir height was varied and fillet size, voiding and die shear were recorded.

The assembled parts were cleaned in an in-line and ultrasonic batch cleaning stations at 60C by Zestron Inc. with different cleaning chemistries. The cleaned and un-cleaned parts were characterized for radiant flux before and after aging (at 150C for 1000 hours). Preliminary, pre-aging results are discussed in this paper.

RESULTS

The pin transfer volume stability for Lumet P23 is shown in Figure 5. As can be the seen the variation in the volume over 8 hours is maximum 15% (difference between maximum and minimum volumes deposited at 1 hour intervals over 8 hours). This translates into ~2 micron variation in bond-line-thickness (BLT) over 8 hours – which meets the spec for almost all applications (see Figure 6 for the measured BLT variation).

Figure 5 Lumet P23 transfer weight variation over time during 8-hour pin transfer over 8-hours

Figure 6 Bond Line Thickness variation over 8 hours

The reservoir thickness optimization results are discussed next. The bond force had to be kept at the lower end of the bonder range (30-50 grams) to prevent excess squeeze out while the bonding time was kept as

low as possible to ensure high throughput. Hence the reservoir thickness optimization becomes a key to ensure that there is no bridging between the p & n pads while at the same time there is enough solder volume for adequate die shear strength for reliability. Flip-chip LEDs active light emitting areas are close to the bottom of the die and it is important to ensure that the interconnect material (solder in this case) does not block the light from these active regions.

Figures 7 shows the transferred solder paste, squeeze out after die placement and x-ray of the die-substrate assemblies at different reservoir heights before solder reflow. The assemblies after reflow are shown in Figure 8. It is important to note that at all reservoir heights, the solder squeeze out in-between the die pads was contained and there was absolutely no bridging (as clearly seen in x-ray shots)

At the lowest reservoir height (200um), the volume of solder transferred was inadequate to cover the entire pad area and did not coalesce to form a uniform interconnect layer between the die and the substrate. The distinct circular deposits of wet solder at can be seen both before and after the reflow. For 300um height setting, the paste did coalesce, however, the spread around the pad was non-uniform.

On the other end, higher reservoir heights (600-700um), resulted in excessive volume transfer that excessive spread around the pad and may block the light emitting regions (or block the reflective pad on the substrate thereby indirectly reducing the light extracted).

0.25

0.45

0.65

0.85

1.05

0 hr 2 hr 4 hr 6 hr 8 hr

Wei

ght o

f Pin

Tra

nsfe

r in

mg

Time

Lumet P23 Pin transfer over Time

5

10

15

20

0 2 4 6 8 10

BLT

[um

]

Time [Hours]

BLT Variation during Pin Transfer

Figure 7 Pin transferred Lumet P23 paste and squeeze out after die placement (wet) before reflow

Figure 8 Lumet P23 solder coalescence and fillet at different reservoir heights

The volume of transferred Lumet P23 solder paste also results in different levels of die shear and voiding. Excessive solder (from a thick reservoir height), although not desirable for active light emission, does help reduce the voiding and increase the die shear strength. The low volume transfer (off the lower reservoir heights, especially 200-300um) resulted in higher voiding and lowest die shear.

Table 1 summarizes the process outputs like die shear, voiding, fillet, coalescence, mid-chip solder balling etc. as a function of reservoir height.

Table 1. Process outputs variation with paste reservoir height.

Figure 9. Die shear variation as a function of Reservoir Height

It is important to note that the intermediate reservoir height settings (at 400-500um) gave the optimal balance between coverage (which impacts die shear and voiding), coalescence and fillet spread.

The effect of cleaning of the assemblies on radiant flux is shown in Figure 10. The measurements clearly indicate that radiant flux output is significantly higher for the cleaned assemblies irrespective of the chemistries used. The radiant flux for the best-cleaned assemblies is of the order of 15% higher than the un-cleaned ones.

Figure 10. Effect of cleaning (and different chemistries) on radiant flux output

It would be interesting to track the change in radiant flux for these assemblies during the high temperature aging at 150°C. Those results would be presented elsewhere.

SUMMARY / CONCLUSION

Pin transfer / stamping process was successfully adapted for high throughput assembly of flip-chip LEDs with Alpha Lumet P23 solder paste with Type 6 SAC305 alloy). The paste volume was optimized to achieve high die-shear, low voiding and minimal spread-out for highest light extraction. Solder paste stability over 8-hours of the stamping / pin transfer process was also demonstrated.

Preliminary functional performance testing of the assembled UV LEDs suggest that cleaning after assembly can have significant positive impact on the radiant flux output.

ACKNOWLEDMENT

The authors appreciate the help of Ravi Parthasarathy and Christine Anderson of Zestron Inc. (located in Manassas, Virginia, USA) towards cleaning of the flip-chip assemblies with different cleaning chemistries on Zestron cleaning equipment.

ENABLING THE USE OF PET FLEXIBLE SUBSTRATES FOR LED LIGHTING APPLICATIONS

Amit Patel, Rahul Raut, Ranjit Pandher, Ph.D., Ramazan Soydan, Westin Bent and Ravi Bhatkal, Ph.D.

Alpha, an Alent plc Company South Plainfield, NJ, USA

[email protected]

Brent Sweitzer, James Toonen, Bob Hanson Multek

Northfield, MN, USA [email protected]

ABSTRACT This paper presents a structured study covering the assembly of mid power LED packages on thermally conductive polyethylene terephthalate (PET/Polyester) and polyimide flexible substrates. The study evaluates the feasibility of using PET as a low cost, low temperature alternative with SnBi Alloy to traditional polyimide with SAC based alloy assemblies. Initially, an assembly method was developed for both polyimide and PET based substrates. In order to validate the use of PET as an alternative to polyimide substrates , electrical testing, voiding, and thermal cycling tests were conducted. The results of processability and long term reliability of using low temperature solders (SnBi based SBX02 alloy) on PET versus traditional SAC 305 on polyimide are presented in this paper. Keywords: SSL, LED, Low Temperature Assembly, Flexible Circuits, Polyimide and PET Substrates, Sn-Bi, SBX02, Solder Paste. INTRODUCTION LEDs are now becoming more prevalent and are being widely used in a variety of applications such as Automotive Lighting, Commercial and Indoor Lighting. Further system cost reductions to enable wider adoption can be achieved by:

LED package cost reduction through innovative package design and high throughput, high volume manufactuing.

Substrate cost reduction through reductions in material stack / footprint, improvement in process flexibility and process cost reductions.

Polyimide (PI) is the most commonly used flexible substrate in conjunction with SAC-based Solder Pastes (a melting point of around 218°C). Advancements in Polyethylene Terephthalate [commonly known as Polyester (PET)] flexible subtrates, coupled with low temperture assembly of LEDs, can enable further system cost reductions while enabling new design form factors.

This study assessed the feasibility of utilizing PET flexible substrates with low temperature solder paste for Solid State Lighting (SSL). ASSEMBLY MATERIALS & COMPONENTS Materials and components were chosen based on commercially available LED packages, solder pastes and flexible substrates. Mid Power LED package For this study a 3535 package was selected. It consists of a 3535 lead-frame design (3.5mm x 3.5mm). A small notch on the corner of the package marks the cathode side of the emitter package. The anode and cathode both serve as thermal pads for the emitter, with the majority of the heat being conducted through the larger pad, corresponding to the cathode as seen in Figure 2.

Figure 1. Image of Mid Power LED Package (Refer 1)

Figure 2. LED Package Rendering Including Solder Footprint (Refer 1)

Polyimide (PI) and Polyethylene Terephthalate (PET) Substrates Flexible circuits allow for a reduced board material stack over rigid boards and are able to provide designers with a higher design freedom in the SSL industry. The increased demand for flex circuits is most noticeable in applications for indoor linear lighting, cabin lighting for automobiles,

backlights for mobile displays, digital cameras and flat panel displays. There are a number of different materials used as base films for flexible circuits including: polyester (PET), polyimide (PI), polyethylene napthalate (PEN), Polyetherimide (PEI), etc. Each substrate has its unique electrical, mechanical, chemical and thermal properties. For this study the LED packages were assembled on two base materials, Polyimide (PI) and Polyethylene Terephthalate (PET). Both substrates have a similar thickness and construction comprised of a copper-aluminum composite. The test vehicle with both substrates was designed in a 9x7 LED matrix. A total of sixty-three (63) LED packages were assembled in this configuration as shown in Table 1. The image of the test vehicle used is shown in Figure 3. Table 1. Details of the Test Vehicle Substrates

Test Vehicle Details: Polyethylene Terephthalate (PET)

Dimensions: 18”x12” Solder Pad Sites: 63 (9x7)

Polyimide (PI) Dimensions: 18”x12” Solder Pad Sites: 63 (9x7)

Figure 3. Substrate Design

A cross sectional view of the PI substrate is shown in Figure 4.

Figure 4. Cross Sectional View of the Flexible Substrate (Polyimide) (Refer 2) Solder Paste Lead-free Sn-Ag-Cu pastes are typically used in assemblies utilizing polyimide flexible substrates. Solder Pastes using Sn-Ag-Cu alloys have melting ranges between 217°C and 228°C, requiring reflow temperatures in the range of 245°C to 265°C. Although manufacturers who utilize flexible circuits have adapted to these higher reflow temperatures, a set of very strong drivers is pushing forward the use of

lower reflow temperatures in application of LEDs assembled on flexible substrates. The major benefits of using low temperature alloys are: (Refer 3, 4, 5)

Assembly of heat sensitive packages and components.

Long-term reliability, as low temperature solders reduce exposure to thermal excursion, warpage and other defects caused by excessive heat. .

Reduced material costs by using low temperature alloy and solder paste, low Tg PCBs and low temperature compatible components.

Reduced energy costs through lowering temperature processing.

Higher throughputs by reducing reflow / processing cycle time.

In general, assemblies involving LED components are considered to be temperature-sensitive. Heat induced defects such as browning and softening of the silicone lens, and discoloration of the white solder mask typically utilized in LED assembles, affects the light output. Furthermore, in case of flexible circuits/assemblies, higher temperatures can cause delamination and warpage of substrates. Low-temperature solders are preferred for these applications. In this study a novel low-temperature Sn-Bi based alloy (SBX02) solder paste is used allowing the assembly of the LED packages to be reflowed under 175°C, Further, a solder paste with a SAC305 alloy was also used as the baseline. PROCESS AND ASSEMBLY DETAILS Test Matrix Based on the package, substrate and materials selected the process involved three key assembly combinations, Figure 5 shows these combinations. First combination involved using a polyimide substrate with a SAC305 solder paste representing the current industry practice. The second combination involved again, a polyimide substrate in conjunction with a low-temperature SBX02 alloy based solder paste. This combination represents the traditional substrate with the low-temperature solder paste. The final combination used a Polyester (PET) substrate with the low-temperature solder paste (SBX02 alloy).

Figure 5. Three Tier Combination of LED assemblies on Flexible Substrates.

Process Details Table 2 summarizes the SMT equipment that was used for assembling the LED packages onto the substrate combinations. Table 2. SMT Equipment Summary

SMT Equipment Equipment Details Stencil Printer Standard Stencil Printer Pick and Place Standard Pick and Place

Machine Placement Nozzle Flex Jet nozzle Reflow Oven Seven Zone Reflow Oven

Solder Paste Printing Solder paste printing was done using a stencil printer with a 5 mil thick laser cut stainless steel stencil with a 1:1 aperture size to pad size ratio. Stencil printing parameters used for all solder pastes and board combinations are shown in Table 3

Table 3. Print Parameters

SMT Parameters

SMT Process Details (SI Standard)

SMT Process Details (Metric

System) Print Speed 1 inch/sec. 25 mm/s Print Pressure 1.25 lbs/inch 0.22 kg/cm Stencil Release 0.02 inches/sec 0.508 mm/sec Snap off 0 inches (on contact printing) Wipe Frequency

Dry wipe after each print

Component Placement A pick and place machine with flex jet head was used for the picking and placing the LED package. Care was taken to avoid any contact of the nozzle exterior with the LED domed silicone lens. Reflow Soldering A reflow oven, with seven heating and two cooling zones was used for the reflow assembly. All boards were assembled in an air atmosphere with the following Temperature/Humidity conditions: 20.4-25.2C / 16-47% RH. All of the substrates used in the study were pre-baked before going under their respective reflow conditions. The table below and Figure 6 summarizes the reflow conditions for each combination. Table 4. Reflow Parameters

Substrate + Solder Paste

Reflow Conditions

Polyimide + Lumet™ P39 SAC305

High Soak 150-200C/105s 245C Peak 68-75s TAL

Polyimide + Lumet™ P53 SBX02

Low Soak 100-120C/104s 175C Peak 65s TAL

PET + Lumet™ P53 SBX02

Low Soak 100-120C/104s 175C Peak 65s TAL

Figure 6. Reflow Profile of SAC305 vs. SBX02 RESULTS AND DISCUSSIONS After the final assembly, multiple tests were undertaken:

1. Electrical testing of the assembly in the “light on” mode was conducted by measuring the current across each board and paste combination. This verifies proper assembly and functionality of the circuits in the as assembled state.

2. A voiding study was conducted by X-Ray analysis to study the performance of SAC305 and SBX02 on both PET and Polyimide.

3. A cross section analysis was conducted to examine the characteristics of the solder joint in the as assembled state.

4. The study evaluated the reliability of each assembly by exposing the all of the paste and substrate combinations to thermal cycling. “Light on” current measurements and cross sectional analysis were recorded for 250 to 1000 cycles. The thermal cycling conditions used were -40°C to +85°C with a 30 minute dwell time.

Light On Current Measurements and Results A light on current test was conducted to ensure the LED packages both on PET and Polyimide were operational. Using a commercially available power supply with a constant input voltage of 25V, the current across each circuit was recorded as shown in Figure 7. Each substrate was tested visually to ensure the LED lit for a minimum of 3 seconds as seen in Figure 8.

Figure 7. Current Across Substrate & Paste Combination

Figure 8. LED Circuit Under Operation.

The current measured across each circuit produces a low variation from the mean. A significant decrease in current would indicate an increase in resistance. The light output test confirmed that all combinations of the LED circuits passed the reflow processing conditions. Furthermore, the LED circuit shown in Figure 8 lit up confirming there are no failures within the assembled LED package, solder layer or board circuitry. Voids Measurement and Results Voids can reduce the overall rate of heat transfer between the LED package and board. This reduction of heat transfer efficiency can cause the LED to degrade much quicker. This can lead to:

Reduced solder joint integrity which lowers

overall life expectancy / reliability of the LED. Inefficient manufacturing process with

reduced first pass yields. Higher costs due to scrapped materials i.e.

boards, LED packages, and solder. An X-ray machine was used to measure the voids percentages (by area) of the reflowed solder joints. A total of 40 randomly selected solder sites for each solder paste and board combination were evaluated. A typical example of an individual site on PET with SBX02 under X-Ray inspection can be seen below in Figure 9. Void % by pad and total void % were analyzed.

Figure 9. Void % by Total Area Figure 10 shows a box plot for percent voids per total pad area for the 3 combinations of paste and substrate type. It

shows that overall, the percentage of voids are under 10%. PET in conjunction with the use of SBX02 solder paste produces the least amount of voids as seen in Table 5.

Figure 10. Box Plot of Total Area Void %.

Table 5. Void % and Standard Deviation.

Combination Mean

Void % Standard Deviation

PET + Lumet™ P53 SBX02 5.82 1.97

Polyimide + Lumet™ P39 SAC305

7.23 3.64

Polyimide + Lumet™ P53 SBX02

8.46 2.43

The average percentage of voiding in all 3 combinations falls below 10%. The maximum size of a single void including their respective sum of standard deviation for any combination falls below 10.89%. Solder Layer Measurements and Results Cross section analysis of the assembled LEDs is presented below; Examples of PET and polyimide using SBX02 are shown in Figures 11A, B and 12A, B below. Polyimide using SAC305 are shown in Figures 13A, B. Figures 11A, 12A and 13A correspond to a general cross section profile of the assembled LED package, while 11B 12B and 13B shows the edge view (fillet) of the solder joint structure.

TOTAL VOID % POL W/ SACTOTAL VOID % PET W/ SBXTOTAL VOID % POL W/ SBX

20

15

10

5

0

Dat

a

8.46925

5.82175

7.235

Boxplot of TOTAL VOID % POL, TOTAL VOID % PET, TOTAL VOID % POL

Pad

Alpha 15.0kV 11.9mm x39SE

SBX02

Figure 11A. Overall View of an LED Package on PET with SBX02

Figure 12A. Overall View of an LED Package on Polyimide with SBX02

Figure 13A. Overall View of an LED Package on Polyimide with SAC305

Figure 11B. Solder Edge View of LED Package on PET with SBX02

Figure 12B. Solder Edge View of LED Package on Polyimide with SBX02

Figure 13B. Solder Edge View of LED Package on Polyimide with SAC305 The solder joints exhibited excellent fillet. No visual cracking was observed across all 3 combinations. Thermal Cycling Measurement and Results Reliability plays an important role in applications of LED devices, modules and systems. To understand the reliability performance of each combination, assemblies were exposed to thermal cycling. All board and paste combinations were placed in a thermal cycling chamber at -40°C to +85C°C, with 30 minute dwell time. Each assembled combination was evaluated in light on state by recording the current across each circuit (Figure 14).



Pad

Pad

Alpha 15.0kV 11.5mm x217 BSE3D



SBX02

SAC305

SBX02

SBX02

SAC305

Figure 14. Current across each board and paste across 250 to 1000 cycles at [-40°C + 85°C]

Combination Mean Current at 1000 Cycles

PET + SBX02 31.20 mA Polyimide + SAC305 31.40 mA

Polyimide + SBX02 31.00 mA

A total of 5 circuits of each board and paste combination

were analyzed by recording the current at a constant input voltage of 25V for 250 to 1000 cycles. The ANOVA results show that the average current recorded is in statistical range (P value of 0.61) of the current measurement mean calculated in Figure 7(31mA) which is considered to be initial (T0). The results at 1000 cycles conclude there is no significant change in the current across the assembled combinations. SUMMARY

1) PET with Lumet™ P53 solder paste with SBX02 alloy can be used as an alternative to Polyimide with SAC305 based solder pastes, for LED assembly in certain solid state lighting applications.

2) All of the assembled packages passed the ”light on” current test indicating that there are no failures within the solder joint, LED package itself or board circuitry as assembled.

3) The X-Ray inspection showed minimal voiding percentages that meet or exceed typical SSL industry requirements.

4) All of the assembled paste and substrate combinations using mid-power LED packages were able to withstand 1000 cycles at -40°C to +85°C with a 30 minute dwell time.

In conclusion, PET subtrates coupled with low temperture solder enabled LED assembly provide several advantages, such as:

1) Enabling system cost reduction by using a lower cost board and assembly material stack.

2) Enabling lower energy costs through low temperature assembly.

3) Enabling the use of SAC solder based LED die attach.

REFERENCES

[1] Ref 1 - “LUXEON 3535L, Assembly and Handling Information – AB203”

[2] Ref 2 - “Multek Q-Prime® Product Bulletin REV B” [3] Ref 3 - Morgana Ribas, Sujatha Chegudi, Anil Kumar,

Ranjit Pandher, Rahul Raut, Sutapa Mukherjee, Siuli Sarkar, Bawa Singh “Development of Low-Temperature Drop Shock Resistant Solder Alloys for Handheld Devices”

[4] Ref 4 - Ribas Morgana, Chegudi Sujatha, Kumar Anil1, Pandher Ranjit, Mukherjee Sutapa, Sarkar Siuli1,Raut Rahul and Singh Bawa “Low Temperature Alloy Development for Electronics Assembly”

[5] Ref 5 - Morgana Ribas, Ph.D., Sujatha Chegudi, Anil Kumar, Sutapa Mukherjee, Siuli Sarkar, Ph.D. Ranjit Pandher, Ph.D., Rahul Raut, Bawa Singh, PhD, “Low Temperature Alloy Development for Electronics Assembly – Part II SMTAI-2013”

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