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Block Diagram

Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

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Page 1: Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

Block Diagram

Page 2: Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

DREFSSCLK (100 MHz)

DREFSSCLK# (100 MHz)

CLK_ICH14(14.318 MHz)

CLK_MCH_BCLK# (166 MHz)

Volvi2 Clock Block Diagram

CPU

Crestline

CLK_CPU_BCLK (166 MHz)

CLK_CPU_BCLK# (166 MHz)

Crystal14.31818MHz

CPUC0

CPUT0

CPUC1_F

CLKGENICS9LPR502

X1/X2

CPUT1_F

DDR2NORMAL

TYPE

DDR2NORMAL

TYPE

M_C

LK_D

DR

0/#

MINI CARDKEDRON a/b/g/n

CLK_PCIE_MINI1

PCI3

Crystal32.768KHz

KBC WPC8763L

ICH8-M

X1/X2

RTC 32.768kHz

PCI_F5/ITP_EN

USB_48MHz/FSLA

REF0

CODECALC268

MDC

ACZ_BITCLK

AC_BTCLK_MDC

CLK48_ICH(48 MHz)

CLK_ICHPCI(33 MHz)

PCLK_KBC (33 MHz)

SRCT0/DOTT_96 DREFCLK (96 MHz)

FWH

SRCC0/DOTC_96 DREFCLK# (96 MHz)

CLK_PCIE_ICH(100 MHz)CLK_PCIE_ICH#(100 MHz)

SRCT6

SRCC6

Crystal 25MHz

SRCT3SRCC3

CLK_MCH_3GPLL (100 MHz)CLK_MCH_3GPLL# (100 MHz)

BCLK1

BCLK0

HPLL_CLK

HPLL_CLK#

PEG_CLK

PEG_CLK#

DPLL_REF_CLK

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

DPLL_REF_CLK#

CLK14

CLK48

PCICLK

DMI_CLKN

DMI_CLKP

SRCT7

SRCC7

M_C

LK_D

DR

1/#

M_C

LK_D

DR

2/#

M_C

LK_D

DR

3/#

PCI4

SRCC4

SRCT4

CLK_PCIE_MINI1# (100 MHz)

(100 MHz)

PCLK_FWH (33 MHz)

LAN 10/100Marvell 88E8039

CLK_PCIE_LAN

SRCC8

SRCT8

CLK_PCIE_LAN#

(100 MHz)

(100 MHz)

SATA

CLK_PCIE_SATA

SRCC2

SRCT2

CLK_PCIE_SATA# (100 MHz)

(100 MHz)

NEW CARD

CLK_PCIE_NEW

SRCC1

SRCT1

CLK_PCIE_NEW#(100 MHz)

(100 MHz)

CLK_MCH_BCLK (166 MHz)

Page 3: Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

Volvi2 Power ON/RESET Sequence

3D3V_S0 3D3V_S5

5V_S05V_S5

5V_S0

VCC_CORE_S0

RTC_AUX_S5

3D3V_AUX_S5

3D3V_S0

1D25V_S0

PM_SLP_S3#

5V_S0

ICH8-M

G792

Merom

CLK

ICS9LPR502

MAX8770

Crestline

KBCWPC8763L

-2

REGISTER(BTCRL.SBR)

1:RESET

0:RELEASE

RTC

VGATE_PWRGD

SLP_S4# SLP_S3#

PWROK CPUPWRGD

SHDN#RSTIN#

H_CPURST#

RESET#

RTCRST#

CPUCORE_ONPWROK

VRMPWRGD

CK_PWRGD

PWRGD

PWRGOOD

RSMRST#

RSMRST#_KBC

PWRBTN#PCIRST#

PLT_RST1#

3D3V_S5

RSMRST#_

KBC_PWRBTN#PM_PWRBTN#

PM_PWRBTN#

PM_SLP_S3#

TPS51100S5

CPUCORE_ON

RESET#

PWROK

H_P

WR

GD

H_CPURST#

PLTRST#

HDDDRV#_5

Adapter In

AD+ DCBATOUT5V_AUX_S5

MAX8744

-4-5-6

-7

1

2

23 4

1D5V_S0

DDR_VREF_S3

S3

7

7 8

9

10

11

12

13

S5_ENABLE

5

4

5

5

CD ROM

PM_SLP_S4#

PM_SLP_S4#

PM_SLP_S3#PM_SLP_S4#

DDR_VREF_S0

5

3D3V_S55V_S5

-2S5_ENABLE

-1-1

APL5915

APL5913

6

1D8V_S0

1D8V_S3

WPC8768L

3D3V_AUX_S5

-3G909

PM_SLP_S3#

TPS51124

PG1

PG2EN1 EN2

51D8V_S3 1D05V_S0

4

1D8V_S3

DCBATOUT

1D8V_S0 1D8V_S35

18ms after VCCRTC

RTC_AUX_S5 VCCRTC

VCCSUS1_05

10ms after VCCSUS1_05

10ms after VCCSUS1_05

3ms after VGATE_PWRGD99ms after 1D05V_S0

GOLDFINGER

LAN

MINICARD

NEWCARD

WINDBONDCK_PWRGD

CLK_PWRGD

TP

Page 4: Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

Volvi2 Power ON Sequence

Page 5: Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

ICH8M

VCC_CORE_S0

Crestline Merom

VCC_CORE_S0 (CORE) (47A)1D05V_S0 (FSB VCCP) (4.5A)1D5V_VCCA_S0 (PLL) (130mA)

CLK GENICS 9LPRS502

220mA

CODEC3.3V(35mA)5V(55mA)

LPCROM6mA

DDRII 1D8V_S3(5000mA)

DDR_VREF__S0(1.2A)

17204mA

1D8V_S3

Mini card802.11/BT

660mA

VCC_CORE_S0

3D3V_S5

1D8V_S3

3D3V_S5

47000mA

5331 mA

200mA

3D3V_S0

5V_S0

CRT500mA

HDD2000mA

CD ROM1500mA

AMP 1431800mA

TOUCHPAD25mA

LCD400mA

3645 mA

1D5V_S0

FAN500mA

1D5V_S0

KBC Winbond WPC8763L3D3V_AUX_S5(170mA)

KBC EV BD

1D05V_S01D05V_S0

1510mA5V_S5

3D3V_AUX_S5

Marvell 88E8039LAN3D3V_LAN_S5(500mA)

5V_S5

8598mA

2660mA

907mA

DDR_VREF_S0 1200mA DDR_VREF_S0

MDC40mA

1D25V_S01D25V_S0 710mA

AMP 1410408mA

1D05V_S0 (CORE+GFX) (11310mA)(11573mA)1D25V_S0 (PLL/DMI)(710mA)1D5V_S0(TV/CRT) (130mA)1D8V_S3 (DDRIO/LVDSIO) (3598mA)3D3V_S0 (TVDAC/CRT Sync/IO/Bandgap) (316mA )

1D05V_S0 (Core/I/O) (1131mA)1D5V_S0 (Azalia/PATA/PCI/PCIE/DMI/ SATA/LPC/USB) (2400mA)3D3V_S0 (LAN/SPI) (400mA)3D3V_S5 (SUS) ( 277mA)5V_S5 (SUS) (10mA)5V_S0 (USB/PATA/PCI) (6mA)

3D3V_AUX_S5

ExpressCARD

1000mA

BIOS ROM30mA

Power Budget Block Diagram

5V_AUX_S5 5V_AUX_S550mA

USB*31500mA

Page 6: Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

LPC BUS

KBCWPC8763L

ECSCI#

SMI#

PWUREQ#ECSWI#

ECSCI#_1GPIO7

GPIO8

GPIO12

Volvi2 SMI/SCI/SWI Interface

HDA_SDIN0

PWRBTN#

ICH8-M

Power Switch block

AC_Link

AC_IN#

BAT_IN#

GPIO06

From S3 state wakeup event: (1) Power Button; (2) WOL ( AC Only ); (3) Embedded Modem ( AC Only ) ;(4) RTC; (5) Lid; (6) Battery Critical

PM_SLP_S3#

GPIO07

KBC_PWRBTN#

LID_CLOSE#

RSMRST#

GPIO12

G792THRM/FanAlert#

RSMRST#

ACZ_SDATAOUT

HDA_SDIN1CODECALC268

MDC

FWH

ACZ_SDATAIN0

GS

D

1

23

3D3V_AUX_S5

12

12

C

12

ECRST#

GPIO23

VCC_POR#

GPIO40

GPIO03

X-Bus

GPIO01

HDA_SDOUT

ACZ_SDATAIN1

RSMRST#_KBC

PM_PWRBTN#

Page 7: Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

ACZ_SPKR

CODECREALTEK ALC268

ICH8-M

CDRCDLCD-GND

Line Out

PCBEEP

MIC1_RMIC1_L

PHONE

Volvi2 Audio Block Diagram

MDC CON.

Mic-In

H.P. Jack

Line Out

2 Watt

2 Watt

AC97

KBCWPC8763L

KBC_BEEP

AUDIO_BEEP

LINR_IN_R

LINL_IN_L

INT_MIC1_CN

Audio AMP.

G1431F

Audio AMP.

G1412R

MIC2_RMIC2_L

Page 8: Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

Volvi2 SMB Interface

KBC

WPC8768L

3D3V_AUX_S5

VCC

3D3V_AUX_S5

Battery AID=16/17

3D3V_S0

ICH8_M

SMBC_ICH

SMBD_ICH

CLK GEN ICS 9LPRS502

ID=D2/D3

ThermalG792ID=7A/7B

DDR2DIMM B

ID=A2/A3

DDR2DIMM A

ID=A0/A1

5V_S03D3V_S5 3D3V_S0

4D7K4D7K

1D8V_S0 1D8V_S0 3D3V_S0

5V_S0

5V_AUX_S5

10K

KBC_SCL2

KBC_SDA2

3D3V_S0

10K

BAT_SCL

BAT_SDA

Page 9: Block Diagram. DREFSSCLK (100 MHz) DREFSSCLK# (100 MHz) CLK_ICH14 (14.318 MHz) CLK_MCH_BCLK# (166 MHz) Volvi2 Clock Block Diagram CPU Crestline CLK_CPU_BCLK

CrestlineGMCH

GMCH_DDCCLK

GMCH_DDCDATA CRT

LCD

CLK_DDC_EDID

DAT_DDC_EDID

2.2K

CLK_DDC1_5

DAT_DDC1_5

Volvi2 SMB Interface3D3V_S0 5V_S0

10K

3D3V_S0

2.2K