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The B&K-hecision Model 530 Semiconductor Tester is de-signed for in-circuit and out-of-circuit semiconductor testing,with special f 'eatures for nraking additional tests on devicesout-of-circuit. It uses a high-current, low duty-cycle pulsetechnique to test transistors in the presence of shuntingcircuitry. and a low-current drive systern which enables theuser to identify the ternrinals of the device in mostin-ciicuit tests and all out-of-circuit checks.

An exceptional feature is provision for rleasurement ofthe frequency at which transistor gain is one or unity. This

is the fr rating for a transistor and is applied to bipolardevices.

For out-of-circuit measurements of transistor beta andFET gm, the low duty-cycle, high-power pulse techniqueprovides for testing high current devices at rated current, upto 2 amperes, without over-dissipation.

The instrument is designed for a minimum amount ofcontrol manipulation, facilitating rapid testing of mostdevices.

INTRODUCTION

SPECIAL FEATURES

l . Patented linrited-energy pulse circuit permits highlysuccessful use of in-circuit testing in the presence oflow shunt irnpedances with complete safety for thedevice under test.

Six-position TEST switch sequentially connects thedevice being tested in all possible configurationsnraking it unnecessary to know the device terminalidentif ication. Can be left in GOOD position so thatadditional tests can be made without memorizing testposi t ion.

Base or gate lead identified by color as Test Switch isoperated when testing with HI drive. All leads oftransistor are identified when testing with LO drive.Gate lead is identif ied on FET's.

4. Autornatic polarity indication to identify NPN or PNPbipolar devices and N-channel or P-channel for FET's.

5. A-udible tone tells when the device under test isgood - no need to take eyes off circuit board whiletestins hard-to-set-at devices.

Measures beta of low-power and high-power transistorsin two ranges. A special 300 pSEC , l% duty-cycle,high-current (1. = 2 arnp for 0 = 200) pulsing circuitfor accurate ttsting of power transistors withoutoverdissipation.

Measures & (gain-Uandwidth product) of bipolar tran'sistors.

Measures gm of low-power and high-power FET's.Both depletion-mode and enchancement-mode powerFET's can be tested.

Measures voltage breakdown and reverse voltage leak'age ratings up to 100V. Automatic current limitingprevents damage to devices under test.

Has a compressed leakage meter scale, which displays awide leakage current range on a single meter.

Clip-on test leads make positive connections to devicesin difficult locations. Frees operator's hands to makefurther tests.

Choice of test leads or front panel sockets forout-of-circuit tests.

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BRIEF SUMMARY OF WHAT THE 530 WILL DO

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1. Determines good or bad transistors, FET's or SCR's, in-or out-of-circuit.

2. Determines good or bad diodes in' or out'of-circuit. -

3. Identifies Emitter-Base-Collector leads of transistors.

4. Identifies gate lead of FET.

5. Indicates polarity of good devices (NPN or PNP; N or Pchannel).

6. Identifies Cathode-Gate-Anode leads of SCR's.

7. Measures all breakdown and leakage parameters oftransistors.

8. Measures lpg5 and gate leakage of FET's.

9. Measures BVggg of transistors and PIV of diodes up to100 v.

10. Measures reverse leakage current of diodes.

1 1. Measures fr of bipolar transistors, in 3 ranges:0-100 MHz, 0-500 MHz,0-1500 MHz.

12. Determines whether device is a transistor, FET or SCR.

13. Will test new power FET's, both enhancement anddepletion types.

HINTS AND KINKS

IDENTIFYING TRANSISTORS AND DIODES

1. Nearly all germanium transistors come in .rnetal cases,either the tubular type with flexible leads, or in thestandard TO-5 package.

2. Power transistors in stud packages or in the TO-5 orTO-3 can be either germanium, siliCon or FET. Two-and three-digit 2N-numbers are mostly germanium.

3. The T0-66 power transistors and the plastic power tabpackages are nearly always silicon. The collector isusually, but not always, connected to the mounting taband the center lead. This always can be verified by acontinuity check between the collector pin and themounting tab.

4. The base leail of most modern plastic-type transistors iseither the center lead or the right-hand lead whenfacing the flat side with the leads down. In the lattercase, the collector lead is in the middle.

5. Most plastic FET's have the gate lead on the right sidewhen facing the flat side with the leads down and thesource in the middle, but there are exceptions. Innearly all junction FET's, the source and drain can beinterchanged with no adverse effects.

All transistors will have some gain with the collectorand emitter leads interchanged, with the exception ofDarlingtons.

Germanium signal diodes usually can be recognized bytheir transparent hollow glass cases with either three orfour color bands, or type numbers printed on them.Silicon diodes usually are painted because silicon islight-sensitivg urd must be protected from ambienttiftrt. fne "moose" types, such as the'stud package,can be either germanium or silicon.

8. Power FET's in TO-3 packages generally have leadconfigurations similar to bipolar transistors, with thefollowing comparisons :

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The APPENDIX to this instruction manual providesthe schematic symbols for devices tested by the Model530. This information should be used to identify thedevice prior to testing.

An extensive list of semiconductor test and operatingparameters is provided in the APPENDIX also.

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USING THE MODEL 530

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CAI.]"fIONMake sure all power is turned off in the circuitbeing tested, and that all capacitors are dis-charged.

A. Transistors and FET's:1. Set the DRIVE Switch (5) to the LO position.2. Connect the three test leads (in any manner) to

the three leads of the device you wish to test. Thetest leads must be plugged into their respectivecolor Test kad Sockets (6).

3. Move the Test Switch (4) slowly through its sixpositions until one of the two red lamps (1) or (2),glows. A tone also will be heard if SPEAKERSwitch (8) is ON. The lamp that glows indicateswhether the device is NPN (l) or PNP (2) or N oiP channel. In LO drive, most transistors that testgood will do so in only one Test Switch position(see "THINGS TO KNOW ABOUT THE 530"). Inthis Test Switch position, all the leads of thetransistor can be identified as shown in the I-eadIdentification Window (3). Most FET's will testgood (LO or HI drive) in two Test Switchpositions having the same BASE color shown inthe IBad Identification Window (3), since practi-cally all junction FET's are symmetrical. TheBASE color indicated is the gate Iead of the FET.

4. If there is no good indication (neither of the twolamps glows) as the Test Switch (a) is slowlymoved througlr its six positions, in LO drive, thenthe device under test is one of the following:

a. Device with high leakage or very low gain(-uy not function properly in circuit).

b. Device with open/shorted elements.

c. Device with excessive circuit shunting (see"SPECIFICATIONS").

d. FET that will not test with LO drive.

5. Re-test the device, using HI drive. In HI drive,most transistors that test good will do so in /woadjacent Test Switch positions having the sameBASE color shown in the kad IdentificationWindow. Only the base lead of the transistor canthen be identified.

6. If the device tests good using HI drive, then 4(a) or4(d) above could be true.

7. If the device does not test good in any Test Switchposition, in HI drive, lemove the device from thecircuit and re-test using OUT-OF-CIRCUIT pro-cedures.

B. SCR'S:1. Set the DRIVE switch (5) to the HI position.

t 0

2. Connect the three test leads (in any manner) tothe tfuee leads of the SCR you wish to test.

3. Move the Test Switch (4) slowly through its sixpositions until the NPN lamp (l) glows in oneposition and PNP lamp (2) glows in anotherposition haying a different BASE color as shown inthe Lead Identification Window (3).

4. The SCR is good only if the following indicationsare obtained:a. One NPN.b. One PNP,

NOTE: indications must not have same BASE color.

LEAD IDENTIFICATION:a. The BASE color shown in the kad ldentifica'

tion Window (3) is the gate lead when theNPN lamp (1) glows.

b. The BASE color shown in the kad ldentifica'tion Window is the cathode lead when thePNP (2) lamp glows.

5. If the SCR tests bad, then it should be removedfrom the circuit and tested again (muy be subjebtto excessive shunting in-circuit), using out'of-circuit procedures.

C. Diodes:l. Set LEAKAGE VOLTS control (14) to zero.

2. Set Test Switch (a) to top position (Green baseidentification).

3. Set NPN/PNP Switch (12) to PNP.4. Connect the blue and yellow test leads across the

diode to be tested.

5. Adjust the LEAKAGE VOLTS Control (1a) toapproximately l0 volts, as indicated on the con'trol panel.

6. Depress the PUSH-TO-TEST Switch (13) and,while keeping this switch depressed, rotate the lest .Switch (a) to each of the upper two positions.(Green base identification.)

7. While performing step 6, observe the results onLEAKAGE/GAIN Meter (19). The meter readingwill be approximately full scale for one position ofTest Switch ( ) while the other position of theTest Switch will give a lower reading, dependingon the shunting effect of the circuitry. In theposition giving the highest reading, the cuthode ofihe diode under test is connected to the test leadhaving the collector (C) color in the Lead Identifi'cation Window (3). If both positions producefull-scale readings the diode is either shorted orheavily shunted by low-resistance circuitry; forexample, a transient suppressor diode across arelay

-or a solenoid coil. In this case the diode

should be disconnected from the circuit andre-tested using OUT-OF-CIRCUIT procedures.

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3. fr Tests:

Measurement of the fr parameters of bipolartransistors is complex in theory and performance.A detailed explanation of fr measurements isprovided in the appendix of this manual.

When measuring fr, it is important to know that,with some transistors. the same meter deflectionmay occur on two ranges, such as the 0-100 MHzand the G500 MHz ranges. The fr of the transistoris always the range reading that gives the highestnumerical value (in this example, the reading onthe 0-500 rimge applies).a. To obtain reliable information regarding the

frequency characteristics of the transistorunder test, the lead identification and polarityof the device must be known as determined inthe previous tests.

b. Insert the transistor under test into theappropriate fr test socket (15) or (16). Thetransistor leads must properly match thesocket lead designations. If the device cannotbe made to fit into the socket provided, usethe three-lead adapter provided to make theconnections to the transistor. Note that anyadditional lead length can be detrimental tothe accuracy of this test; therefore, thethree-lead adapter should be used only ifabsolutely necessary.

c. Set the fr RANGE MHz Switch (17) to the0- 1500 range and read the value on the frmeter (18) on the 1500 MHz scale.

d. If the reading is greater than 300, this is the frof the transistor under test.

e. If the observed reading is less than 300, setthe RANGE, MHz switch (17) to the 0'500range and observe the meter (18). If thereading is greater than 50, this is the fr of thetransistor under test.

f . If the observed reading is less than 50, set theRANGE, MHz switch (17) to the 0-100 rangeand observe meter (18). This is the fr readingof the transistor under test. The accuracy ofreadings below 5 on this range is questionable.

E. If there is a difference in readings on tworanges where the scales overlap, the largestabsolute value for fr is the most accurate.

NOTE ON VOLTAGE ANDBREAKDOWN TESTS

All voltage and breakdown tests outlined hereeliminate the need to know the device leadidentification when beginning the test. In caseswhen the device lead identification is known,the following table indicates the connectionsrequired for the device tests. The indicatedpositions of Test Switch (4) correspond to the

uppermost for position I and the adjacentposition for position 2. Both of these TestSwitch positions have the green base identifi-cation in [rad ldentif ication Window (3).Connections can be made to the test leadsprovided or the device can be inserted into TestSocket (7). The required connections areindicated by an "X". Where no connection isrequired, "NC" is entered.

TEST LEAD COLOR AND NUMBER

BVCpS (Collector-Emitter Breakdown VoltageWith Base Shorted to Emitter):a. Connect transistor to the test leads or plug it

into the test socket (7).

b. Make sure the DRIVE switch (5) is in the LOposition.

c. Move the Test Switch (4) to the positionwhich produces a good indication, as in-dicated by the polarity lights (l) or (2).

NOTE

If the good-bad test of paragraph "A-1" resultsrn a good indication in two adjacent positionsof Test Switch (4), the collector can beidentified by observations during the leakagetest as follows:

o Set the LEAKAGE VOLTS Control (14)to about 10 volts.

o Depress the PUSH-TO-TEST Switch (13)and move the Test Switch (4) between the twopositions which gave a good indication.

r The Test Switch (4) position which givesthe lowest indicated current on LEAKAGE/GAIN Meter (19) is the position in.which alltransistor leads can be identified.

d. Set the NPN/PM Switch (12) to the positioncorresponding to the polarity light (1) or (2)which lights.

e. Set the LEAKAGE VOLTS Control (l ) tozero.

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DeviceTests

Yellow (3)

Emitter

Green (2)

Base

Blue ( l)

Collector

TestSwitchPosition

BVCES, ICpSBVCEO, ICEOBVCBO,tCgOBVECS, IgCSBVECO, Ip,COBVEBO, Ig,gO

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NCXXX

XNCXXNCX

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e.d. Depress the PUSH-TO-TEST button (13) andset the LEAKAGE VOLTS control (14) to thespecified test voltage.

Disconnect the voltmeter, if used, after thetest voltage has been set; otherwise the leak-age current measurement will be in error.

With'the PUSH-TO-TEST button (13) de-pressed, observe the leakage current asindicated on LEAKAGE/GAIN meter (19).This is the 1699 value of the device undertest.


With the PUSH-TO-TEST button (13) de-pressed, observe the leakage current as in-dicated on LEAKAGE/GAIN meter (19). Thisis the IpgO value of the device under test.

f.

10. BVB3O (Reverse Emitter-Base Breakdown VoltageWith Collector Open):a. Set the LEAKAGE VOLTS Control (la) to

zeto,

Set the Test Switch (4) to the positionadjacent to that used for the BV6'ps test ofparagraph "2" which has the sarne*Firr colorindication in kad Identification Window (3).Disconnect the collector lead, either by dis-connecting the test lead if so connected, or bybending the collector lead and inserting thetransistor in Test Socket (7) so that only theemitter and base leads are connected.

Depress the PUSH-TO-TEST switch (13) andadjust the LEAKAGE VOLTS Control (14)until a sharp increase or sudden change incurrent is observed on LEAKAGE/GAINmeter (19). This is the BVegO voltage of thedevice under test. This voltage can bemeasured accurately by connecting a high-impedance voltmeter across the base andemitter terminals of the device under test. Donot leave the voltmeter connected after thevoltage is adjusted.

12. BVBCO (Reverse Emitter-Collector BreakdownVolfage With Base Open):a. Set the LEAKAGE VOLTS Control (14) to

zeto.

Set the Test Switch (4) to the positionadjacent to that used for the BV6'pg test ofpaiagfaph "2" which has the same-Fise colorindication in I-ead Identification Window (3).Disconnect the base lead, either by discon-necting the test lead if so connected, or bybending the base lead and inserting the tran-sistor in Test Socket (7) so that only theemitter and collector leads are connected.

Depress the PUSH-TO-TEST switch (13) andadjust the LEAKAGE VOLTS control (14)until a sharp increase or sudden change incurrent is observed on LEAKAGE/GAINmeter (19). This is the BVECO voltage of thedevice under test. This voltage can bemeasured accurately by connecting a high-impedance voltmeter across the collector andemitter terminals of the device under test. Donot leave the voltmeter connected after thevoltage is adjusted.

I3CO (Reverse Emitter-Collector Current WithBase Open):This current is a specified limit at a specified testvoltage. If these values arc known, proceed asfollows:

Leave Test Switch (a) in the test position usedin the previous test.

The transistor connections are the same as inthe previous test.

If only an approximate voltage indication isrequired, the panel calibration of the LEAK-AGE VOLTS control (14) can be used. If theexact test voltage is desired, connect a high-impedance voltmeter to the emitter andcollector terminals of the device under test.

Depress the PUSH-TO-TEST button (13) andset the LEAKAGE VOLTS control (14) to thespecified test voltage.


b .

c.b.

c .

d.

13.

11. IBgg (Reverse Emitter-Base Current With Collec-tor Open):This current is a specified limit at a specified testvoltage. If these values are known, proceed asfollows:

a. Leave Test Switch (4) in the test position usedin the previous test.

b. The transistor connections are the same as inthe previous test.

c. If only an approximate voltage indication isrequired, the panel calibration of the LEAK-AGE VOLTS control (14) can be used. If theexact test voltage is desired, connect a high-impedance voltmeter to the emitter andbase terminals of the device under test.

d. Depress the PUSH-TO-TEST button (13) andset the LEAKAGE VOLTS control (14) to thespecified test voltage.

a.

b.

d.

l 4

e.

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3. IpSS Current:

Currents up to 5 milliamps can be measured belowl0 volts; the current indication is limited to 100microamps when testing above 10 volts. Althoughthe Ip55 values for many J-FET's are specified atdrain-to-source.voltages above l0 volts, the Ip55values obtained between 5 and l0 volts cariSeconsidered accurate because the drain currentcharacteristic usually is constant above a few volts(Sqf. Fig. 3). Most power FET's will providefull-scale readings because the IpSS values areconsiderably higher than 5 milliamps. If a full-scalereading is obtained below 5 volts, the actual IOSSvalue is geater than 5 milliamps and cannot bemeasured accurately with the Model 530.

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Vs5- DRAIN SOURCE VOLTAGE (VOLTS)

Fig. 3. Typical depletion mode FET characteristics.

Set the LEAKAGE VOLTS control (14) tozeto.

Move Test Switch (4) to a position whichproduces a good indication.

Set the NPN/PNP switch (12) to the positionindicated by GOOD test lights (l) or (2).Depress the PUSH-TO-TEST button (13).Increase LEAKAGE VOLTS control (14) andobserve LEAKAGE/GAIN meter (19). Do notexceed 10 volts unless the FET type and testparameters are known. A high-impedance volt-meter can be connected across the drain andsource of the device under test to determinethe exact voltage corresponding to an ob-served IOSS reading. Once the observed cur-rent exceeds 5 milliamps below 10 volts orexceeds 100 microamps above l0 volts, thepanel voltage calibration does not apply be-cause of the built-in current limiting circuitry.

The LEAIGGE/GAIN meter (19) will readIpSS. IpSS of FET's can range from a few

microamperes to several milliamperes, and insome cases will be limited to 5 mA.

FET Gate l-eakage: Drain-to-Gate and/or Source-to-Gate lrakage.

a. Note the polarity indicated by lights (1) or (2)in the GOOD test.

b. Set the NPN/PNP Switch (12) to the oppositepolarity of that indicated in (a).

c. Set LEAKAGE VOLTS Adjust (14) to l0volts, approximately, or the desired test volt-age, if known.

d. Depress the PUSH-TO-TEST button switch(13) and move the Test Switch (4) through allsix positions and watch LEAKAGE/GAINmeter (19). If the device is good, the meterwill indicate zero current in two of the sixTest Switch positions.

FET Drain-to-Gate or Source-to-Gate Leakage(Junction Diodes):

a. With the FET connected to the test leads orinserted in test socket (7) place DRIVESwitch (5) in the HI position and operate TestSwitch (4) until a good indication is obtained.La*p (l) or (2) will light.

b. Note the base color which appears in the l*adIdentification Window (3). This identifies theconnection to the gate of the FET under test.

c. Set LEAKAGE VOLTS control (14) to z.ero.d. Set the NPN/PNP switch (12) to match the.

polarity indicated by lights (l) or (2).e. Pqsition the Test Switch (4) so that the color

associated with the gate lead is indicated asthe collector lead in the Lead ldentificationWindow (3).

f. Depress the PUSH-TO-TEST switch (13) andslowly adjust the LEAKAGE VOLTS control(14) starting at zero and gradually increasinguntil a sudden increase in leakage current isindicated on LEAKAGE/GAIN meter (19).The current and the corresponding voltagehave the following meaning for two types ofFET's:

J-FET: Forward bias current and voltagefor the gate-to-channel P-N junc-tion.

MOS-FET: The Breakdown voltage for thecombined currents of the gate-to-channel leakage current and theprotection diode if present ondevice.

Depletion Mode FET's (low-power):

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a. One NPN indication.

b. One PNP indication.

c. Indications must not have same BASE color.

LEAD IDENTIFICATION:

a. The BASE color shown in the I*ad ldeptifica-tion Window (3) is the gate lead when theNPN lamp (l) glows.

b. The BASE color shown in the kad ldentifica-tion Window is the cathode lead when thePNP lamp (2) glows.

MODEL 530 CIRCUIT DESCRIPTION

A. Test Switch

The 530 semiconductor tester uses a six-positionlever switch located at the top right corner of thefront panel. This switch is used to connect thedevice being tested in the correct' manner fortesting. As this test switch is moved through itspositions, the device that is connected either tothe three test leads or plugged into the test socketis connected in all possible configurations forfurther testing. The uppermost position is the"normal" connection, that is the test socket isconnected in the standard triangle configuration tothe testing circuits and the blue, green and yellowtest leads are connected to the collector, base, andemitter circuits respectively (drain, gate and sourcefor FET's).In two of the six positions, using HI drive, thedevice is connected properly for the basic testcircuitry. This is true since all bipolar transistorshave gain, although usually very little, when thecollector and emitter are interchanged, and mostjunction FET's are symmetrical. These two testswitch positions are always adjacent and alwaysdisplay the same base color in the lBad Identifica-tion Window whenever the 530 is indicating agood device.

In LO drive, a transistor should indicate good inonly one test switch position since limited basedrive and lower detection sensitivity allow thedetector to test the device as good only in its highgain connection. A device that indicates good in asingle test switch position in LO drive is connectedproperly for further gain testing with the Model530.

B. Good/Bad Test Circuitry

l. The Model 530 test circuitry uses two clockgenerators that produce a series of pulses designedto test a device periodically, about seven times persecond. These short, high-current pulses areapplied to the collector (drain); the first is positivefor testing NPN/N-CH devices, followed by anegative pulse for testing PM/P-CH devices.During these pulses, a shorter pulse of the samepolarity is applied to the base (gate) of the device,which drives the collector (drain) voltage towardsaturation. (See Fig. 4, pulses A and B.)

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Taking a closer look at the basic test circuitry,refer to Fig. 4 and schematic. The slow clock,which runs at approximately 7 llz, initiates eachtest period while simultaneously resetting flip-flopI and flip-flop 2. The fast clock runs at approxi-mately 500 Hz and controls the pulse-formingcircuits.

The pulse-forming circuit uses a combination oftoggles and RS flip-flop to produce the propersequence of pulses for the collector (drain) drivecircuit, and the base (gate) drive circuit.The collector (drain) and the base (gate) drivecircuits arc level-shifting complementary driverswhich can deliver several hundred milliamperes at+5V and -5V, or return to zerovolts.

A properly connected NPN or N-channel devicewill see both waveforms 'A' and 'B' of (Fig. a).The collector (drain) will see waveform 'A', andthe base (gate) of the device under test will seewaveform'B'.

Note that during the positive excursion of thecollector (drain) voltage, the base (gate) is drivenfirst negative and then positive.

If the device being tested is NPN or N-channel, thecollector (drain) voltage will drop abruptly whenits base (gate) is driven positive. This negative-going transition, which will only occur if gainaction is present (a good device), is differentiatedand the signal produced is used to latch flip-f[op 1of Fig. 4.

If a PNP or P-channel device is tested, the turn-ontransition occurs during the second half of wave-form 'A' of Fig. 4, and in the opposite direction.This transition (positive-going) is differentiatedand the produced signal is inverted and used tolatch flip-flop 2 of Fig.4.

Of course, other pulses appear at the differentiatoroutput, since all voltage transitions of pulsg 'A' aresimilarly differentiated, but the synchronizedgating circuits prevent the unwanted pulses fromreaching flipflops I and 2, thus eliminating wrongindications.

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time period in which a NPN or N-channel devicecan be detected and similarly flip-flop 2 is enabledonly when a PNP or P-channel device can bedetected. Only the flip-flop which corresponds tothe type of device being tested can be latched.

4. The outputs of flip-flops I and2 of Fig. 4 are either+5V or - 5V, depending on whether the devicetested was a good MN/P-channel or PIIP/P-channel. The output from the activated flip-flopdrives a LED DRIVER which produces enoughcurrent to turn on the corresponding front panelindicator, the NPN/N-channel or the PNP/P-channel LED.

When either flip-flop I or 2 is latched, the speakerdriver is activated and audible tone is heardthrough the speaker, indicating a good device.

Leakage/Breakdown Test Circuitry

1. The 530 leakage/breakdown voltage circuitry usesan externally controlled DC power supply. Voltageand. current sensors control automatically, viafeedback, the voltage regulator that feeds theexternal load (See Fig. 5 and schematic).A four-stage amplifier circuit is used to drive ameter driver which in turn drives the meter, on a 0to 5 mA non-linear scale.

2. Taking a closer look at the leakage/breakdownvoltage circuitry, refer to Fig. 5 and schematic.

A voltage-adjust potentiometer is connected to aDC power supply. This potentiometer which is thefront panel LEAKAGE VOLTS control, drives aseries regulated circuit, and it can vary from zeroto 100V. The voltage regulator is fed back throughvoltage and current sensors, which automaticallycontrbl the voltage and current outputs to theexternal load.

3. The external load (device under test) is connectedto the voltage regulator through the polarityswitch (NPN N-channel/PNP P-channel), the leverTEST SWITCH, and is activated when the PUSH-TO-TEST switch is pressed.

When the LEAKAGE VOLTS control on the frontpanel is turned clockwise, the external load voltagecan go up to 100V DC, but this is ture as long asthe load current is 100 pA or less. As the loadimpedance drops, the voltage regulator which isfed back through the voltage and current sensors,starts to reduce the voltage to maintain 100 pAthrough the load. This output voltage reductionand constant current of 100 pA will continue untilthe voltage across the external load drops to aboutlOV. If the load impedance is reduced to lower theexternal voltage below about 10 volts, the lowvoltage current-limiting circuit takes over and theindicated current on the LEAKAGE/GAIN meterwill increase to 5 milliamperes.

Further reduction of the load impedance, up to acomplete short, will reduce the load voltage tozeto-. The vbltage regulator is currentJimited andcan deliver only 5 mA to the external load.

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A.

MAINTENANCE AND CALIBRATION

I*akage/Gain Meter "Zero" Calibration

1. Turn the Model 530 power off. If LEAKAGE/GAIN meter (19) does not indicate zero, insert asuitable Screwdriver in the hole just below themeter and adjust it to indicate zrjro on top scale.

2. Turn the Model 530 power on, if the LEAKAGE/GAIN meter (19) indicates zero on top scale,proceed to step H.lf the LEAKAGE/GAIN meter(19) does not indicate zero, turn the 530 power

17,

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Hi I MeterScale

NPN SocketB

Fig. 12. Field calibration, fr circuit.

(d) Adjust R-22 for a collector current of l0milliamperes (See Fig. 8 for location of R-22).

(e) Remove NPN Transistor and insert PNP Tran-sistor into front panel socket labeled PNP (15)with current meter in series with the collectorlead (See Fig. l3). Current measured shouldbe between 9 and 1l milliamperes for properoperation.

PNP Socket

Fig. 13. Field calibration, fr circuit.

Calibration of I MHz, l0 MHz, and 30 MHzoscillators.

Equipment Required:

. Frequency Counter - 100 mV sensitivityat frequency up to 30 MHz (B & K-Precision Model 1801).

. Any NPN transistor with an fr of greaterthan 500 MHz.

. Non-metalliccoil-adjustingtool.

(a) Tum Model 530 power on.(b) Insert NPJrl transistor into front panel socket

labeled NPN (16). All frequency measure-ments are taken at TP-4. See Fig. 8 forlocation of TP-4 and oscillator coils.

PulseHeigh t {V}in Volts

E.

Fig. 11. Hi p calibration chart.

"TRANSISTOR BETA" position, and adjust trim-pot R-92 with suitable screwdriver so that LEAK-AGE/GAIN meter (19) reads the recorded "HI pCAL" value (found in step 6) on the "HI p" scaleof the LEAKAGE/GAIN meter (19).

fr Circuit Calibration1. Tum Model 530 off. If fr OUT-OF-CIRCUIT

meter (18) does not indicate zero, insert a suitablescrewdriver in the hole just below the meter andadjust it to indicate zero on the top scale.

2. Remove the Model 530 bottom panel by removingthe five screws (three on the bottom panel andtwo on the back panel).

3. Turn Model 530 power on. Without any transistorsplugged into fr sockets (15) or (16), check for frmeter (18) reading of zero for each range selectedon the RANGE, MHz Switch (17). If the fr meter(18) does not read zero, adjust R-55 to obtain azero reading (Fig. 8).

4. Calibration of Automatic Bias Circuit.

Equipment Required:

. 4ny good quality digital Voltmeter (B & K-hecision Model 2S0).

o Any known good NPN and PNP Tran-sistors.

(a) Tum Model 530 power on.(b) Insert NPN Transistor into front panel tran-

sistor socket labeled NPN (16).(c) Place current meter in series with the collector

lead. (See Fig. 12.)

5 .

28

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2.

(g) Being careful not to break any wires, raise thefront edge of the main P.C. board and slide ittoward the front so that the back edge clearsthe transformer. Next, rotate the main P.C.board with the front edge up with the boardin the vertical position for full access to allcomponents.

(h) To replace the main P.C. board, reverse theprevious steps for removal.

Removal of fr P.C. board for service.

(u) On the control panel, pull to remove the knoband remove the mounting nut from theRANGE MHz switch (17).

(b) Turn the Model 530 over so that it lies withthe control panel face down and the bottompanel up,

(.) Remove the bottom panel by removing thethree screws in the bottom panel and- twoscrews in the back panel nearest the bottompanel.

(d) Remove the four P.C. board mounting screws(identified with an asterick in Fig. 8) fiom thefr P.C. board located as follows:

o Two screws near back panel.

o Two screws near front panel.

(e) Lift the fr board out and rotate it to asuitable position for access to service com-ponents.

(f) To replace the fr P.C. board, reverse theprevious steps for removal.

NOTES

30

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xtcNlddv

FIELD-EFFECT TRANSISTORS

Bm - common source transfer conductance. Ratio of ACdrain current to gate-to-source voltage in common sourcemode.

channel. A region of semiconductor material in whichcurrent flow is influenced by a transverse electrical field.A channel may physically be an inversion layer, a diffusedlayer, or bulk material. The type of channel is determinedby the type of majority carriers during conduction;i.e.,P-channel or N-channel.

depletion-mode operation. The operation of a field-effecttransistor such that changing the gate-source voltage fromzero to a finite value decreases the"magnitude of the draincurrent.

depletion-type field-effect transistor. A field-effect tran-sistor having appreciable channel conductivity for zerogate-source voltage; the channel conductivity may beincreased or decreased according to the polarity of theapplied gate-source voltage.

drain (D, d). A region into which majority carriers flowfrom the channel.

enhancement-mode operation. The operation of a field-effect transistor such that changing the gate-source voltagefrom zero to a finite value increases the magnitude of t[edrain current.

enhancement-type field-effect transistor. A field-effecttransistor having substantially zero channel conductivityfor zero gate-source voltage; the channel conductivity maybe increased by the application of a gate-source voltage ofappropriate polarity.

field-effect transistor. A transistor in which the conduitionis due entirely to the flow of majority carriers through aconduction channel controlled by an electric field arisingfrom a voltage applied between the gate and sourceterminals.

gaie (G,'g). The electrode associated with the region inwhich 'the electric field due to the control voltage iseffective.

insulated-gate field-effect transistor. A field-effe ct transistorhaving one or more gate electrodes which are electricallyinsulated from the channel.

junction fiunction-gate) field-effect transistor. A field-effect transistor that uses one or more gate regions thatform P-N junction(s) with the channel.

metal-oxide-semiconductor (MOS) field-effect tran-sistor. An insulated-gate field-effect transistor in whichthe insulating layer between each gate electrode and thechannel is oxide material.

N-channel field-effect transistor. A field-effect transistorthat has an N-type conduction channel.

P-channel field-effect transistor. A field-effect transistorthat has a P-type conduction channel.

source (S, r). A region from which majority carriers flowinto the channel.

32

substrate (U, u) of a junction field-effect transistor or aninsulated-gate field-effect transistor. A semiconductormaterial that contains a channel, a source, and a drain andwhich may be connected to a terminal.

substrate - of a thin-film field-effect transistor. An insulat-ing material that supports the thin semiconductor layer,the insulating layer, and the source, gate, and drainelectrodes.

tetrode field-effect transistor. A field-effect transistorhaving two independent gates, a source, and a drain. Anactive substrate terminated externally and independentlyof other elements is considered a gate for the purpose ofthis definition.

triode field-effect transistor. A field-effect transistor havinga gate, a source, and a drain.

Ip - drain current, DC. The direct current into the drainterminal.

IOSS - zerc-gate-voltage drain current. The direct currentinto the drain terminal when the gate-source voltage iszero. This is an on-state current in a depletion-type device,an off-state current in an enhancement-type device.

15 - gate current, DC. The direct current into the gateterminal.

ICSS reverse gate current, drain short-circuited tosource. The direct curient into the gate terminal of ajunction-gate field-effect transistor when the gate terminalis reverse-biased with respect to the source terminal andthe drain terminal is short-circuited to the source termi-nal.

15 - source current, DC. The direct current into the sourceterminal.

VBGSS - gtesource breakdown voltage. The breakdownvoltage between the gate and source terminals with thedrain terminal short-circuited to the source terminal.Note: Jh9 symbol VB65g is primarily used with junction-glte field-effect transistors. The symbols VBCSSR orVBGSSp' should be used with insulated-gate tiansistorshaving shunting diodes or similar voltage-limiting devices.

V-BCSSp - forward gate-source breakdown voltage. Thebreakdown voltage between the gate and source terminalswith a forward gate-source voltage applied and the drainterminal short-circuited to the source terminal. See V65p.

V-BCSSn reverse gate-source breakdown voltage. Thebreakdown voltage between the gate and source terminalswith a reverse gate-source voltage applied and the drainterminal short-circuited to the source terminal. SeevcsR.

VDD, VG_G, VSS - DC supply voltage for drain, gate,source. The DC supply voltage applied to a ciicuitconnected to the reference terminal.

VOC - drain-gate voltage. The DC voltage between thedrain and gate terminals.

VOS - drain-source voltage. The DC voltage between thedrain and source terminals.

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Icgo

DEFINITION

Collector-emitter breakdown voltage at a specifiedcurrent (lCgS) with the base shorted to emitter.

Collector-emitter current with the base shorted toemit ter .

Collector-base breakdown voltage at a specified cur-rent (Iggg) with the emitter open.

Collector-base current with the emitter open.

+V (NPN) -V (PNP)

+ V ( N P N ) - V (PNP)

BVcpo

IcEo

Collector-emitter breakdown voltage at a specifiedcurrent (ICgO) with the base open.

Collector-emitter current with the base open.

+V(NPN) -V(PNP)

Bvpcs

IEcs

Reverse emitter-collector breakdown voltage at aspecified current (1865) with the base shorted tocollector.

Emitter-collector current with the base shorted tocollector and reverse voltage.

+V(NPN ) -V(PNP)

BvBco

Inco

Reverse emitter-collector breakdown voltage atspecified current (IpCO) with the base open.

Emitter-collector current with the base open andreverse voltage.

+V(NPN) -V(PNP)

Bvpgo

IBgo

Reverse emitter-base breakdown voltage at a specifiedcurrent (IfgO) with the collector open.

Emitter-base current with the collector open andreverse voltage.

+V(NPN ) -V(PNP)

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Thyr is tor , b id i rect iona l d iode type; b i -swi tch

Graphic Symbols forSemiconductor Devices

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Temperature-dependent d iode

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U n i d i r e c t i o n a l d i o d e ; v o l t a g e r e g u l a t o r

Un i junc t ion t rans is to r w i th N- type base

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Documents

B&K 530 Semiconductor Tester