IEEE TRANSACTIONS ON COMPUTERS, VOL. C-19, NO. 5, MAY 1970

REFERENCES[1] M. B. Scott and R. L. Hoffman, "The Mercury programming

system," 1961 Proc. Eastern Joint Computer Conf., vol. 20. NewYork: Macmillan, p. 47.

[2] J. H. Mueller, "Philosophy of the RTCC control programs,"1966 Proc. Real-Time Systems Seminar. Houston, Tex.: IBMCorporation, November 1966.

[3] RTCC System Specifications, book II, sec. 3.1, RT 12112,June 15, 1967.

[4] E. R. Strecker and L. E. Kuhlken, "Generalized RTOS,"Independent Research and Development (IRAD) Rept.,March 1967.

[5] "Report on real-time operating system/360," Federal SystemsCenter, Houston, Tex., FSD, IBM, May 1968.

[6] B. L. Hanover, "RTOS design decision no. 6, RTOS/360 controlprogram services for real-time data tables," December 21, 1965(unpublished IBM Rept.).

[7] T. A. Humphrey, "Large core storage utilization in theory andin practice," 1967 Spring Joint Computer Conf., A FIPS Proc.,vol. 30. Washington, D. C.: Thompson, 1967, pp. 719-727.

[81 K. B. Adams, "RTOS design decision no. 31, dynamic LCSallocation," May 17, 1967 (unpublished IBM Rept.).

[9] W. I. Stanley and H. F. Hertel, "Statistics gathering and simu-lation for the Apollo real-time operating system," IBM Sys. J.,vol. 7, no. 2, pp. 85-102. 1968.

Biresidue Error-Correcting Codes

for Computer Arithmetic

THAMMAVARAPU R. N. RAO, MEMBER, IEEE

Abstract-In an earlier paper [111 a scheme for detecting errors inADD, COMPLEMENT, SHIFT, and ROTATE operations using a residuecheck circuitry was presented. A scheme for error location and correc-tion in those operations is derived by a suitable application of a codecalled biresidue arithmetic code described here. Any single errorposition can be located and also corrected by use of two residuecheckers which work separately and in parallel with the arithmeticunit. The estimated cost of redundancy is approximately the same asthat required for duplication of the arithmetic unit.

Index Terms-Biresidue codes, multiresidue codes, residuecodes, self-correcting computers, separate and nonseparate residuecodes, syndrome, syndrome decoder.

INTRODUCTION

AS THE complexity and size of modern computersincreases, the need grows for efficient self-de-tecting and self-correcting computation. The

class of codes known variously as AN codes [2], [4],residue class codes [8], or linear residue codes [3] isconsidered useful in monitoring errors in arithmeticoperations as well as in communication. The develop-ment of these codes is related to the theory and develop-ment of residue number systems [7], [14], [15]. FirstDiamond [4] and later Brown [2] developed the resi-due codes and discussed several interesting examples.Chien [3], Henderson [8], and Peterson [12] haveextended and proved a number of important theorems.Massey [lo] presents a firm mathematical foundationand an excellent survey of the earlier work on these

Manuscript received June 17, 1968; revised May 10, 1969. Thiswork was supported in part by National Science Foundation GrantGK-1543.

The author is with the University of Maryland, College Park, Md.

codes. Garner [6] establishes the algebraic structure ofthe separate- and nonseparate-type residue codes asmachine number systems. Mandelbaum [9] has exposeda new class of AN codes with large minimum distance.On the practical implementation of residue codes,

Avizienis [1 ] has developed algorithms for the practicalapplication of a 15N code for a diagnosable arithmeticprocessor. The author [II] has shown in detail in anearlier paper how an error can be detected with a sepa-rate residue code (N, NJ 3) for all arithmetic operationssuch as ADD, COMPLEMENT, SHIFT, and ROTATE. It isshown here that separate residue coding using two resi-due checks with respect to two suitable moduli providecorrection of single errors in the main processor or anyone of the checkers. If the moduli for the residuecheckers are of the type 2k -1, the maximum permissiblelength of arithmetic register is derived as a theorem.Later, practical implementation of these codes is con-sidered in some detail.

It is shown that all arithmetic operations such asADD, COMPLEMENT, SHIFT, and ROTATE can be monitoredin a parallel manner with practically no loss of speed ofcomputation. The residue checker circuits, the decoder,and the corrector would involve circuit redundancy nogreater than the arithmetic unit itself. It should be ofinterest to know that one well-known technique whichprovides error correction is the triplication and majorityvote-taking (or the so-called von Neumann approach)and that approach requires three times or more of circuitredundancy. Thus the coding approach presented herecould save considerable cost in circuits as well as inpower and size requirements.

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BACKGROUND

Representing an integer N by the product AN whereA is a suitable prime integer has been shown [2], [12]to yield error detection and correction. If AN is repre-sented in the binary form, single-error detection can beobtained for any range of values of N by choosing anodd integer A>3. Furthermore, if A is an odd primeand if 2 is a primitive element in the field of integersmodulo A, then correction of any single error is realizedif N is constrained to the range

0 < N < [2(A-l)/2 + 1]/A.A table showing the range of N for several values of Ais given in [12].Mandelbaum [9] discussed AN codes of "large

distance" by choosing A to be equal to (2P-1-1)/Pfor a suitable prime P. These codes provide multiple-error detection and correction and also are cyclic. Therange1 of these codes M, (O<N<M) is too small forapplication to computer arithmetic units. Besides, theAN codes are questionable from the practical pointof view of computer arithmetic.A separate residue code of interest is one where N

is coded as a pair (N, NJ A). An arrangement by whichthe processor operates on N and the "checker" operateson NJ A separately and in parallel with the processorhas some practical advantages. However, such a codecan only provide error detection but no correction.

Error-checking logic for operations such as ADD,COMPLEMENT, SHIFT, and ROTATE is derived through theuse of a separate residue code [11] in which it statesthat in order for the checking logic to be simple andeasy to implement, the following constraints are neces-sary.

1) A is to be of the type 2k_1, i.e., A =3, 7, 15, etc.2) The arithmetic logic is to be l's complement

arithmetic.3) The arithmetic registers must be of length n bits

so that k divides n. (Note 2k -1 =A.) The check circui-try required for A = 3 is of the order of 30 to 40 percentof the part of the processor that is subject to checking.

BIRESIDUE CODE

Consider an integer N coded as a triple (N, NJ A,NJ B) where A and B are two relatively prime integers.We call NJ A, NJ B the residues of N modulo A and B,respectively.2 We define the addition of two code words(N1, N1i A, N1i B), (N2, N21 A, N21 B) to result in(Ni+N2, NlIA+ N21 A, Nlj A+ I N2I B) where theaddition of the residues is carried out with regard to therespective moduli. The three components of the codeare called the accumulator part, the checker A, and thechecker B. The two definitions follow naturally.

1 Peterson [121 used M2(A, d) to denote the range of N, O<N<M2(A, d), for the binary AN codes of minimum distance d.

2 N|IA denotes the smallest nonnegative residue congruent to Nmodulo A. This is also the nonnegative remainder obtained when Nis divided by A.

Definition 1: A triple (X, Y, Z) is said to be a biresiduecode word with respect to moduli A and B if and only ifY=|X|A and Z=|X|B-Definition 2: A syndrome for a triple (X, Y, Z) with

respect to moduli A and B, denoted as S(X, Y, Z), isa pair (Sa, Sb) where Sa= |X- YA and Sb= |X-Z|B.From the two above definitions one could see trivially

that a triple (X, Y, Z) of integers is a biresidue codeword with respect to moduli A and B if and only if itssyndrome S(X, Y, Z) with respect to the same moduli A,B equals (0, 0).

Let (X, Y, Z) be a biresidue code word with respectto moduli A and B. Consider an error, e in any one ofthe three components of the code. The three possiblecases are as follows.

Case 1-Error in Accumulator Part: The erroneousword in this case be denoted by (X', Y, Z) whereX'=X+e. Syndrome S(X', Y, Z)=(|X'-Y|A,(X'-Z B)= (I ej A, |eI B). The error e goes undetectedif only e|A=|e |B=0.

Case 2-Error in Checker A: The erroneous word herecan be denoted by (X, Y', Z) where Y'= Y+e. Its syn-drome is ( -el A, 0).

Case 3-Error in Checker B: The erroneous word canbe denoted by (X, Y, Z') where Z'= Z+e. Its syndromeis (0, |-eI B).

If we consider class of errors e such that Ie IA0,eI B50, then the error in any component is detectedand located by the form of its syndrome. If the error islocated to one of the checkers, then it could be correctedby generating that residue from the result of the ac-cumulator. On the other hand, if the error is located tothe accumulator part, then the position and magnitudeof the error could be determined uniquely by the syn-drome (Sa, Sb), providing of course that the length of theaccumulator register is no greater than that specifiedby the moduli A and B. The following will provide abasis for length n of the accumulator register for anytwo given moduli which are of the type 2k -1 and alsoare relatively prime.Lemma 1:3 If GCD (a, b) = 1, then GCD * (2a'-1, 2b-1)

= 1.Proof: Let GCD (2a_1, 2b-1) =d-1 and let p be

any prime that divides d. Then 2a-1 =2b-10(mod P) and 2a=_2b 1 (mod P). If e is the exponent towhich 2 belongs in the field of integers modulo P, thene>1 divides both a and b. Therefore e divides GCD(a, b). In other words, GCD* (a, b) = ek for some integerk, which is contradictory. Therefore GCD * (2a- 1, 2b - 1)= 1, as is to be proved.Here we consider error patterns that affect the ac-

cumulator part. If we say e is the error value, we shallmean that the accumulator value x is modified tox' =x +e. By a single error we mean the value of e = ± 2for some j=0, 1, 2, - - *, n-1. In other words, there areexactly 2n single error patterns for an n-bit accumulator.

I We use GCD- as an abbreviation for greatest common divisor.

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Finally, since in I's complement arithmetic the additionis carried out with end-around carry (or modulo 2n- 1),the error value is to be determined by e = x'- x modulo(2n-1). Also the syndrome of (x', y, z) =S(x+e, y, z)=S(e, 0, 0)+S(x, y, z) =S(e, 0, 0).In order to correct single errors in the accumulator

part there should be a one-to-one correspondence be-tween the single error patterns and syndromes. The fol-lowing theorem leads to an upper limit for n, for twogiven moduli A and B of the type 2k _1, while preservingsuch (1 -1) correspondence.

Let n denote the number of binary positions in theaccumulator part.

Theorem 1: Let the moduli A =2a_1, B=2b-1 suchthat GCD* (a, b) = 1. The set of all single errors in theaccumulator denoted by {e= +2j, j=0, 1, 2, . ,n -1 } will have distinct syndromes with respect to A,B provided n is no greater than ab.

Proof: For a code word (x, y, z), the syndromeS(x, y, z)=0. For an erroneous accumulator part de-noted by x'=x+e, S(x', y, z) =S(x+e, y, z) =S(e, 0, 0)= (I el A, ! el B). As a first step we will show that S(2 i, 0, 0)5 S(-2 j, 0, 0) for any i, j. As a second step we will showthat for any i, j, i Lj if S(2i, 0, 0) =S(2j, 0, 0); then abdivides i-j which will complete the proof.

Let S(2i, 0, 0)=S(-2j, 0, 0). Then clearly |2i A= I-2jlA or 2i-j-=-1 (mod A). The residues moduloA 22a_ 1 of the powers of 2 follow the sequence 1, 2,4, . . , 2a-1, 1, 2 4, , ,etc., where !2iIA=12ilaIA.The only way that one of these residues could be con-gruent to -1 is that A =3. Similarly, we could showthat B =3, also, and therefore reach a contradiction.Now we let S(2i, 0, 0)=S(2i, 0, 0), i j; then 2i=2

(mod A) or 2 i-i = 1 (mod A). It follows that a divides(i-j). Similarily b divides i-j. Since GCD (a, b) = 1,a, b divides (i-j). Thus the syndromes of all singleerrors are distinct provided n<a, b.Example: Let A = 7 = 23-1- B = 15 = 24-1. From the

theorem n = ab = 3 X4 = 12, the syndromes correspond-ing to all single errors are shown in the table below.

Syndrome of +2i Syndrome of _2is = ~~(I +2il 7, 12i! 5) (I-2i 17, 12-ill65)0 (1, 1) (6, 14)1 (2, 2) (5, 13)2 (4, 4) (3, 11)3 (1, 8) (6, 7)4 (2, 1) (5, 14)5 (4, 2) (3, 13)6 (1, 4) (6, 11)7 (2, 8) (5, 7)8 (4, 1) (3, 14)9 (1, 2) (6, 13)

10 (2, 4) (5, 11)11 (4, 8) (3, 7)

12 (1, 1) (6, 14)

It is to be noted that the 24 syndromes listed above theline are distinct.A somewhat more general theorem may be stated by

removing the constraint GCD - (a, b) = as follows.

Theorem 2: For moduli A, B of the type 2k -1, the setof all single errors in the accumulator part denoted by

{e= + 2i, j=0,1,2, . .*,n-1}

will have distinct syndromes, provided n is no greaterthan the least common multiple of a, b.The proof is not very different from the previous one

and will not be given here.It was mentioned in an earlier paper [11] that the

implementation of residue codes is greatly simplified ifthe moduli divide the range of the accumulator numbersystem. For that reason l's complement arithmetic isnaturally chosen and the addition of Y to the accumula-tor contents X will result in X+ YJ M, where M= 2n _1.Also, 2a_ 1 divides 2n-1 if and only if a divides n. Thusn=a*b is an optimum choice.A natural extension of biresidue code is the multi-

residue code where N is represented as an m+1 tuple(N, N! A1, N! A2 I N Am) with respect to themoduli A1, A2, - * * I Am. If Ai=2a% -1 for each i andGCD- (As, Aj) = 1 for i j, then the length of the binaryaccumulator n can be equal to the product aja2 . . a.

ERROR CORRECTION THROUGH BIRESIDUE CODINGThe method we shall employ to achieve error correc-

tion is as follows (Figs. 1 and 3). We use two residuecheckers (one each for moduli A and B) which includetwo check registers CRA and CRB, respectively. If xdenotes the integer value of the accumulator at a giveninstant of time, CRA and CRB are to maintain the cor-responding residues X! A and XI B, respectively. Thethree registers, the accumulator, CRA, and CRB thuscontain a biresidue code word. We consider an operation4 on the accumulator such as ADD, COMPLEMENT, SHIFT,LOAD ACC., ROTATE which modifies the contents of theaccumulator. For each operation Xk, corresponding par-allel operations kA, 'kB are to be devised for the contentsof the check registers CRA and CRB. These paralleloperations which are carried out in the respective resi-due checkers will enable maintenance of the correctresidues, and therefore a biresidue code word by theend of each operation cycle. However, the errors may beintroduced due to malfunctions and these are to be de-coded and corrected. To enable computation in thepresence of single errors, all we have to do is to correcterrors located to the accumulator. The errors located toeither checker may be left uncorrected, but the controlshould prohibit further error correction of the accumu-lator. The decision of correcting an error in a checker ornot is usually based on the specific application of thecomputer and the willingness on the part of the designerto expend hardware for correction of the checkers.

PRACTICAL IMPLEMENTATIONThe basic processor organization we will consider

here is the same as in [II] (Fig. 2). Instead of one resi-due check circuit required for error detection, there will

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INPUT

IA

Fig. 1. Error-correction scheme.

Fig. 2. Basic processor organization.

Fig. 4. Residue checker.

OUTPUTBUS

TO ACC TO OUTPUT BUS

Fig. 5. Decoder, corrector.

INPUTBUS

01JTPUTBUS

Fig. 3. Processor and checker organization.

be two residue check circuits (one each for moduli Aand B). In addition, there will be a decoder, corrector,as shown in Fig. 1, to form the syndrome and to makethe correction on the accumulator outputs.

RESIDUE CHECKERSThe checkers A and B are logically identical except

that their residue bases are different. The residue gen-

erator, the residue manipulator, the residue register(RR), and the check register (CR) required for eachchecker are explained in detail in [11], hence, there willbe no need for repetition. However, there will be some

minor modifications. A block diagram for residuechecker A is given in Fig. 4.

DECODER, CORRECTOR

The syndrome generated by the checkers is first gatedinto syndrome registers (SRA, SRB). See Fig. 5. Thesyndrome decoder determines the form of error correc-

tion to be made. If the error is located to one of thecheckers, no correction is made on the check registers.Further correction is withheld until the necessary main-tenance is performed on the checker. If the error is lo-cated to the processor, the error correction involvessubtraction of the error value from the accumulator.However, for a certain class of errors, such as a flip-flopof the accumulator stuck at one or zero, the correction isnot possible by restoring the correct result. A rerun ofdiagnosis, location of such troubles, and masking tech-niques have to be used. These engineering details are

beyond the scope of the paper but have been success-

fully worked out in [5].

CONCLUSION

A biresidue code using moduli A =2-1, B = 2b -1 isshown to be capable of correcting single errors for arith-metic registers of size no greater than n = ab. However,if n = ab the residue manipulation and correction logic

ACCUMULATORCORRECTEDOUTPUT

INPUTBUS

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will be a lot simpler and hence less costly. A rough esti-miiate on the complexities of the processor, checkers, anddecoder, corrector are made. These estimates revealthat single-error correction can be achieved for costs no

greater than processor duplication. In comparison, withthe triplication and majority vote-taking scheme, theapplication of biresidue coding should be an attractivealternative.

Further work relating to biresidue codes is presentlyin progress at the University of Maryland. Preliminaryresults show that AN codes with large minimum dis-tance but small range for N, such as Mandelbaum-typecodes [9], can be converted to biresidue code form, andthereby codes of large minimum distance and largerange are conceived. That step could lead to a realiza-tion of practical size arithmetic units capable of mul-tiple-error correction.

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Propulsion Lab., Space Programs Summary 37.37, vol. 4, 1966.[2] D. T. Brown, "Error detecting and correcting binary codes for

arithmetic operations," IRE Trans. Electronic Computers, vol.EC-9, pp. 333-337, September 1960.

[31 R. T. Chien, "Linear codes for single error correction in binaryarithmetic and transmission," 1963 IEEE Natl. Conv. Rec., pt. 4,pp. 133-138.

14] J. M. Diamond, "Checking codes for digital computers," Proc.IRE (Correspondence), vol. 43, pp. 487-488, April 1955.

[5] 0. N. Garcia, "Error correction in parallel binary adders,"Proc. Southeastern Symp. on System Theory B-4, VirginiaPolytechnic Institute, Blacksburg, Va., May 1969.

[61 H. L. Garner, "Error codes for arithmetic operations," IEEETrans. Electronic Computers, vol. EC-15, pp. 763-770, October1966.

[71 -, "The residue number system," IRE Trans. ElectronicComputers. vol. EC-8, pp. 140-147, June 1959.

[8] D. S. Henderson, "Residue class error checking codes," Proc.16th Natl. Meeting of the Association for Computing Machinery,Los Angeles, Calif., September 1961.

[9] D. Mandelbaum, "Arithmetic codes with large distance," IEEETrans. Information Theory, vol. IT-13, pp. 237-242, April 1967.

[10] J. L. Massey, "Survey of residue coding for arithmetic errors,"Internatl. Computation Center Bull., vol. 3, October 1964.

[11] T. R. N. Rao, "Error-checking logic for arithmetic-type opera-tions of a processor," IEEE Trans. Computers, vol. C-17, pp.845-849, September 1968.

[12] W. W. Peterson, Error-Correcting Codes. New York: Wiley, andCambridge, Mass.: M.I.T. Press, 1961.

[13] N. S. Szabo and R. I. Tanaka, Residue Arithmetic and its Appli-cations to Computer Technology. New York: McGraw-Hill,1967.

[14] R. W. Watson, "Self-checked computations using residuearithmetic," Proc. IEEE, vol. 54, pp. 1920-1931, December 1966.

[15] , "Error detection and correction and other residue inter-acting operations in a redundant residue number system," Ph.D.dissertation, University of California, Berkeley, January 1965.

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